Core driver for register formats of imx1/imx21/imx27 processors.
The pins of those processors are grouped into ports. Each port has 32
pins. The pins mux configuration is controlled by registers with 1 or 2
bit per pin, depending on the specific control register.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The data structure of_match_ptr() protects is always compiled in.
Hence of_match_ptr() is not needed.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch fix the error handling in tb10x_pinctrl_probe():
- devm_ioremap_resource() return ERR_PTR() and never return NULL
- remove the dev_err call to avoid redundant error message
- pinctrl_register() returns NULL not ERR_PTR()
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The gpio interrupt controller on Rockchip socs can do edge triggers only
for single edges but not both. Nevertheless a lot of gpio users rely on
the availability of both-edge triggered interrupts - i.e. gpio-keys.
Therefore implement a solution similar to pinctrl-coh901 re-setting the
triggering edge depending on the gpio value in the interrupt demuxer.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Besides the pull registers sitting in a separate place, the rk3188 also
has the peculiarity that the pull registers of the first bank are split
and the first half is sitting in the register space of the pmu.
Therefore this adds a special bank-type for the first bank, to handle
the two register sources.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The check limiting bias options to supported ones is already
done thru rockchip_pinconf_pull_valid. Therefore this check is
redundant and can be removed.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There are Rockchip SoCs, namely the rk3188, that combine a set of
regular banks with banks that need special handling for some settings.
Therefore add the possibility for the driver to handle more than one
bank type.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Further investigation of the different Rockchip SoCs showed that
the differences especially in the pull settings are quite deep.
As further patches will show, the register layout for the pulls of
the rk3188 is quite strange. Also it is to assume, that later
Rockchip SoCs may introduce even more quirks in this regard, making
it hard to support all of those using the current generic pull_*
variables.
Therefore move the driver to hold the type of controller in an enum
and do the handling according to it in the necessary places. Also
instead of calculating the register in the get and set pull functions
move it to a type-specific callback.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs.
Used to control the pinmux and is a prerequisite for the GPIO driver.
Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Pierrick Hascoet <pierrick.hascoet@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds the infrastructure required to register non-linear gpio
ranges through gpiolib and the standard GPIO device tree bindings.
Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The AS3722 is a compact system PMU suitable for mobile phones, tablets etc.
Add a driver to support accessing the GPIO, pinmux and pin configuration
of 8 GPIO pins found on the ams AS3722 through pin control driver and
gpiolib.
The driver will register itself as the pincontrol driver and gpio driver.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
GPIO output value should be set after the GPIO interrupt is disabled.
Use BIT macro as well.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
[Edited commit message]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Also avoid use NULL pointer in error message.
v2-changes:
- use port pinter only after checking
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Palmas devices do not support the default bias configuration
and hence removing this option from valid pin config parameters.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dn and dp of USB1 can share with UART1(UART1 can route rx,tx to dn and dp pins of USB1).
here we add this pinmux capability.
USB1/UART1 mode selection has dedicated control register in RSC module, here we attach
the register offset of private data of related pin groups.
Signed-off-by: Rong Wang <Rong.Wang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
USP(Universal Serial Ports) can be UART as commit 5df831117b,
this patch defines the USP-based UART function pin groups for prima2.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
the old codes defined uart0_nostreamctrl_pins, but missed pingroup
and padmux definition for it. this patch fixes it.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Recent movement of all configurations of pin in the single call of
pin_config_set(), it is aborting configuration if BIAS_PULL_PIN_DEFAULT
is selected as return of configuration.
The original idea was to just avoid any update on register for pull up/down
configuration if this option is selected.
Fixing this by just bypassing any register update for BIAS_PULL_PIN_DEFAULT
and continuing the remaining configuration.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Palmas pinmux and pin configuration support the single pin level
configuration in place of pin group.
Hence it is only require to pin_config_{set|get} and do not require
pin_config_group_{set|get}. As core framework already check for
require APIs availability, it is not require to implement as dummy
for non-require ops and so removing it.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Markus Pargmann
Alexandre Belloni
Sachin Kamat
Wei Yongjun
Heiko Stübner
Roel Kluin
Christian Ruppert
Laxman Dewangan
Sonic Zhang
Linus Walleij
Rong Wang
Qipan Li