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[POWERPC] 4xx: Fix TLB 0 problem with CONFIG_SERIAL_TEXT_DEBUG

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Right now TLB entry 0 ist used as UART0 mapping for the early debug
output (via CONFIG_SERIAL_TEXT_DEBUG). This causes problems when many
TLB's get used upon Linux bootup (e.g. while PCIe scanning behind
bridges and/or switches on 440SPe platforms). This will overwrite the
TLB 0 entry and further debug output's may crash/hang the system.

This patch moves the early debug UART0 TLB entry from 0 to 62 as done
in arch/powerpc. This way it is in the "pinned" area and will not get
overwritten. Also the arch/ppc/mm/44x_mmu.c code is now synced with the
newer code from arch/powerpc.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Stefan Roese
2007-11-20 21:19:16 +11:00
committed by Josh Boyer
parent 4922566f03
commit f4151b9ba8
3 changed files with 23 additions and 36 deletions
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include/asm-ppc/mmu.h
+6
View File
@@ -383,6 +383,12 @@ typedef struct _P601_BAT {
#define BOOKE_PAGESZ_256GB 14
#define BOOKE_PAGESZ_1TB 15
#ifndef CONFIG_SERIAL_TEXT_DEBUG
#define PPC44x_EARLY_TLBS 1
#else
#define PPC44x_EARLY_TLBS 2
#endif
/*
* Freescale Book-E MMU support
*/