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Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (76 commits) [ARM] 4002/1: S3C24XX: leave parent IRQs unmasked [ARM] 4001/1: S3C24XX: shorten reboot time [ARM] 3983/2: remove unused argument to __bug() [ARM] 4000/1: Osiris: add third serial port in [ARM] 3999/1: RX3715: suspend to RAM support [ARM] 3998/1: VR1000: LED platform devices [ARM] 3995/1: iop13xx: add iop13xx support [ARM] 3968/1: iop13xx: add iop13xx_defconfig [ARM] Update mach-types [ARM] Allow gcc to optimise arm_add_memory a little more [ARM] 3991/1: i.MX/MX1 high resolution time source [ARM] 3990/1: i.MX/MX1 more precise PLL decode [ARM] 3986/1: H1940: suspend to RAM support [ARM] 3985/1: ixp4xx clocksource cleanup [ARM] 3984/1: ixp4xx/nslu2: Fix disk LED numbering (take 2) [ARM] 3994/1: ixp23xx: fix handling of pci master aborts [ARM] 3981/1: sched_clock for PXA2xx [ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit [ARM] 3979/1: extend the SA11x0 sched_clock implementation from 32 to 63 bit period [ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter ...
This commit is contained in:
Linus Torvalds
@@ -17,8 +17,6 @@
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#define __virt_to_bus(x) __virt_to_phys(x)
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#define __bus_to_virt(x) __phys_to_virt(x)
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#ifdef CONFIG_DISCONTIGMEM
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/*
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* The nodes are the followings:
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*
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@@ -27,42 +25,6 @@
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* node 2: 0xf800.0000 - 0xfbff.ffff
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* node 3: 0xfc00.0000 - 0xffff.ffff
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*/
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/*
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* Given a kernel address, find the home node of the underlying memory.
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*/
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#define KVADDR_TO_NID(addr) \
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(((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
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/*
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* Given a page frame number, convert it to a node id.
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*/
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#define PFN_TO_NID(pfn) \
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(((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
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/*
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* Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
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* and return the mem_map of that node.
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*/
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#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
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/*
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* Given a page frame number, find the owning node of the memory
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* and return the mem_map of that node.
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*/
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#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
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/*
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* Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
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* and returns the index corresponding to the appropriate page in the
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* node's mem_map.
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*/
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#define LOCAL_MAP_NR(addr) \
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(((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
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#define NODE_MAX_MEM_SHIFT 26
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#define NODE_MAX_MEM_SIZE (1 << NODE_MAX_MEM_SHIFT)
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#endif /* CONFIG_DISCONTIGMEM */
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#define NODE_MEM_SIZE_BITS 26
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#endif /* __ASM_ARCH_MEMORY_H */
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@@ -0,0 +1,53 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91_aic.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Advanced Interrupt Controller (AIC) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_AIC_H
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#define AT91_AIC_H
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#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
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#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
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#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
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#define AT91_AIC_SRCTYPE_LOW (0 << 5)
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#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
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#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
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#define AT91_AIC_SRCTYPE_RISING (3 << 5)
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#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
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#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
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#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
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#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
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#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
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#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
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#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
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#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
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#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
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#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
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#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
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#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
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#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
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#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
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#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
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#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
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#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
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#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
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#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
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#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
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#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
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#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
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#endif
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@@ -0,0 +1,45 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91_dbgu.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Debug Unit (DBGU) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_DBGU_H
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#define AT91_DBGU_H
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#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
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#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
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#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
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#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
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#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
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#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
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#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
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#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
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#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
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#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
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#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
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#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
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#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
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#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
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#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
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#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
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#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
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#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
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#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
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#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
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#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
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#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
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#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
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#endif
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@@ -0,0 +1,38 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91_ecc.h
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*
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* Error Corrected Code Controller (ECC) - System peripherals regsters.
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* Based on AT91SAM9260 datasheet revision B.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef AT91_ECC_H
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#define AT91_ECC_H
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#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
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#define AT91_ECC_RST (1 << 0) /* Reset parity */
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#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
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#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
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#define AT91_ECC_PAGESIZE_528 (0)
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#define AT91_ECC_PAGESIZE_1056 (1)
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#define AT91_ECC_PAGESIZE_2112 (2)
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#define AT91_ECC_PAGESIZE_4224 (3)
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#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
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#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
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#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
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#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
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#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
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#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
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#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
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#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
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#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
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#endif
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@@ -0,0 +1,148 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91_lcdc.h
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*
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* LCD Controller (LCDC).
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* Based on AT91SAM9261 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_LCDC_H
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#define AT91_LCDC_H
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#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */
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#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */
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#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */
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#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */
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#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */
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#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */
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#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */
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#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */
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#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */
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#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */
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#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */
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#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */
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#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */
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#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */
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#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */
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#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */
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#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */
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#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */
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#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */
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#define AT91_LCDC_DISTYPE_STNMONO (0 << 0)
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#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0)
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#define AT91_LCDC_DISTYPE_TFT (2 << 0)
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#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */
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#define AT91_LCDC_SCANMOD_SINGLE (0 << 2)
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#define AT91_LCDC_SCANMOD_DUAL (1 << 2)
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#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */
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#define AT91_LCDC_IFWIDTH_4 (0 << 3)
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#define AT91_LCDC_IFWIDTH_8 (1 << 3)
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#define AT91_LCDC_IFWIDTH_16 (2 << 3)
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#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */
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#define AT91_LCDC_PIXELSIZE_1 (0 << 5)
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#define AT91_LCDC_PIXELSIZE_2 (1 << 5)
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#define AT91_LCDC_PIXELSIZE_4 (2 << 5)
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#define AT91_LCDC_PIXELSIZE_8 (3 << 5)
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#define AT91_LCDC_PIXELSIZE_16 (4 << 5)
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#define AT91_LCDC_PIXELSIZE_24 (5 << 5)
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#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */
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#define AT91_LCDC_INVVD_NORMAL (0 << 8)
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#define AT91_LCDC_INVVD_INVERTED (1 << 8)
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#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */
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#define AT91_LCDC_INVFRAME_NORMAL (0 << 9)
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#define AT91_LCDC_INVFRAME_INVERTED (1 << 9)
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#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */
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#define AT91_LCDC_INVLINE_NORMAL (0 << 10)
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#define AT91_LCDC_INVLINE_INVERTED (1 << 10)
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#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */
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#define AT91_LCDC_INVCLK_NORMAL (0 << 11)
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#define AT91_LCDC_INVCLK_INVERTED (1 << 11)
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#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */
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#define AT91_LCDC_INVDVAL_NORMAL (0 << 12)
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#define AT91_LCDC_INVDVAL_INVERTED (1 << 12)
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#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */
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#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
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#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
|
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#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */
|
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#define AT91_LCDC_MEMOR_BIG (0 << 31)
|
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#define AT91_LCDC_MEMOR_LITTLE (1 << 31)
|
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#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */
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#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */
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#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */
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#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */
|
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#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */
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#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */
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#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */
|
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#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */
|
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#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */
|
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|
||||
#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */
|
||||
#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */
|
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#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */
|
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||||
#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */
|
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#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */
|
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#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */
|
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#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */
|
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#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */
|
||||
#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */
|
||||
#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */
|
||||
#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */
|
||||
#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */
|
||||
#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */
|
||||
#define AT91_LCDC_DP1_2_VAL (0xff)
|
||||
#define AT91_LCDC_DP4_7_VAL (0xfffffff)
|
||||
#define AT91_LCDC_DP3_5_VAL (0xfffff)
|
||||
#define AT91_LCDC_DP2_3_VAL (0xfff)
|
||||
#define AT91_LCDC_DP5_7_VAL (0xfffffff)
|
||||
#define AT91_LCDC_DP3_4_VAL (0xffff)
|
||||
#define AT91_LCDC_DP4_5_VAL (0xfffff)
|
||||
#define AT91_LCDC_DP6_7_VAL (0xfffffff)
|
||||
|
||||
#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */
|
||||
#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */
|
||||
#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */
|
||||
#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */
|
||||
|
||||
#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */
|
||||
#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */
|
||||
#define AT91_LCDC_PS_DIV1 (0 << 0)
|
||||
#define AT91_LCDC_PS_DIV2 (1 << 0)
|
||||
#define AT91_LCDC_PS_DIV4 (2 << 0)
|
||||
#define AT91_LCDC_PS_DIV8 (3 << 0)
|
||||
#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */
|
||||
#define AT91_LCDC_POL_NEGATIVE (0 << 2)
|
||||
#define AT91_LCDC_POL_POSITIVE (1 << 2)
|
||||
#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */
|
||||
#define AT91_LCDC_ENA_PWMDISABLE (0 << 3)
|
||||
#define AT91_LCDC_ENA_PWMENABLE (1 << 3)
|
||||
|
||||
#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */
|
||||
#define AT91_LCDC_CVAL (0xff) /* PWM compare value */
|
||||
|
||||
#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */
|
||||
#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */
|
||||
#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */
|
||||
#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */
|
||||
#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */
|
||||
#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */
|
||||
#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */
|
||||
#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */
|
||||
#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */
|
||||
#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */
|
||||
#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */
|
||||
|
||||
#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */
|
||||
|
||||
#endif
|
||||
+13
-11
@@ -1,11 +1,11 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
|
||||
* include/asm-arm/arch-at91rm9200/at91_mci.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* MultiMedia Card Interface (MCI) registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
* Based on AT91RM9200 datasheet revision F.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@@ -13,8 +13,8 @@
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91RM9200_MCI_H
|
||||
#define AT91RM9200_MCI_H
|
||||
#ifndef AT91_MCI_H
|
||||
#define AT91_MCI_H
|
||||
|
||||
#define AT91_MCI_CR 0x00 /* Control Register */
|
||||
#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
|
||||
@@ -25,10 +25,10 @@
|
||||
|
||||
#define AT91_MCI_MR 0x04 /* Mode Register */
|
||||
#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
|
||||
#define AT91_MCI_PWSDIV (3 << 8) /* Power Saving Divider */
|
||||
#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
|
||||
#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
|
||||
#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
|
||||
#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
|
||||
#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
|
||||
|
||||
#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
|
||||
#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
|
||||
@@ -43,8 +43,8 @@
|
||||
#define AT91_MCI_DTOMUL_1M (7 << 4)
|
||||
|
||||
#define AT91_MCI_SDCR 0x0c /* SD Card Register */
|
||||
#define AT91_MCI_SDCSEL (0xf << 0) /* SD Card Selector */
|
||||
#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
|
||||
#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
|
||||
#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
|
||||
|
||||
#define AT91_MCI_ARGR 0x10 /* Argument Register */
|
||||
|
||||
@@ -78,18 +78,20 @@
|
||||
|
||||
#define AT91_MCI_SR 0x40 /* Status Register */
|
||||
#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
|
||||
#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
|
||||
#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
|
||||
#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
|
||||
#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
|
||||
#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
|
||||
#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
|
||||
#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
|
||||
#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
|
||||
#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
|
||||
#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */
|
||||
#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
|
||||
#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
|
||||
#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
|
||||
#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
|
||||
#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
|
||||
#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
|
||||
#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
|
||||
#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
|
||||
#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */
|
||||
#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
|
||||
+3
-3
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
|
||||
* include/asm-arm/arch-at91rm9200/at91_pdc.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
@@ -13,8 +13,8 @@
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91RM9200_PDC_H
|
||||
#define AT91RM9200_PDC_H
|
||||
#ifndef AT91_PDC_H
|
||||
#define AT91_PDC_H
|
||||
|
||||
#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
|
||||
#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91_pio.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* Parallel I/O Controller (PIO) - System peripherals registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_PIO_H
|
||||
#define AT91_PIO_H
|
||||
|
||||
#define PIO_PER 0x00 /* Enable Register */
|
||||
#define PIO_PDR 0x04 /* Disable Register */
|
||||
#define PIO_PSR 0x08 /* Status Register */
|
||||
#define PIO_OER 0x10 /* Output Enable Register */
|
||||
#define PIO_ODR 0x14 /* Output Disable Register */
|
||||
#define PIO_OSR 0x18 /* Output Status Register */
|
||||
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
|
||||
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
|
||||
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
|
||||
#define PIO_SODR 0x30 /* Set Output Data Register */
|
||||
#define PIO_CODR 0x34 /* Clear Output Data Register */
|
||||
#define PIO_ODSR 0x38 /* Output Data Status Register */
|
||||
#define PIO_PDSR 0x3c /* Pin Data Status Register */
|
||||
#define PIO_IER 0x40 /* Interrupt Enable Register */
|
||||
#define PIO_IDR 0x44 /* Interrupt Disable Register */
|
||||
#define PIO_IMR 0x48 /* Interrupt Mask Register */
|
||||
#define PIO_ISR 0x4c /* Interrupt Status Register */
|
||||
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
|
||||
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
|
||||
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
|
||||
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
|
||||
#define PIO_PUER 0x64 /* Pull-up Enable Register */
|
||||
#define PIO_PUSR 0x68 /* Pull-up Status Register */
|
||||
#define PIO_ASR 0x70 /* Peripheral A Select Register */
|
||||
#define PIO_BSR 0x74 /* Peripheral B Select Register */
|
||||
#define PIO_ABSR 0x78 /* AB Status Register */
|
||||
#define PIO_OWER 0xa0 /* Output Write Enable Register */
|
||||
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
|
||||
#define PIO_OWSR 0xa8 /* Output Write Status Register */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91_pit.h
|
||||
*
|
||||
* Periodic Interval Timer (PIT) - System peripherals regsters.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_PIT_H
|
||||
#define AT91_PIT_H
|
||||
|
||||
#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
|
||||
#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
|
||||
#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
|
||||
#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
|
||||
|
||||
#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
|
||||
#define AT91_PIT_PITS (1 << 0) /* Timer Status */
|
||||
|
||||
#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
|
||||
#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
|
||||
#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
|
||||
#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91_pmc.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* Power Management Controller (PMC) - System peripherals registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_PMC_H
|
||||
#define AT91_PMC_H
|
||||
|
||||
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
|
||||
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
|
||||
|
||||
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
|
||||
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
|
||||
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
|
||||
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
|
||||
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
|
||||
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
|
||||
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
|
||||
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
|
||||
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
|
||||
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
|
||||
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
|
||||
|
||||
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
|
||||
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
|
||||
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
|
||||
|
||||
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
|
||||
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
||||
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
|
||||
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
||||
|
||||
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
|
||||
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
|
||||
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
|
||||
|
||||
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
|
||||
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
|
||||
#define AT91_PMC_DIV (0xff << 0) /* Divider */
|
||||
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
|
||||
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
|
||||
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
|
||||
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
|
||||
|
||||
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
|
||||
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
|
||||
#define AT91_PMC_CSS_SLOW (0 << 0)
|
||||
#define AT91_PMC_CSS_MAIN (1 << 0)
|
||||
#define AT91_PMC_CSS_PLLA (2 << 0)
|
||||
#define AT91_PMC_CSS_PLLB (3 << 0)
|
||||
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
|
||||
#define AT91_PMC_PRES_1 (0 << 2)
|
||||
#define AT91_PMC_PRES_2 (1 << 2)
|
||||
#define AT91_PMC_PRES_4 (2 << 2)
|
||||
#define AT91_PMC_PRES_8 (3 << 2)
|
||||
#define AT91_PMC_PRES_16 (4 << 2)
|
||||
#define AT91_PMC_PRES_32 (5 << 2)
|
||||
#define AT91_PMC_PRES_64 (6 << 2)
|
||||
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
|
||||
#define AT91_PMC_MDIV_1 (0 << 8)
|
||||
#define AT91_PMC_MDIV_2 (1 << 8)
|
||||
#define AT91_PMC_MDIV_3 (2 << 8)
|
||||
#define AT91_PMC_MDIV_4 (3 << 8)
|
||||
|
||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
|
||||
|
||||
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
|
||||
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
|
||||
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
|
||||
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
|
||||
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
||||
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
||||
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
|
||||
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
|
||||
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
||||
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91_rstc.h
|
||||
*
|
||||
* Reset Controller (RSTC) - System peripherals regsters.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_RSTC_H
|
||||
#define AT91_RSTC_H
|
||||
|
||||
#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
|
||||
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
|
||||
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
|
||||
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
|
||||
#define AT01_RSTC_KEY (0xff << 24) /* KEY Password */
|
||||
|
||||
#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
|
||||
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
|
||||
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
|
||||
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
|
||||
#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
|
||||
#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
|
||||
#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
|
||||
#define AT91_RSTC_RSTTYP_USER (4 << 8)
|
||||
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
|
||||
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
|
||||
|
||||
#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
|
||||
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
|
||||
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
|
||||
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
|
||||
#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,75 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91_rtc.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* Real Time Clock (RTC) - System peripheral registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_RTC_H
|
||||
#define AT91_RTC_H
|
||||
|
||||
#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
|
||||
#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
|
||||
#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
|
||||
#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
|
||||
#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
|
||||
#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
|
||||
#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
|
||||
#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
|
||||
#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
|
||||
#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
|
||||
#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
|
||||
#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
|
||||
|
||||
#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
|
||||
#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
|
||||
|
||||
#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
|
||||
#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
|
||||
#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
|
||||
#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
|
||||
#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
|
||||
|
||||
#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
|
||||
#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
|
||||
#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
|
||||
#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
|
||||
#define AT91_RTC_DAY (7 << 21) /* Current Day */
|
||||
#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
|
||||
|
||||
#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
|
||||
#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
|
||||
#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
|
||||
#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
|
||||
|
||||
#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
|
||||
#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
|
||||
#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
|
||||
|
||||
#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
|
||||
#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
|
||||
#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
|
||||
#define AT91_RTC_SECEV (1 << 2) /* Second Event */
|
||||
#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
|
||||
#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
|
||||
|
||||
#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
|
||||
#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
|
||||
#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
|
||||
#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
|
||||
#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
|
||||
#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
|
||||
#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
|
||||
#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91_rtt.h
|
||||
*
|
||||
* Real-time Timer (RTT) - System peripherals regsters.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_RTT_H
|
||||
#define AT91_RTT_H
|
||||
|
||||
#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */
|
||||
#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
|
||||
#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
|
||||
#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
|
||||
#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
|
||||
|
||||
#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */
|
||||
#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
|
||||
|
||||
#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */
|
||||
#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
|
||||
|
||||
#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */
|
||||
#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
|
||||
#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91_shdwc.h
|
||||
*
|
||||
* Shutdown Controller (SHDWC) - System peripherals regsters.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_SHDWC_H
|
||||
#define AT91_SHDWC_H
|
||||
|
||||
#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
|
||||
#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */
|
||||
#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */
|
||||
|
||||
#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
|
||||
#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
|
||||
#define AT91_SHDW_WKMODE0_NONE 0
|
||||
#define AT91_SHDW_WKMODE0_HIGH 1
|
||||
#define AT91_SHDW_WKMODE0_LOW 2
|
||||
#define AT91_SHDW_WKMODE0_ANYLEVEL 3
|
||||
#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
|
||||
#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
|
||||
|
||||
#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
|
||||
#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
|
||||
#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
|
||||
|
||||
#endif
|
||||
+4
-4
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
|
||||
* include/asm-arm/arch-at91rm9200/at91_spi.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
@@ -13,8 +13,8 @@
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91RM9200_SPI_H
|
||||
#define AT91RM9200_SPI_H
|
||||
#ifndef AT91_SPI_H
|
||||
#define AT91_SPI_H
|
||||
|
||||
#define AT91_SPI_CR 0x00 /* Control Register */
|
||||
#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
|
||||
@@ -28,7 +28,7 @@
|
||||
#define AT91_SPI_PS_FIXED (0 << 1)
|
||||
#define AT91_SPI_PS_VARIABLE (1 << 1)
|
||||
#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
|
||||
#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */
|
||||
#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
|
||||
#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
|
||||
#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
|
||||
#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
|
||||
+13
-3
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
|
||||
* include/asm-arm/arch-at91rm9200/at91_ssc.h
|
||||
*
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
@@ -12,8 +12,8 @@
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91RM9200_SSC_H
|
||||
#define AT91RM9200_SSC_H
|
||||
#ifndef AT91_SSC_H
|
||||
#define AT91_SSC_H
|
||||
|
||||
#define AT91_SSC_CR 0x00 /* Control Register */
|
||||
#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
|
||||
@@ -36,6 +36,10 @@
|
||||
#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
|
||||
#define AT91_SSC_CKI_FALLING (0 << 5)
|
||||
#define AT91_SSC_CK_RISING (1 << 5)
|
||||
#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */
|
||||
#define AT91_SSC_CKG_NONE (0 << 6)
|
||||
#define AT91_SSC_CKG_RFLOW (1 << 6)
|
||||
#define AT91_SSC_CKG_RFHIGH (2 << 6)
|
||||
#define AT91_SSC_START (0xf << 8) /* Start Selection */
|
||||
#define AT91_SSC_START_CONTINUOUS (0 << 8)
|
||||
#define AT91_SSC_START_TX_RX (1 << 8)
|
||||
@@ -45,6 +49,7 @@
|
||||
#define AT91_SSC_START_RISING_RF (5 << 8)
|
||||
#define AT91_SSC_START_LEVEL_RF (6 << 8)
|
||||
#define AT91_SSC_START_EDGE_RF (7 << 8)
|
||||
#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */
|
||||
#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
|
||||
#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
|
||||
|
||||
@@ -75,6 +80,9 @@
|
||||
#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
|
||||
#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
|
||||
|
||||
#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */
|
||||
#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */
|
||||
|
||||
#define AT91_SSC_SR 0x40 /* Status Register */
|
||||
#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
|
||||
#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
|
||||
@@ -84,6 +92,8 @@
|
||||
#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
|
||||
#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
|
||||
#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
|
||||
#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */
|
||||
#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */
|
||||
#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
|
||||
#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
|
||||
#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91_st.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* System Timer (ST) - System peripherals registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_ST_H
|
||||
#define AT91_ST_H
|
||||
|
||||
#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
|
||||
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
|
||||
|
||||
#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
|
||||
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
|
||||
|
||||
#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
|
||||
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
|
||||
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
|
||||
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
|
||||
|
||||
#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
|
||||
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
|
||||
|
||||
#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
|
||||
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
|
||||
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
|
||||
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
|
||||
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
|
||||
|
||||
#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
|
||||
#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
|
||||
#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
|
||||
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
|
||||
|
||||
#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
|
||||
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
|
||||
|
||||
#endif
|
||||
+3
-3
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
|
||||
* include/asm-arm/arch-at91rm9200/at91_tc.h
|
||||
*
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
@@ -12,8 +12,8 @@
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91RM9200_TC_H
|
||||
#define AT91RM9200_TC_H
|
||||
#ifndef AT91_TC_H
|
||||
#define AT91_TC_H
|
||||
|
||||
#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
|
||||
#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
|
||||
+5
-5
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
|
||||
* include/asm-arm/arch-at91rm9200/at91_twi.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
@@ -13,8 +13,8 @@
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91RM9200_TWI_H
|
||||
#define AT91RM9200_TWI_H
|
||||
#ifndef AT91_TWI_H
|
||||
#define AT91_TWI_H
|
||||
|
||||
#define AT91_TWI_CR 0x00 /* Control Register */
|
||||
#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
|
||||
@@ -43,8 +43,8 @@
|
||||
#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
|
||||
#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
|
||||
#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
|
||||
#define AT91_TWI_OVRE (1 << 6) /* Overrun Error */
|
||||
#define AT91_TWI_UNRE (1 << 7) /* Underrun Error */
|
||||
#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
|
||||
#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
|
||||
#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
|
||||
|
||||
#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
|
||||
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91_wdt.h
|
||||
*
|
||||
* Watchdog Timer (WDT) - System peripherals regsters.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_WDT_H
|
||||
#define AT91_WDT_H
|
||||
|
||||
#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
|
||||
#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
|
||||
#define AT91_WDT_KEY (0xff << 24) /* KEY Password */
|
||||
|
||||
#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
|
||||
#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
|
||||
#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
|
||||
#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
|
||||
#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
|
||||
#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
|
||||
#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
|
||||
#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
|
||||
#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
|
||||
|
||||
#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
|
||||
#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
|
||||
#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user