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Merge branch 'samsung/exynos5' into next/soc2
This commit is contained in:
Arnd Bergmann
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
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machine-$(CONFIG_ARCH_S5PC100) := s5pc100
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machine-$(CONFIG_ARCH_S5PV210) := s5pv210
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machine-$(CONFIG_ARCH_EXYNOS4) := exynos
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machine-$(CONFIG_ARCH_EXYNOS5) := exynos
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machine-$(CONFIG_ARCH_SA1100) := sa1100
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machine-$(CONFIG_ARCH_SHARK) := shark
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machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
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@@ -0,0 +1,26 @@
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/*
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* SAMSUNG SMDK5250 board device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/include/ "exynos5250.dtsi"
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/ {
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model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
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compatible = "samsung,smdk5250", "samsung,exynos5250";
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memory {
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reg = <0x40000000 0x80000000>;
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};
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chosen {
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bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
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};
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};
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@@ -0,0 +1,413 @@
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/*
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* SAMSUNG EXYNOS5250 SoC device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
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* EXYNOS5250 based board files can include this file and provide
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* values for board specfic bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
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* additional nodes can be added to this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "samsung,exynos5250";
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interrupt-parent = <&gic>;
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gic:interrupt-controller@10490000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x10490000 0x1000>, <0x10480000 0x100>;
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};
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watchdog {
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compatible = "samsung,s3c2410-wdt";
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reg = <0x101D0000 0x100>;
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interrupts = <0 42 0>;
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};
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rtc {
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compatible = "samsung,s3c6410-rtc";
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reg = <0x101E0000 0x100>;
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interrupts = <0 43 0>, <0 44 0>;
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};
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sdhci@12200000 {
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compatible = "samsung,exynos4210-sdhci";
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reg = <0x12200000 0x100>;
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interrupts = <0 75 0>;
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};
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sdhci@12210000 {
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compatible = "samsung,exynos4210-sdhci";
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reg = <0x12210000 0x100>;
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interrupts = <0 76 0>;
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};
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sdhci@12220000 {
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compatible = "samsung,exynos4210-sdhci";
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reg = <0x12220000 0x100>;
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interrupts = <0 77 0>;
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};
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sdhci@12230000 {
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compatible = "samsung,exynos4210-sdhci";
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reg = <0x12230000 0x100>;
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interrupts = <0 78 0>;
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};
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serial@12C00000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C00000 0x100>;
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interrupts = <0 51 0>;
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};
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serial@12C10000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C10000 0x100>;
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interrupts = <0 52 0>;
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};
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serial@12C20000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C20000 0x100>;
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interrupts = <0 53 0>;
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};
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serial@12C30000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C30000 0x100>;
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interrupts = <0 54 0>;
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};
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i2c@12C60000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C60000 0x100>;
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interrupts = <0 56 0>;
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};
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i2c@12C70000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C70000 0x100>;
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interrupts = <0 57 0>;
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};
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i2c@12C80000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C80000 0x100>;
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interrupts = <0 58 0>;
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};
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i2c@12C90000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C90000 0x100>;
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interrupts = <0 59 0>;
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};
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i2c@12CA0000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12CA0000 0x100>;
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interrupts = <0 60 0>;
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};
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i2c@12CB0000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12CB0000 0x100>;
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interrupts = <0 61 0>;
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};
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i2c@12CC0000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12CC0000 0x100>;
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interrupts = <0 62 0>;
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};
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i2c@12CD0000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12CD0000 0x100>;
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interrupts = <0 63 0>;
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus";
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interrupt-parent = <&gic>;
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ranges;
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pdma0: pdma@121A0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121A0000 0x1000>;
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interrupts = <0 34 0>;
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};
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pdma1: pdma@121B0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121B0000 0x1000>;
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interrupts = <0 35 0>;
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};
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mdma0: pdma@10800000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x10800000 0x1000>;
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interrupts = <0 33 0>;
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};
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mdma1: pdma@11C10000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x11C10000 0x1000>;
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interrupts = <0 124 0>;
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};
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};
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gpio-controllers {
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#address-cells = <1>;
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#size-cells = <1>;
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gpio-controller;
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ranges;
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gpa0: gpio-controller@11400000 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x11400000 0x20>;
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#gpio-cells = <4>;
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};
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gpa1: gpio-controller@11400020 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x11400020 0x20>;
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#gpio-cells = <4>;
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};
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gpa2: gpio-controller@11400040 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x11400040 0x20>;
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#gpio-cells = <4>;
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};
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gpb0: gpio-controller@11400060 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x11400060 0x20>;
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#gpio-cells = <4>;
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};
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gpb1: gpio-controller@11400080 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x11400080 0x20>;
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#gpio-cells = <4>;
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};
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gpb2: gpio-controller@114000A0 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x114000A0 0x20>;
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#gpio-cells = <4>;
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};
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gpb3: gpio-controller@114000C0 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x114000C0 0x20>;
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#gpio-cells = <4>;
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};
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gpc0: gpio-controller@114000E0 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x114000E0 0x20>;
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#gpio-cells = <4>;
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};
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gpc1: gpio-controller@11400100 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x11400100 0x20>;
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#gpio-cells = <4>;
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};
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gpc2: gpio-controller@11400120 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x11400120 0x20>;
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#gpio-cells = <4>;
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};
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gpc3: gpio-controller@11400140 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x11400140 0x20>;
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#gpio-cells = <4>;
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||||
};
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gpd0: gpio-controller@11400160 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x11400160 0x20>;
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#gpio-cells = <4>;
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};
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gpd1: gpio-controller@11400180 {
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compatible = "samsung,exynos4-gpio";
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reg = <0x11400180 0x20>;
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||||
#gpio-cells = <4>;
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||||
};
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gpy0: gpio-controller@114001A0 {
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||||
compatible = "samsung,exynos4-gpio";
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||||
reg = <0x114001A0 0x20>;
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||||
#gpio-cells = <4>;
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};
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gpy1: gpio-controller@114001C0 {
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||||
compatible = "samsung,exynos4-gpio";
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||||
reg = <0x114001C0 0x20>;
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||||
#gpio-cells = <4>;
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||||
};
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||||
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||||
gpy2: gpio-controller@114001E0 {
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||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114001E0 0x20>;
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||||
#gpio-cells = <4>;
|
||||
};
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||||
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||||
gpy3: gpio-controller@11400200 {
|
||||
compatible = "samsung,exynos4-gpio";
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||||
reg = <0x11400200 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy4: gpio-controller@11400220 {
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||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400220 0x20>;
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||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy5: gpio-controller@11400240 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400240 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy6: gpio-controller@11400260 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400260 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx0: gpio-controller@11400C00 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C00 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx1: gpio-controller@11400C20 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C20 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx2: gpio-controller@11400C40 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C40 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx3: gpio-controller@11400C60 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C60 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe0: gpio-controller@13400000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe1: gpio-controller@13400020 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400020 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpf0: gpio-controller@13400040 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400040 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpf1: gpio-controller@13400060 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400060 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpg0: gpio-controller@13400080 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400080 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpg1: gpio-controller@134000A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x134000A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpg2: gpio-controller@134000C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x134000C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gph0: gpio-controller@134000E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x134000E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gph1: gpio-controller@13400100 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400100 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv0: gpio-controller@10D10000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv1: gpio-controller@10D10020 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10020 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv2: gpio-controller@10D10040 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10040 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv3: gpio-controller@10D10060 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10060 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv4: gpio-controller@10D10080 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10080 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpz: gpio-controller@03860000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x03860000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -11,18 +11,19 @@ if ARCH_EXYNOS
|
||||
|
||||
menu "SAMSUNG EXYNOS SoCs Support"
|
||||
|
||||
choice
|
||||
prompt "EXYNOS System Type"
|
||||
default ARCH_EXYNOS4
|
||||
|
||||
config ARCH_EXYNOS4
|
||||
bool "SAMSUNG EXYNOS4"
|
||||
default y
|
||||
select HAVE_SMP
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
help
|
||||
Samsung EXYNOS4 SoCs based systems
|
||||
|
||||
endchoice
|
||||
config ARCH_EXYNOS5
|
||||
bool "SAMSUNG EXYNOS5"
|
||||
select HAVE_SMP
|
||||
help
|
||||
Samsung EXYNOS5 (Cortex-A15) SoC based systems
|
||||
|
||||
comment "EXYNOS SoCs"
|
||||
|
||||
@@ -41,6 +42,7 @@ config SOC_EXYNOS4212
|
||||
bool "SAMSUNG EXYNOS4212"
|
||||
default y
|
||||
depends on ARCH_EXYNOS4
|
||||
select SAMSUNG_DMADEV
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
help
|
||||
@@ -50,9 +52,17 @@ config SOC_EXYNOS4412
|
||||
bool "SAMSUNG EXYNOS4412"
|
||||
default y
|
||||
depends on ARCH_EXYNOS4
|
||||
select SAMSUNG_DMADEV
|
||||
help
|
||||
Enable EXYNOS4412 SoC support
|
||||
|
||||
config SOC_EXYNOS5250
|
||||
bool "SAMSUNG EXYNOS5250"
|
||||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
help
|
||||
Enable EXYNOS5250 SoC support
|
||||
|
||||
config EXYNOS4_MCT
|
||||
bool
|
||||
default y
|
||||
@@ -333,6 +343,7 @@ config MACH_SMDK4212
|
||||
select SAMSUNG_DEV_BACKLIGHT
|
||||
select SAMSUNG_DEV_KEYPAD
|
||||
select SAMSUNG_DEV_PWM
|
||||
select EXYNOS4_DEV_DMA
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_I2C3
|
||||
select EXYNOS4_SETUP_I2C7
|
||||
@@ -351,7 +362,7 @@ config MACH_SMDK4412
|
||||
Machine support for Samsung SMDK4412
|
||||
endif
|
||||
|
||||
comment "Flattened Device Tree based board for Exynos4 based SoC"
|
||||
comment "Flattened Device Tree based board for EXYNOS SoCs"
|
||||
|
||||
config MACH_EXYNOS4_DT
|
||||
bool "Samsung Exynos4 Machine using device tree"
|
||||
@@ -365,6 +376,15 @@ config MACH_EXYNOS4_DT
|
||||
Note: This is under development and not all peripherals can be supported
|
||||
with this machine file.
|
||||
|
||||
config MACH_EXYNOS5_DT
|
||||
bool "SAMSUNG EXYNOS5 Machine using device tree"
|
||||
select SOC_EXYNOS5250
|
||||
select USE_OF
|
||||
select ARM_AMBA
|
||||
help
|
||||
Machine support for Samsung Exynos4 machine with device tree enabled.
|
||||
Select this if a fdt blob is available for the EXYNOS4 SoC based board.
|
||||
|
||||
if ARCH_EXYNOS4
|
||||
|
||||
comment "Configuration for HSMMC 8-bit bus width"
|
||||
|
||||
@@ -12,7 +12,9 @@ obj- :=
|
||||
|
||||
# Core
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += common.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
|
||||
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
|
||||
|
||||
@@ -40,9 +42,11 @@ obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
|
||||
obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
|
||||
|
||||
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
|
||||
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
|
||||
|
||||
# device support
|
||||
|
||||
obj-y += dev-uart.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
|
||||
@@ -51,7 +55,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Header file for exynos4 clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H __FILE__
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
extern struct clksrc_clk exynos4_clk_aclk_133;
|
||||
extern struct clksrc_clk exynos4_clk_mout_mpll;
|
||||
|
||||
extern struct clksrc_sources exynos4_clkset_mout_corebus;
|
||||
extern struct clksrc_sources exynos4_clkset_group;
|
||||
|
||||
extern struct clk *exynos4_clkset_aclk_top_list[];
|
||||
extern struct clk *exynos4_clkset_group_list[];
|
||||
|
||||
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
@@ -1,7 +1,5 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-exynos4/clock-exynos4210.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4210 - Clock support
|
||||
@@ -28,20 +26,20 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/exynos4-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4210_clock_save[] = {
|
||||
SAVE_ITEM(S5P_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKSRC_LCD1),
|
||||
SAVE_ITEM(S5P_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKDIV_LCD1),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
|
||||
|
||||
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
|
||||
return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &clkset_mout_corebus,
|
||||
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
||||
.sources = &exynos4_clkset_mout_corebus,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
|
||||
.enable = exynos4_clksrc_mask_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
||||
.sources = &exynos4_clkset_group,
|
||||
.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
|
||||
{
|
||||
.name = "sataphy",
|
||||
.id = -1,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sata",
|
||||
.id = -1,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
@@ -117,7 +115,7 @@ static void exynos4210_clock_resume(void)
|
||||
#define exynos4210_clock_resume NULL
|
||||
#endif
|
||||
|
||||
struct syscore_ops exynos4210_clock_syscore_ops = {
|
||||
static struct syscore_ops exynos4210_clock_syscore_ops = {
|
||||
.suspend = exynos4210_clock_suspend,
|
||||
.resume = exynos4210_clock_resume,
|
||||
};
|
||||
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
|
||||
clk_mout_mpll.reg_src.shift = 8;
|
||||
clk_mout_mpll.reg_src.size = 1;
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 8;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
@@ -1,7 +1,5 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-exynos4/clock-exynos4212.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4212 - Clock support
|
||||
@@ -28,22 +26,22 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/exynos4-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4212_clock_save[] = {
|
||||
SAVE_ITEM(S5P_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct clk *clk_src_mpll_user_list[] = {
|
||||
[0] = &clk_fin_mpll,
|
||||
[1] = &clk_mout_mpll.clk,
|
||||
[1] = &exynos4_clk_mout_mpll.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clk_src_mpll_user = {
|
||||
@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
|
||||
.name = "mout_mpll_user",
|
||||
},
|
||||
.sources = &clk_src_mpll_user,
|
||||
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
@@ -89,7 +87,7 @@ static void exynos4212_clock_resume(void)
|
||||
#define exynos4212_clock_resume NULL
|
||||
#endif
|
||||
|
||||
struct syscore_ops exynos4212_clock_syscore_ops = {
|
||||
static struct syscore_ops exynos4212_clock_syscore_ops = {
|
||||
.suspend = exynos4212_clock_suspend,
|
||||
.resume = exynos4212_clock_resume,
|
||||
};
|
||||
@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
|
||||
int ptr;
|
||||
|
||||
/* usbphy1 is removed */
|
||||
clkset_group_list[4] = NULL;
|
||||
exynos4_clkset_group_list[4] = NULL;
|
||||
|
||||
/* mout_mpll_user is used */
|
||||
clkset_group_list[6] = &clk_mout_mpll_user.clk;
|
||||
clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
|
||||
exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
|
||||
exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
|
||||
|
||||
clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
|
||||
clk_mout_mpll.reg_src.shift = 12;
|
||||
clk_mout_mpll.reg_src.size = 1;
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 12;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+355
-94
File diff suppressed because it is too large
Load Diff
@@ -12,30 +12,44 @@
|
||||
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
|
||||
extern struct sys_timer exynos4_timer;
|
||||
|
||||
void exynos_init_io(struct map_desc *mach_desc, int size);
|
||||
void exynos4_init_irq(void);
|
||||
void exynos5_init_irq(void);
|
||||
void exynos4_restart(char mode, const char *cmd);
|
||||
void exynos5_restart(char mode, const char *cmd);
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS4
|
||||
void exynos4_register_clocks(void);
|
||||
void exynos4_setup_clocks(void);
|
||||
|
||||
void exynos4210_register_clocks(void);
|
||||
void exynos4212_register_clocks(void);
|
||||
#else
|
||||
#define exynos4_register_clocks()
|
||||
#define exynos4_setup_clocks()
|
||||
#endif
|
||||
|
||||
void exynos4_restart(char mode, const char *cmd);
|
||||
|
||||
extern struct sys_timer exynos4_timer;
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS
|
||||
extern int exynos_init(void);
|
||||
extern void exynos4_map_io(void);
|
||||
extern void exynos4_init_clocks(int xtal);
|
||||
extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
#ifdef CONFIG_ARCH_EXYNOS5
|
||||
void exynos5_register_clocks(void);
|
||||
void exynos5_setup_clocks(void);
|
||||
|
||||
#else
|
||||
#define exynos4_init_clocks NULL
|
||||
#define exynos4_init_uarts NULL
|
||||
#define exynos4_map_io NULL
|
||||
#define exynos_init NULL
|
||||
#define exynos5_register_clocks()
|
||||
#define exynos5_setup_clocks()
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_EXYNOS4210
|
||||
void exynos4210_register_clocks(void);
|
||||
|
||||
#else
|
||||
#define exynos4210_register_clocks()
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_EXYNOS4212
|
||||
void exynos4212_register_clocks(void);
|
||||
|
||||
#else
|
||||
#define exynos4212_register_clocks()
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
|
||||
|
||||
@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_SATA,
|
||||
.end = IRQ_SATA,
|
||||
.start = EXYNOS4_IRQ_SATA,
|
||||
.end = EXYNOS4_IRQ_SATA,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[4] = {
|
||||
.start = IRQ_AC97,
|
||||
.end = IRQ_AC97,
|
||||
.start = EXYNOS4_IRQ_AC97,
|
||||
.end = EXYNOS4_IRQ_AC97,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Base EXYNOS UART resource and device definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
#define EXYNOS_UART_RESOURCE(_series, _nr) \
|
||||
static struct resource exynos##_series##_uart##_nr##_resource[] = { \
|
||||
[0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \
|
||||
[1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \
|
||||
};
|
||||
|
||||
EXYNOS_UART_RESOURCE(4, 0)
|
||||
EXYNOS_UART_RESOURCE(4, 1)
|
||||
EXYNOS_UART_RESOURCE(4, 2)
|
||||
EXYNOS_UART_RESOURCE(4, 3)
|
||||
|
||||
struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
|
||||
[0] = {
|
||||
.resources = exynos4_uart0_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart0_resource),
|
||||
},
|
||||
[1] = {
|
||||
.resources = exynos4_uart1_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart1_resource),
|
||||
},
|
||||
[2] = {
|
||||
.resources = exynos4_uart2_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart2_resource),
|
||||
},
|
||||
[3] = {
|
||||
.resources = exynos4_uart3_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
|
||||
},
|
||||
};
|
||||
|
||||
EXYNOS_UART_RESOURCE(5, 0)
|
||||
EXYNOS_UART_RESOURCE(5, 1)
|
||||
EXYNOS_UART_RESOURCE(5, 2)
|
||||
EXYNOS_UART_RESOURCE(5, 3)
|
||||
|
||||
struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
|
||||
[0] = {
|
||||
.resources = exynos5_uart0_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
|
||||
},
|
||||
[1] = {
|
||||
.resources = exynos5_uart1_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
|
||||
},
|
||||
[2] = {
|
||||
.resources = exynos5_uart2_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart2_resource),
|
||||
},
|
||||
[3] = {
|
||||
.resources = exynos5_uart3_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
|
||||
},
|
||||
};
|
||||
+113
-12
@@ -29,6 +29,7 @@
|
||||
#include <asm/irq.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/irqs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
@@ -36,7 +37,7 @@
|
||||
|
||||
static u64 dma_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
u8 pdma0_peri[] = {
|
||||
static u8 exynos4210_pdma0_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM2_RX,
|
||||
@@ -69,15 +70,47 @@ u8 pdma0_peri[] = {
|
||||
DMACH_AC97_PCMOUT,
|
||||
};
|
||||
|
||||
struct dma_pl330_platdata exynos4_pdma0_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
|
||||
.peri_id = pdma0_peri,
|
||||
static u8 exynos4212_pdma0_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM2_RX,
|
||||
DMACH_PCM2_TX,
|
||||
DMACH_MIPI_HSI0,
|
||||
DMACH_MIPI_HSI1,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI2_RX,
|
||||
DMACH_SPI2_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S2_RX,
|
||||
DMACH_I2S2_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART2_RX,
|
||||
DMACH_UART2_TX,
|
||||
DMACH_UART4_RX,
|
||||
DMACH_UART4_TX,
|
||||
DMACH_SLIMBUS0_RX,
|
||||
DMACH_SLIMBUS0_TX,
|
||||
DMACH_SLIMBUS2_RX,
|
||||
DMACH_SLIMBUS2_TX,
|
||||
DMACH_SLIMBUS4_RX,
|
||||
DMACH_SLIMBUS4_TX,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_PCMOUT,
|
||||
DMACH_MIPI_HSI4,
|
||||
DMACH_MIPI_HSI5,
|
||||
};
|
||||
|
||||
AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0,
|
||||
{IRQ_PDMA0}, &exynos4_pdma0_pdata);
|
||||
struct dma_pl330_platdata exynos4_pdma0_pdata;
|
||||
|
||||
u8 pdma1_peri[] = {
|
||||
static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
|
||||
EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
|
||||
|
||||
static u8 exynos4210_pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM1_RX,
|
||||
@@ -105,19 +138,84 @@ u8 pdma1_peri[] = {
|
||||
DMACH_SLIMBUS5_TX,
|
||||
};
|
||||
|
||||
struct dma_pl330_platdata exynos4_pdma1_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
|
||||
.peri_id = pdma1_peri,
|
||||
static u8 exynos4212_pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_PCM1_TX,
|
||||
DMACH_MIPI_HSI2,
|
||||
DMACH_MIPI_HSI3,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S1_RX,
|
||||
DMACH_I2S1_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
DMACH_UART1_TX,
|
||||
DMACH_UART3_RX,
|
||||
DMACH_UART3_TX,
|
||||
DMACH_SLIMBUS1_RX,
|
||||
DMACH_SLIMBUS1_TX,
|
||||
DMACH_SLIMBUS3_RX,
|
||||
DMACH_SLIMBUS3_TX,
|
||||
DMACH_SLIMBUS5_RX,
|
||||
DMACH_SLIMBUS5_TX,
|
||||
DMACH_SLIMBUS0AUX_RX,
|
||||
DMACH_SLIMBUS0AUX_TX,
|
||||
DMACH_SPDIF,
|
||||
DMACH_MIPI_HSI6,
|
||||
DMACH_MIPI_HSI7,
|
||||
};
|
||||
|
||||
AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1,
|
||||
{IRQ_PDMA1}, &exynos4_pdma1_pdata);
|
||||
static struct dma_pl330_platdata exynos4_pdma1_pdata;
|
||||
|
||||
static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
|
||||
EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
|
||||
|
||||
static u8 mdma_peri[] = {
|
||||
DMACH_MTOM_0,
|
||||
DMACH_MTOM_1,
|
||||
DMACH_MTOM_2,
|
||||
DMACH_MTOM_3,
|
||||
DMACH_MTOM_4,
|
||||
DMACH_MTOM_5,
|
||||
DMACH_MTOM_6,
|
||||
DMACH_MTOM_7,
|
||||
};
|
||||
|
||||
static struct dma_pl330_platdata exynos4_mdma1_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(mdma_peri),
|
||||
.peri_id = mdma_peri,
|
||||
};
|
||||
|
||||
static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
|
||||
EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
|
||||
|
||||
static int __init exynos4_dma_init(void)
|
||||
{
|
||||
if (of_have_populated_dt())
|
||||
return 0;
|
||||
|
||||
if (soc_is_exynos4210()) {
|
||||
exynos4_pdma0_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4210_pdma0_peri);
|
||||
exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
|
||||
exynos4_pdma1_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4210_pdma1_peri);
|
||||
exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
|
||||
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
|
||||
exynos4_pdma0_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4212_pdma0_peri);
|
||||
exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
|
||||
exynos4_pdma1_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4212_pdma1_peri);
|
||||
exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
|
||||
}
|
||||
|
||||
dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
|
||||
amba_device_register(&exynos4_pdma0_device, &iomem_resource);
|
||||
@@ -126,6 +224,9 @@ static int __init exynos4_dma_init(void)
|
||||
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
|
||||
amba_device_register(&exynos4_pdma1_device, &iomem_resource);
|
||||
|
||||
dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
|
||||
amba_device_register(&exynos4_mdma1_device, &iomem_resource);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos4_dma_init);
|
||||
|
||||
@@ -21,8 +21,13 @@
|
||||
*/
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
ldr \rp, = S3C_PA_UART
|
||||
ldr \rv, = S3C_VA_UART
|
||||
mov \rp, #0x10000000
|
||||
ldr \rp, [\rp, #0x0]
|
||||
and \rp, \rp, #0xf00000
|
||||
teq \rp, #0x500000 @@ EXYNOS5
|
||||
ldreq \rp, =EXYNOS5_PA_UART
|
||||
movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
|
||||
ldr \rv, =S3C_VA_UART
|
||||
#if CONFIG_DEBUG_S3C_UART != 0
|
||||
add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
|
||||
add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
|
||||
|
||||
@@ -1,43 +0,0 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Header file for exynos4 clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H __FILE__
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
extern struct clk clk_sclk_hdmi27m;
|
||||
extern struct clk clk_sclk_usbphy0;
|
||||
extern struct clk clk_sclk_usbphy1;
|
||||
extern struct clk clk_sclk_hdmiphy;
|
||||
|
||||
extern struct clksrc_clk clk_sclk_apll;
|
||||
extern struct clksrc_clk clk_mout_mpll;
|
||||
extern struct clksrc_clk clk_aclk_133;
|
||||
extern struct clksrc_clk clk_mout_epll;
|
||||
extern struct clksrc_clk clk_sclk_vpll;
|
||||
|
||||
extern struct clk *clkset_corebus_list[];
|
||||
extern struct clksrc_sources clkset_mout_corebus;
|
||||
|
||||
extern struct clk *clkset_aclk_top_list[];
|
||||
extern struct clksrc_sources clkset_aclk;
|
||||
|
||||
extern struct clk *clkset_group_list[];
|
||||
extern struct clksrc_sources clkset_group;
|
||||
|
||||
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user