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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Catalin Marinas:
"Mostly refactoring/clean-up:
- CPU ops and PSCI (Power State Coordination Interface) refactoring
following the merging of the arm64 ACPI support, together with
handling of Trusted (secure) OS instances
- Using fixmap for permanent FDT mapping, removing the initial dtb
placement requirements (within 512MB from the start of the kernel
image). This required moving the FDT self reservation out of the
memreserve processing
- Idmap (1:1 mapping used for MMU on/off) handling clean-up
- Removing flush_cache_all() - not safe on ARM unless the MMU is off.
Last stages of CPU power down/up are handled by firmware already
- "Alternatives" (run-time code patching) refactoring and support for
immediate branch patching, GICv3 CPU interface access
- User faults handling clean-up
And some fixes:
- Fix for VDSO building with broken ELF toolchains
- Fix another case of init_mm.pgd usage for user mappings (during
ASID roll-over broadcasting)
- Fix for FPSIMD reloading after CPU hotplug
- Fix for missing syscall trace exit
- Workaround for .inst asm bug
- Compat fix for switching the user tls tpidr_el0 register"
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (42 commits)
arm64: use private ratelimit state along with show_unhandled_signals
arm64: show unhandled SP/PC alignment faults
arm64: vdso: work-around broken ELF toolchains in Makefile
arm64: kernel: rename __cpu_suspend to keep it aligned with arm
arm64: compat: print compat_sp instead of sp
arm64: mm: Fix freeing of the wrong memmap entries with !SPARSEMEM_VMEMMAP
arm64: entry: fix context tracking for el0_sp_pc
arm64: defconfig: enable memtest
arm64: mm: remove reference to tlb.S from comment block
arm64: Do not attempt to use init_mm in reset_context()
arm64: KVM: Switch vgic save/restore to alternative_insn
arm64: alternative: Introduce feature for GICv3 CPU interface
arm64: psci: fix !CONFIG_HOTPLUG_CPU build warning
arm64: fix bug for reloading FPSIMD state after CPU hotplug.
arm64: kernel thread don't need to save fpsimd context.
arm64: fix missing syscall trace exit
arm64: alternative: Work around .inst assembler bugs
arm64: alternative: Merge alternative-asm.h into alternative.h
arm64: alternative: Allow immediate branch as alternative instruction
arm64: Rework alternate sequence for ARM erratum 845719
...
This commit is contained in:
Linus Torvalds
@@ -45,11 +45,13 @@ sees fit.)
|
||||
|
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Requirement: MANDATORY
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The device tree blob (dtb) must be placed on an 8-byte boundary within
|
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the first 512 megabytes from the start of the kernel image and must not
|
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cross a 2-megabyte boundary. This is to allow the kernel to map the
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blob using a single section mapping in the initial page tables.
|
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The device tree blob (dtb) must be placed on an 8-byte boundary and must
|
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not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
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using blocks of up to 2 megabytes in size, it must not be placed within
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any 2M region which must be mapped with any specific attributes.
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NOTE: versions prior to v4.2 also require that the DTB be placed within
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the 512 MB region starting at text_offset bytes below the kernel Image.
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3. Decompress the kernel image
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------------------------------
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@@ -218,11 +218,6 @@ static inline int kvm_arch_dev_ioctl_check_extension(long ext)
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return 0;
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}
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static inline void vgic_arch_setup(const struct vgic_params *vgic)
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{
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BUG_ON(vgic->type != VGIC_V2);
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}
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int kvm_perf_init(void);
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int kvm_perf_teardown(void);
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@@ -24,6 +24,8 @@
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#include <asm/kvm_psci.h>
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#include <asm/kvm_host.h>
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#include <uapi/linux/psci.h>
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/*
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* This is an implementation of the Power State Coordination Interface
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* as described in ARM document number ARM DEN 0022A.
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@@ -268,6 +268,7 @@ void __init arm_memblock_init(const struct machine_desc *mdesc)
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if (mdesc->reserve)
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mdesc->reserve();
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early_init_fdt_reserve_self();
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early_init_fdt_scan_reserved_mem();
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/* reserve memory for DMA contiguous allocations */
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@@ -72,6 +72,7 @@ config ARM64
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select HAVE_RCU_TABLE_FREE
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select HAVE_SYSCALL_TRACEPOINTS
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select IRQ_DOMAIN
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select IRQ_FORCED_THREADING
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select MODULES_USE_ELF_RELA
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select NO_BOOTMEM
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select OF
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@@ -180,6 +180,7 @@ CONFIG_LOCKUP_DETECTOR=y
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# CONFIG_SCHED_DEBUG is not set
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# CONFIG_DEBUG_PREEMPT is not set
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# CONFIG_FTRACE is not set
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CONFIG_MEMTEST=y
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CONFIG_SECURITY=y
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CONFIG_CRYPTO_ANSI_CPRNG=y
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CONFIG_ARM64_CRYPTO=y
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@@ -16,6 +16,7 @@
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#include <linux/irqchip/arm-gic-acpi.h>
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#include <asm/cputype.h>
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#include <asm/psci.h>
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#include <asm/smp_plat.h>
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/* Basic configuration for ACPI */
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@@ -39,18 +40,6 @@ extern int acpi_disabled;
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extern int acpi_noirq;
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extern int acpi_pci_disabled;
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/* 1 to indicate PSCI 0.2+ is implemented */
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static inline bool acpi_psci_present(void)
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{
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return acpi_gbl_FADT.arm_boot_flags & ACPI_FADT_PSCI_COMPLIANT;
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}
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/* 1 to indicate HVC must be used instead of SMC as the PSCI conduit */
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static inline bool acpi_psci_use_hvc(void)
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{
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return acpi_gbl_FADT.arm_boot_flags & ACPI_FADT_PSCI_USE_HVC;
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}
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static inline void disable_acpi(void)
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{
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acpi_disabled = 1;
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@@ -88,9 +77,11 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) { }
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void __init acpi_init_cpus(void);
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#else
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static inline bool acpi_psci_present(void) { return false; }
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static inline bool acpi_psci_use_hvc(void) { return false; }
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static inline void acpi_init_cpus(void) { }
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#endif /* CONFIG_ACPI */
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static inline const char *acpi_get_enable_method(int cpu)
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{
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return acpi_psci_present() ? "psci" : NULL;
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}
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#endif /*_ASM_ACPI_H*/
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@@ -1,29 +0,0 @@
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#ifndef __ASM_ALTERNATIVE_ASM_H
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#define __ASM_ALTERNATIVE_ASM_H
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#ifdef __ASSEMBLY__
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.macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len
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.word \orig_offset - .
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.word \alt_offset - .
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.hword \feature
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.byte \orig_len
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.byte \alt_len
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.endm
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.macro alternative_insn insn1 insn2 cap
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661: \insn1
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662: .pushsection .altinstructions, "a"
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altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f
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.popsection
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.pushsection .altinstr_replacement, "ax"
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663: \insn2
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664: .popsection
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.if ((664b-663b) != (662b-661b))
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.error "Alternatives instruction length mismatch"
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.endif
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.endm
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#endif /* __ASSEMBLY__ */
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|
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#endif /* __ASM_ALTERNATIVE_ASM_H */
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@@ -1,6 +1,8 @@
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#ifndef __ASM_ALTERNATIVE_H
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#define __ASM_ALTERNATIVE_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/stddef.h>
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#include <linux/stringify.h>
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@@ -24,7 +26,20 @@ void free_alternatives_memory(void);
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" .byte 662b-661b\n" /* source len */ \
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" .byte 664f-663f\n" /* replacement len */
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/* alternative assembly primitive: */
|
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/*
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* alternative assembly primitive:
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*
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* If any of these .org directive fail, it means that insn1 and insn2
|
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* don't have the same length. This used to be written as
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*
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* .if ((664b-663b) != (662b-661b))
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||||
* .error "Alternatives instruction length mismatch"
|
||||
* .endif
|
||||
*
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||||
* but most assemblers die if insn1 or insn2 have a .inst. This should
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* be fixed in a binutils release posterior to 2.25.51.0.2 (anything
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||||
* containing commit 4e4d08cf7399b606 or c1baaddf8861).
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*/
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#define ALTERNATIVE(oldinstr, newinstr, feature) \
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"661:\n\t" \
|
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oldinstr "\n" \
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@@ -37,8 +52,31 @@ void free_alternatives_memory(void);
|
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newinstr "\n" \
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"664:\n\t" \
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".popsection\n\t" \
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".if ((664b-663b) != (662b-661b))\n\t" \
|
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" .error \"Alternatives instruction length mismatch\"\n\t"\
|
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".endif\n"
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||||
".org . - (664b-663b) + (662b-661b)\n\t" \
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".org . - (662b-661b) + (664b-663b)\n"
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#else
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||||
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.macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len
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.word \orig_offset - .
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.word \alt_offset - .
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.hword \feature
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||||
.byte \orig_len
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.byte \alt_len
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.endm
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||||
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||||
.macro alternative_insn insn1 insn2 cap
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661: \insn1
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662: .pushsection .altinstructions, "a"
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altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f
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.popsection
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.pushsection .altinstr_replacement, "ax"
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663: \insn2
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664: .popsection
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.org . - (664b-663b) + (662b-661b)
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.org . - (662b-661b) + (664b-663b)
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.endm
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||||
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ALTERNATIVE_H */
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||||
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@@ -0,0 +1,14 @@
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|
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#ifndef __ASM_BOOT_H
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#define __ASM_BOOT_H
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|
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#include <asm/sizes.h>
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|
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/*
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||||
* arm64 requires the DTB to be 8 byte aligned and
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* not exceed 2MB in size.
|
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*/
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#define MIN_FDT_ALIGN 8
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#define MAX_FDT_SIZE SZ_2M
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|
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#endif
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@@ -40,10 +40,6 @@
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||||
* the implementation assumes non-aliasing VIPT D-cache and (aliasing)
|
||||
* VIPT or ASID-tagged VIVT I-cache.
|
||||
*
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||||
* flush_cache_all()
|
||||
*
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||||
* Unconditionally clean and invalidate the entire cache.
|
||||
*
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||||
* flush_cache_mm(mm)
|
||||
*
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* Clean and invalidate all user space cache entries
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||||
@@ -69,7 +65,6 @@
|
||||
* - kaddr - page address
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||||
* - size - region size
|
||||
*/
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||||
extern void flush_cache_all(void);
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||||
extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
|
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extern void flush_icache_range(unsigned long start, unsigned long end);
|
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extern void __flush_dcache_area(void *addr, size_t len);
|
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@@ -19,15 +19,15 @@
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#include <linux/init.h>
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#include <linux/threads.h>
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struct device_node;
|
||||
|
||||
/**
|
||||
* struct cpu_operations - Callback operations for hotplugging CPUs.
|
||||
*
|
||||
* @name: Name of the property as appears in a devicetree cpu node's
|
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* enable-method property.
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* @cpu_init: Reads any data necessary for a specific enable-method from the
|
||||
* devicetree, for a given cpu node and proposed logical id.
|
||||
* enable-method property. On systems booting with ACPI, @name
|
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* identifies the struct cpu_operations entry corresponding to
|
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* the boot protocol specified in the ACPI MADT table.
|
||||
* @cpu_init: Reads any data necessary for a specific enable-method for a
|
||||
* proposed logical id.
|
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* @cpu_prepare: Early one-time preparation step for a cpu. If there is a
|
||||
* mechanism for doing so, tests whether it is possible to boot
|
||||
* the given CPU.
|
||||
@@ -40,15 +40,15 @@ struct device_node;
|
||||
* @cpu_die: Makes a cpu leave the kernel. Must not fail. Called from the
|
||||
* cpu being killed.
|
||||
* @cpu_kill: Ensures a cpu has left the kernel. Called from another cpu.
|
||||
* @cpu_init_idle: Reads any data necessary to initialize CPU idle states from
|
||||
* devicetree, for a given cpu node and proposed logical id.
|
||||
* @cpu_init_idle: Reads any data necessary to initialize CPU idle states for
|
||||
* a proposed logical id.
|
||||
* @cpu_suspend: Suspends a cpu and saves the required context. May fail owing
|
||||
* to wrong parameters or error conditions. Called from the
|
||||
* CPU being suspended. Must be called with IRQs disabled.
|
||||
*/
|
||||
struct cpu_operations {
|
||||
const char *name;
|
||||
int (*cpu_init)(struct device_node *, unsigned int);
|
||||
int (*cpu_init)(unsigned int);
|
||||
int (*cpu_prepare)(unsigned int);
|
||||
int (*cpu_boot)(unsigned int);
|
||||
void (*cpu_postboot)(void);
|
||||
@@ -58,14 +58,17 @@ struct cpu_operations {
|
||||
int (*cpu_kill)(unsigned int cpu);
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_IDLE
|
||||
int (*cpu_init_idle)(struct device_node *, unsigned int);
|
||||
int (*cpu_init_idle)(unsigned int);
|
||||
int (*cpu_suspend)(unsigned long);
|
||||
#endif
|
||||
};
|
||||
|
||||
extern const struct cpu_operations *cpu_ops[NR_CPUS];
|
||||
int __init cpu_read_ops(struct device_node *dn, int cpu);
|
||||
void __init cpu_read_bootcpu_ops(void);
|
||||
const struct cpu_operations *cpu_get_ops(const char *name);
|
||||
int __init cpu_read_ops(int cpu);
|
||||
|
||||
static inline void __init cpu_read_bootcpu_ops(void)
|
||||
{
|
||||
cpu_read_ops(0);
|
||||
}
|
||||
|
||||
#endif /* ifndef __ASM_CPU_OPS_H */
|
||||
|
||||
@@ -24,8 +24,9 @@
|
||||
#define ARM64_WORKAROUND_CLEAN_CACHE 0
|
||||
#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1
|
||||
#define ARM64_WORKAROUND_845719 2
|
||||
#define ARM64_HAS_SYSREG_GIC_CPUIF 3
|
||||
|
||||
#define ARM64_NCAPS 3
|
||||
#define ARM64_NCAPS 4
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
@@ -38,6 +39,11 @@ struct arm64_cpu_capabilities {
|
||||
u32 midr_model;
|
||||
u32 midr_range_min, midr_range_max;
|
||||
};
|
||||
|
||||
struct { /* Feature register checking */
|
||||
u64 register_mask;
|
||||
u64 register_value;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -5,20 +5,16 @@
|
||||
|
||||
#ifdef CONFIG_CPU_IDLE
|
||||
extern int arm_cpuidle_init(unsigned int cpu);
|
||||
extern int cpu_suspend(unsigned long arg);
|
||||
extern int arm_cpuidle_suspend(int index);
|
||||
#else
|
||||
static inline int arm_cpuidle_init(unsigned int cpu)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline int cpu_suspend(unsigned long arg)
|
||||
static inline int arm_cpuidle_suspend(int index)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
#endif
|
||||
static inline int arm_cpuidle_suspend(int index)
|
||||
{
|
||||
return cpu_suspend(index);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -17,6 +17,7 @@
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/boot.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
/*
|
||||
@@ -32,6 +33,20 @@
|
||||
*/
|
||||
enum fixed_addresses {
|
||||
FIX_HOLE,
|
||||
|
||||
/*
|
||||
* Reserve a virtual window for the FDT that is 2 MB larger than the
|
||||
* maximum supported size, and put it at the top of the fixmap region.
|
||||
* The additional space ensures that any FDT that does not exceed
|
||||
* MAX_FDT_SIZE can be mapped regardless of whether it crosses any
|
||||
* 2 MB alignment boundaries.
|
||||
*
|
||||
* Keep this at the top so it remains 2 MB aligned.
|
||||
*/
|
||||
#define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M)
|
||||
FIX_FDT_END,
|
||||
FIX_FDT = FIX_FDT_END + FIX_FDT_SIZE / PAGE_SIZE - 1,
|
||||
|
||||
FIX_EARLYCON_MEM_BASE,
|
||||
FIX_TEXT_POKE0,
|
||||
__end_of_permanent_fixed_addresses,
|
||||
|
||||
@@ -281,6 +281,7 @@ __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000)
|
||||
#undef __AARCH64_INSN_FUNCS
|
||||
|
||||
bool aarch64_insn_is_nop(u32 insn);
|
||||
bool aarch64_insn_is_branch_imm(u32 insn);
|
||||
|
||||
int aarch64_insn_read(void *addr, u32 *insnp);
|
||||
int aarch64_insn_write(void *addr, u32 insn);
|
||||
@@ -351,6 +352,8 @@ u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
|
||||
int shift,
|
||||
enum aarch64_insn_variant variant,
|
||||
enum aarch64_insn_logic_type type);
|
||||
s32 aarch64_get_branch_offset(u32 insn);
|
||||
u32 aarch64_set_branch_offset(u32 insn, s32 offset);
|
||||
|
||||
bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
|
||||
|
||||
|
||||
@@ -117,10 +117,10 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
|
||||
* ordering rules but do not guarantee any ordering relative to Normal memory
|
||||
* accesses.
|
||||
*/
|
||||
#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
|
||||
#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
|
||||
#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
|
||||
#define readq_relaxed(c) ({ u64 __v = le64_to_cpu((__force __le64)__raw_readq(c)); __v; })
|
||||
#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
|
||||
#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
|
||||
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
|
||||
#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
|
||||
|
||||
#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
|
||||
#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
|
||||
|
||||
@@ -132,11 +132,6 @@ extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
|
||||
|
||||
extern u64 __vgic_v3_get_ich_vtr_el2(void);
|
||||
|
||||
extern char __save_vgic_v2_state[];
|
||||
extern char __restore_vgic_v2_state[];
|
||||
extern char __save_vgic_v3_state[];
|
||||
extern char __restore_vgic_v3_state[];
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ARM_KVM_ASM_H__ */
|
||||
|
||||
@@ -221,29 +221,6 @@ struct vgic_sr_vectors {
|
||||
void *restore_vgic;
|
||||
};
|
||||
|
||||
static inline void vgic_arch_setup(const struct vgic_params *vgic)
|
||||
{
|
||||
extern struct vgic_sr_vectors __vgic_sr_vectors;
|
||||
|
||||
switch(vgic->type)
|
||||
{
|
||||
case VGIC_V2:
|
||||
__vgic_sr_vectors.save_vgic = __save_vgic_v2_state;
|
||||
__vgic_sr_vectors.restore_vgic = __restore_vgic_v2_state;
|
||||
break;
|
||||
|
||||
#ifdef CONFIG_ARM_GIC_V3
|
||||
case VGIC_V3:
|
||||
__vgic_sr_vectors.save_vgic = __save_vgic_v3_state;
|
||||
__vgic_sr_vectors.restore_vgic = __restore_vgic_v3_state;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static inline void kvm_arch_hardware_disable(void) {}
|
||||
static inline void kvm_arch_hardware_unsetup(void) {}
|
||||
static inline void kvm_arch_sync_events(struct kvm *kvm) {}
|
||||
|
||||
@@ -34,5 +34,6 @@ extern void init_mem_pgprot(void);
|
||||
extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
|
||||
unsigned long virt, phys_addr_t size,
|
||||
pgprot_t prot);
|
||||
extern void *fixmap_remap_fdt(phys_addr_t dt_phys);
|
||||
|
||||
#endif
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user