Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (197 commits)
  sh: add spi header and r2d platform data V3
  sh: update r7780rp interrupt code
  sh: remove consistent alloc stuff from the machine vector
  sh: use declared coherent memory for dreamcast pci ethernet adapter
  sh: declared coherent memory support V2
  sh: Add support for SDK7780 board.
  sh: constify function pointer tables
  sh: Kill off -traditional for linker script.
  cdrom: Add support for Sega Dreamcast GD-ROM.
  sh: Kill off hs7751rvoip reference from arch/sh/Kconfig.
  sh: Drop r7780rp_defconfig, use r7780mp_defconfig as kbuild default.
  sh: Kill off dead HS771RVoIP board support.
  sh: r7785rp: Fix up DECLARE_INTC_DESC() arg mismatch.
  sh: r7785rp: Hook up the rest of the HL7785 FPGA IRQ vectors.
  sh: r2d - enable sm501 usb host function
  sh: remove voyagergx
  sh: r2d - add lcd planel timings to sm501 platform data
  sh: Add OHCI and UDC platform devices for SH7720.
  sh: intc - remove default interrupt priority tables
  sh: Correct pte size mismatch for X2 TLB.
  ...

drivers/rtc/Kconfig

@@ -404,7 +404,7 @@ config RTC_DRV_SA1100
 
 config RTC_DRV_SH
 	tristate "SuperH On-Chip RTC"
-	depends on RTC_CLASS && (CPU_SH3 || CPU_SH4)
+	depends on RTC_CLASS && SUPERH
 	help
 	  Say Y here to enable support for the on-chip RTC found in
 	  most SuperH processors.

drivers/rtc/rtc-sh.c

@@ -26,17 +26,7 @@
 #include <asm/rtc.h>
 
 #define DRV_NAME	"sh-rtc"
-#define DRV_VERSION	"0.1.3"
-
-#ifdef CONFIG_CPU_SH3
-#define rtc_reg_size		sizeof(u16)
-#define RTC_BIT_INVERTED	0	/* No bug on SH7708, SH7709A */
-#define RTC_DEF_CAPABILITIES	0UL
-#elif defined(CONFIG_CPU_SH4)
-#define rtc_reg_size		sizeof(u32)
-#define RTC_BIT_INVERTED	0x40	/* bug on SH7750, SH7750S */
-#define RTC_DEF_CAPABILITIES	RTC_CAP_4_DIGIT_YEAR
-#endif
+#define DRV_VERSION	"0.1.6"
 
 #define RTC_REG(r)	((r) * rtc_reg_size)
 
@@ -58,6 +48,18 @@
 #define RCR1		RTC_REG(14)	/* Control */
 #define RCR2		RTC_REG(15)	/* Control */
 
+/*
+ * Note on RYRAR and RCR3: Up until this point most of the register
+ * definitions are consistent across all of the available parts. However,
+ * the placement of the optional RYRAR and RCR3 (the RYRAR control
+ * register used to control RYRCNT/RYRAR compare) varies considerably
+ * across various parts, occasionally being mapped in to a completely
+ * unrelated address space. For proper RYRAR support a separate resource
+ * would have to be handed off, but as this is purely optional in
+ * practice, we simply opt not to support it, thereby keeping the code
+ * quite a bit more simplified.
+ */
+
 /* ALARM Bits - or with BCD encoded value */
 #define AR_ENB		0x80	/* Enable for alarm cmp   */