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Merge branch 'ioat-md-accel-for-linus' of git://lost.foo-projects.org/~dwillia2/git/iop
* 'ioat-md-accel-for-linus' of git://lost.foo-projects.org/~dwillia2/git/iop: (28 commits) ioatdma: add the unisys "i/oat" pci vendor/device id ARM: Add drivers/dma to arch/arm/Kconfig iop3xx: surface the iop3xx DMA and AAU units to the iop-adma driver iop13xx: surface the iop13xx adma units to the iop-adma driver dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines md: remove raid5 compute_block and compute_parity5 md: handle_stripe5 - request io processing in raid5_run_ops md: handle_stripe5 - add request/completion logic for async expand ops md: handle_stripe5 - add request/completion logic for async read ops md: handle_stripe5 - add request/completion logic for async check ops md: handle_stripe5 - add request/completion logic for async compute ops md: handle_stripe5 - add request/completion logic for async write ops md: common infrastructure for running operations with raid5_run_ops md: raid5_run_ops - run stripe operations outside sh->lock raid5: replace custom debug PRINTKs with standard pr_debug raid5: refactor handle_stripe5 and handle_stripe6 (v3) async_tx: add the async_tx api xor: make 'xor_blocks' a library routine for use with async_tx dmaengine: make clients responsible for managing channels dmaengine: refactor dmaengine around dma_async_tx_descriptor ...
This commit is contained in:
Linus Torvalds
File diff suppressed because it is too large
Load Diff
@@ -166,12 +166,22 @@ static inline int iop13xx_cpu_id(void)
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#define IOP13XX_INIT_I2C_1 (1 << 1)
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#define IOP13XX_INIT_I2C_2 (1 << 2)
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#define IQ81340_NUM_UART 2
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#define IQ81340_NUM_I2C 3
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#define IQ81340_NUM_PHYS_MAP_FLASH 1
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#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
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IQ81340_NUM_I2C +\
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IQ81340_NUM_PHYS_MAP_FLASH)
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/* ADMA selection flags */
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/* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
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#define IOP13XX_INIT_ADMA_DEFAULT (0)
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#define IOP13XX_INIT_ADMA_0 (1 << 0)
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#define IOP13XX_INIT_ADMA_1 (1 << 1)
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#define IOP13XX_INIT_ADMA_2 (1 << 2)
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/* Platform devices */
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#define IQ81340_NUM_UART 2
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#define IQ81340_NUM_I2C 3
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#define IQ81340_NUM_PHYS_MAP_FLASH 1
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#define IQ81340_NUM_ADMA 3
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#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
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IQ81340_NUM_I2C + \
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IQ81340_NUM_PHYS_MAP_FLASH + \
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IQ81340_NUM_ADMA)
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/*========================== PMMR offsets for key registers ============*/
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#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
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@@ -444,22 +454,6 @@ static inline int iop13xx_cpu_id(void)
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/*==============================ADMA UNITS===============================*/
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#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
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#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
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#define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs))
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#define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0)
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#define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4)
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#define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8)
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#define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18)
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#define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c)
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#define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20)
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#define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24)
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#define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28)
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#define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c)
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#define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30)
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#define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34)
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#define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38)
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#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
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#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
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/*==============================XSI BRIDGE===============================*/
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#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
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@@ -0,0 +1,5 @@
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#ifndef IOP32X_ADMA_H
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#define IOP32X_ADMA_H
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#include <asm/hardware/iop3xx-adma.h>
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#endif
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@@ -0,0 +1,5 @@
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#ifndef IOP33X_ADMA_H
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#define IOP33X_ADMA_H
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#include <asm/hardware/iop3xx-adma.h>
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#endif
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File diff suppressed because it is too large
Load Diff
@@ -144,24 +144,9 @@ extern int init_atu;
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#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
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/* DMA Controller */
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#define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400)
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#define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404)
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#define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c)
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#define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410)
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#define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414)
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#define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418)
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#define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c)
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#define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420)
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#define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424)
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#define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440)
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#define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444)
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#define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c)
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#define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450)
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#define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454)
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#define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458)
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#define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c)
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#define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460)
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#define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464)
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#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
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(0x400 + (chan << 6)))
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#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
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/* Peripheral bus interface */
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#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
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@@ -210,48 +195,8 @@ extern int init_atu;
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#define IOP_TMR_RATIO_1_1 0x00
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/* Application accelerator unit */
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#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800)
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#define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804)
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#define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808)
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#define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c)
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#define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810)
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#define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814)
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#define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818)
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#define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c)
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#define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820)
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#define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824)
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#define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828)
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#define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c)
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#define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830)
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#define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834)
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#define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838)
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#define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c)
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#define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840)
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#define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844)
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#define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848)
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#define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c)
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#define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850)
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#define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854)
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#define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858)
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#define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c)
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#define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860)
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#define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864)
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#define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868)
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#define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c)
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#define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870)
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#define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874)
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#define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878)
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#define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c)
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#define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880)
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#define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884)
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#define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888)
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#define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c)
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#define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890)
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#define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894)
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#define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898)
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#define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c)
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#define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0)
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#define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4)
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#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
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#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
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/* I2C bus interface unit */
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#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
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@@ -329,6 +274,9 @@ static inline void write_tisr(u32 val)
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asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
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}
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extern struct platform_device iop3xx_dma_0_channel;
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extern struct platform_device iop3xx_dma_1_channel;
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extern struct platform_device iop3xx_aau_channel;
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extern struct platform_device iop3xx_i2c0_device;
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extern struct platform_device iop3xx_i2c1_device;
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@@ -0,0 +1,118 @@
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/*
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* Copyright © 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef IOP_ADMA_H
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#define IOP_ADMA_H
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#include <linux/types.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#define IOP_ADMA_SLOT_SIZE 32
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#define IOP_ADMA_THRESHOLD 4
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/**
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* struct iop_adma_device - internal representation of an ADMA device
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* @pdev: Platform device
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* @id: HW ADMA Device selector
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* @dma_desc_pool: base of DMA descriptor region (DMA address)
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* @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
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* @common: embedded struct dma_device
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*/
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struct iop_adma_device {
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struct platform_device *pdev;
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int id;
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dma_addr_t dma_desc_pool;
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void *dma_desc_pool_virt;
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struct dma_device common;
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};
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/**
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* struct iop_adma_chan - internal representation of an ADMA device
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* @pending: allows batching of hardware operations
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* @completed_cookie: identifier for the most recently completed operation
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* @lock: serializes enqueue/dequeue operations to the slot pool
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* @mmr_base: memory mapped register base
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* @chain: device chain view of the descriptors
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* @device: parent device
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* @common: common dmaengine channel object members
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* @last_used: place holder for allocation to continue from where it left off
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* @all_slots: complete domain of slots usable by the channel
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* @cleanup_watchdog: workaround missed interrupts on iop3xx
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* @slots_allocated: records the actual size of the descriptor slot pool
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* @irq_tasklet: bottom half where iop_adma_slot_cleanup runs
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*/
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struct iop_adma_chan {
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int pending;
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dma_cookie_t completed_cookie;
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spinlock_t lock; /* protects the descriptor slot pool */
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void __iomem *mmr_base;
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struct list_head chain;
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struct iop_adma_device *device;
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struct dma_chan common;
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struct iop_adma_desc_slot *last_used;
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struct list_head all_slots;
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struct timer_list cleanup_watchdog;
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int slots_allocated;
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struct tasklet_struct irq_tasklet;
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};
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/**
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* struct iop_adma_desc_slot - IOP-ADMA software descriptor
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* @slot_node: node on the iop_adma_chan.all_slots list
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* @chain_node: node on the op_adma_chan.chain list
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* @hw_desc: virtual address of the hardware descriptor chain
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* @phys: hardware address of the hardware descriptor chain
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* @group_head: first operation in a transaction
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* @slot_cnt: total slots used in an transaction (group of operations)
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* @slots_per_op: number of slots per operation
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* @idx: pool index
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* @unmap_src_cnt: number of xor sources
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* @unmap_len: transaction bytecount
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* @async_tx: support for the async_tx api
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* @group_list: list of slots that make up a multi-descriptor transaction
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* for example transfer lengths larger than the supported hw max
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* @xor_check_result: result of zero sum
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* @crc32_result: result crc calculation
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*/
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struct iop_adma_desc_slot {
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struct list_head slot_node;
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struct list_head chain_node;
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void *hw_desc;
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struct iop_adma_desc_slot *group_head;
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u16 slot_cnt;
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u16 slots_per_op;
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u16 idx;
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u16 unmap_src_cnt;
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size_t unmap_len;
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struct dma_async_tx_descriptor async_tx;
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union {
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u32 *xor_check_result;
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u32 *crc32_result;
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};
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};
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struct iop_adma_platform_data {
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int hw_id;
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dma_cap_mask_t cap_mask;
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size_t pool_size;
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};
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#define to_iop_sw_desc(addr_hw_desc) \
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container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc)
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#define iop_hw_desc_slot_idx(hw_desc, idx) \
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( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) )
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#endif
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