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Merge tag 'iwlwifi-for-kalle-2015-06-12' of https://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-fixes
* bug fixes specific for 8000 series
* fix a crash in time events
* fix a crash in PCIe transport
* fix BT Coex code that prevented association on certain
devices (3160).
* revert the new RBD allocation model because it introduced
a bug when running on weak VM setups.
* a new device IDs
This commit is contained in:
@@ -438,6 +438,12 @@ static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl)
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#define RX_QUEUE_MASK 255
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#define RX_QUEUE_SIZE_LOG 8
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/*
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* RX related structures and functions
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*/
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#define RX_FREE_BUFFERS 64
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#define RX_LOW_WATERMARK 8
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/**
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* struct iwl_rb_status - reserve buffer status
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* host memory mapped FH registers
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@@ -540,13 +540,11 @@ static void iwl_set_hw_address_family_8000(struct device *dev,
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hw_addr = (const u8 *)(mac_override +
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MAC_ADDRESS_OVERRIDE_FAMILY_8000);
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/* The byte order is little endian 16 bit, meaning 214365 */
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data->hw_addr[0] = hw_addr[1];
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data->hw_addr[1] = hw_addr[0];
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data->hw_addr[2] = hw_addr[3];
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data->hw_addr[3] = hw_addr[2];
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data->hw_addr[4] = hw_addr[5];
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data->hw_addr[5] = hw_addr[4];
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/*
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* Store the MAC address from MAO section.
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* No byte swapping is required in MAO section
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*/
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memcpy(data->hw_addr, hw_addr, ETH_ALEN);
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/*
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* Force the use of the OTP MAC address in case of reserved MAC
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@@ -660,7 +660,8 @@ struct iwl_scan_config {
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* iwl_umac_scan_flags
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*@IWL_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
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* can be preempted by other scan requests with higher priority.
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* The low priority scan is aborted.
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* The low priority scan will be resumed when the higher proirity scan is
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* completed.
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*@IWL_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
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* when scan starts.
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*/
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@@ -1109,6 +1109,9 @@ static int iwl_mvm_scan_umac(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
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cmd->uid = cpu_to_le32(uid);
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cmd->general_flags = cpu_to_le32(iwl_mvm_scan_umac_flags(mvm, params));
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if (type == IWL_MVM_SCAN_SCHED)
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cmd->flags = cpu_to_le32(IWL_UMAC_SCAN_FLAG_PREEMPTIVE);
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if (iwl_mvm_scan_use_ebs(mvm, vif, n_iterations))
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cmd->channel_flags = IWL_SCAN_CHANNEL_FLAG_EBS |
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IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE |
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@@ -1401,6 +1401,7 @@ int iwl_mvm_set_sta_key(struct iwl_mvm *mvm,
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bool mcast = !(keyconf->flags & IEEE80211_KEY_FLAG_PAIRWISE);
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u8 sta_id;
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int ret;
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static const u8 __maybe_unused zero_addr[ETH_ALEN] = {0};
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lockdep_assert_held(&mvm->mutex);
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@@ -1467,7 +1468,7 @@ int iwl_mvm_set_sta_key(struct iwl_mvm *mvm,
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end:
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IWL_DEBUG_WEP(mvm, "key: cipher=%x len=%d idx=%d sta=%pM ret=%d\n",
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keyconf->cipher, keyconf->keylen, keyconf->keyidx,
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sta->addr, ret);
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sta ? sta->addr : zero_addr, ret);
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return ret;
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}
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@@ -86,7 +86,7 @@ void iwl_mvm_te_clear_data(struct iwl_mvm *mvm,
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{
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lockdep_assert_held(&mvm->time_event_lock);
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if (te_data->id == TE_MAX)
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if (!te_data->vif)
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return;
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list_del(&te_data->list);
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@@ -252,7 +252,7 @@ void iwl_mvm_set_tx_cmd_rate(struct iwl_mvm *mvm, struct iwl_tx_cmd *tx_cmd,
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if (info->band == IEEE80211_BAND_2GHZ &&
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!iwl_mvm_bt_coex_is_shared_ant_avail(mvm))
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rate_flags = BIT(mvm->cfg->non_shared_ant) << RATE_MCS_ANT_POS;
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rate_flags = mvm->cfg->non_shared_ant << RATE_MCS_ANT_POS;
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else
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rate_flags =
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BIT(mvm->mgmt_last_antenna_idx) << RATE_MCS_ANT_POS;
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@@ -368,12 +368,14 @@ static const struct pci_device_id iwl_hw_card_ids[] = {
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/* 3165 Series */
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{IWL_PCI_DEVICE(0x3165, 0x4010, iwl3165_2ac_cfg)},
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{IWL_PCI_DEVICE(0x3165, 0x4012, iwl3165_2ac_cfg)},
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{IWL_PCI_DEVICE(0x3166, 0x4212, iwl3165_2ac_cfg)},
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{IWL_PCI_DEVICE(0x3165, 0x4410, iwl3165_2ac_cfg)},
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{IWL_PCI_DEVICE(0x3165, 0x4510, iwl3165_2ac_cfg)},
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{IWL_PCI_DEVICE(0x3165, 0x4110, iwl3165_2ac_cfg)},
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{IWL_PCI_DEVICE(0x3166, 0x4310, iwl3165_2ac_cfg)},
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{IWL_PCI_DEVICE(0x3166, 0x4210, iwl3165_2ac_cfg)},
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{IWL_PCI_DEVICE(0x3165, 0x8010, iwl3165_2ac_cfg)},
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{IWL_PCI_DEVICE(0x3165, 0x8110, iwl3165_2ac_cfg)},
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/* 7265 Series */
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{IWL_PCI_DEVICE(0x095A, 0x5010, iwl7265_2ac_cfg)},
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@@ -426,9 +428,8 @@ static const struct pci_device_id iwl_hw_card_ids[] = {
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{IWL_PCI_DEVICE(0x24F4, 0x1130, iwl8260_2ac_cfg)},
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{IWL_PCI_DEVICE(0x24F4, 0x1030, iwl8260_2ac_cfg)},
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{IWL_PCI_DEVICE(0x24F3, 0xC010, iwl8260_2ac_cfg)},
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{IWL_PCI_DEVICE(0x24F3, 0xC110, iwl8260_2ac_cfg)},
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{IWL_PCI_DEVICE(0x24F3, 0xD010, iwl8260_2ac_cfg)},
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{IWL_PCI_DEVICE(0x24F4, 0xC030, iwl8260_2ac_cfg)},
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{IWL_PCI_DEVICE(0x24F4, 0xD030, iwl8260_2ac_cfg)},
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{IWL_PCI_DEVICE(0x24F3, 0xC050, iwl8260_2ac_cfg)},
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{IWL_PCI_DEVICE(0x24F3, 0xD050, iwl8260_2ac_cfg)},
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{IWL_PCI_DEVICE(0x24F3, 0x8010, iwl8260_2ac_cfg)},
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@@ -44,15 +44,6 @@
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#include "iwl-io.h"
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#include "iwl-op-mode.h"
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/*
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* RX related structures and functions
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*/
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#define RX_NUM_QUEUES 1
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#define RX_POST_REQ_ALLOC 2
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#define RX_CLAIM_REQ_ALLOC 8
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#define RX_POOL_SIZE ((RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC) * RX_NUM_QUEUES)
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#define RX_LOW_WATERMARK 8
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struct iwl_host_cmd;
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/*This file includes the declaration that are internal to the
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@@ -86,29 +77,29 @@ struct isr_statistics {
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* struct iwl_rxq - Rx queue
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* @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
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* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
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* @pool:
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* @queue:
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* @read: Shared index to newest available Rx buffer
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* @write: Shared index to oldest written Rx packet
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* @free_count: Number of pre-allocated buffers in rx_free
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* @used_count: Number of RBDs handled to allocator to use for allocation
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* @write_actual:
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* @rx_free: list of RBDs with allocated RB ready for use
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* @rx_used: list of RBDs with no RB attached
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* @rx_free: list of free SKBs for use
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* @rx_used: List of Rx buffers with no SKB
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* @need_update: flag to indicate we need to update read/write index
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* @rb_stts: driver's pointer to receive buffer status
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* @rb_stts_dma: bus address of receive buffer status
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* @lock:
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* @pool: initial pool of iwl_rx_mem_buffer for the queue
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* @queue: actual rx queue
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*
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* NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
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*/
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struct iwl_rxq {
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__le32 *bd;
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dma_addr_t bd_dma;
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struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
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struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
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u32 read;
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u32 write;
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u32 free_count;
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u32 used_count;
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u32 write_actual;
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struct list_head rx_free;
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struct list_head rx_used;
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@@ -116,32 +107,6 @@ struct iwl_rxq {
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struct iwl_rb_status *rb_stts;
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dma_addr_t rb_stts_dma;
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spinlock_t lock;
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struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE];
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struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
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};
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/**
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* struct iwl_rb_allocator - Rx allocator
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* @pool: initial pool of allocator
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* @req_pending: number of requests the allcator had not processed yet
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* @req_ready: number of requests honored and ready for claiming
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* @rbd_allocated: RBDs with pages allocated and ready to be handled to
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* the queue. This is a list of &struct iwl_rx_mem_buffer
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* @rbd_empty: RBDs with no page attached for allocator use. This is a list
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* of &struct iwl_rx_mem_buffer
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* @lock: protects the rbd_allocated and rbd_empty lists
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* @alloc_wq: work queue for background calls
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* @rx_alloc: work struct for background calls
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*/
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struct iwl_rb_allocator {
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struct iwl_rx_mem_buffer pool[RX_POOL_SIZE];
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atomic_t req_pending;
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atomic_t req_ready;
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struct list_head rbd_allocated;
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struct list_head rbd_empty;
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spinlock_t lock;
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struct workqueue_struct *alloc_wq;
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struct work_struct rx_alloc;
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};
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struct iwl_dma_ptr {
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@@ -285,7 +250,7 @@ iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
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/**
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* struct iwl_trans_pcie - PCIe transport specific data
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* @rxq: all the RX queue data
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* @rba: allocator for RX replenishing
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* @rx_replenish: work that will be called when buffers need to be allocated
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* @drv - pointer to iwl_drv
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* @trans: pointer to the generic transport area
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* @scd_base_addr: scheduler sram base address in SRAM
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@@ -308,7 +273,7 @@ iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
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*/
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struct iwl_trans_pcie {
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struct iwl_rxq rxq;
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struct iwl_rb_allocator rba;
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struct work_struct rx_replenish;
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struct iwl_trans *trans;
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struct iwl_drv *drv;
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File diff suppressed because it is too large
Load Diff
@@ -182,7 +182,7 @@ static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
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static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
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{
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if (!trans->cfg->apmg_not_supported)
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if (trans->cfg->apmg_not_supported)
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return;
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if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
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@@ -2459,7 +2459,7 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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struct iwl_trans_pcie *trans_pcie;
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struct iwl_trans *trans;
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u16 pci_cmd;
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int err;
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int ret;
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trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
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&pdev->dev, cfg, &trans_ops_pcie, 0);
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@@ -2474,8 +2474,8 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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spin_lock_init(&trans_pcie->ref_lock);
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init_waitqueue_head(&trans_pcie->ucode_write_waitq);
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err = pci_enable_device(pdev);
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if (err)
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ret = pci_enable_device(pdev);
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if (ret)
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goto out_no_pci;
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if (!cfg->base_params->pcie_l1_allowed) {
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@@ -2491,23 +2491,23 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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pci_set_master(pdev);
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
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if (!err)
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
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if (err) {
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (!err)
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err = pci_set_consistent_dma_mask(pdev,
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ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
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if (!ret)
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ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
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if (ret) {
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ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (!ret)
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ret = pci_set_consistent_dma_mask(pdev,
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DMA_BIT_MASK(32));
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/* both attempts failed: */
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if (err) {
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if (ret) {
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dev_err(&pdev->dev, "No suitable DMA available\n");
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goto out_pci_disable_device;
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}
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}
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err = pci_request_regions(pdev, DRV_NAME);
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if (err) {
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ret = pci_request_regions(pdev, DRV_NAME);
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if (ret) {
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dev_err(&pdev->dev, "pci_request_regions failed\n");
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goto out_pci_disable_device;
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}
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@@ -2515,7 +2515,7 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
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if (!trans_pcie->hw_base) {
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dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
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err = -ENODEV;
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ret = -ENODEV;
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goto out_pci_release_regions;
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}
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@@ -2527,9 +2527,9 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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trans_pcie->pci_dev = pdev;
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iwl_disable_interrupts(trans);
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err = pci_enable_msi(pdev);
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if (err) {
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dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
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ret = pci_enable_msi(pdev);
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if (ret) {
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dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
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/* enable rfkill interrupt: hw bug w/a */
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pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
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if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
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@@ -2547,11 +2547,16 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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*/
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if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
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unsigned long flags;
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int ret;
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trans->hw_rev = (trans->hw_rev & 0xfff0) |
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(CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
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ret = iwl_pcie_prepare_card_hw(trans);
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if (ret) {
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IWL_WARN(trans, "Exit HW not ready\n");
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goto out_pci_disable_msi;
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}
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/*
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* in-order to recognize C step driver should read chip version
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* id located at the AUX bus MISC address space.
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@@ -2591,13 +2596,14 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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/* Initialize the wait queue for commands */
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init_waitqueue_head(&trans_pcie->wait_command_queue);
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if (iwl_pcie_alloc_ict(trans))
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ret = iwl_pcie_alloc_ict(trans);
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if (ret)
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goto out_pci_disable_msi;
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err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
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ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
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iwl_pcie_irq_handler,
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IRQF_SHARED, DRV_NAME, trans);
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if (err) {
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if (ret) {
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IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
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goto out_free_ict;
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}
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@@ -2617,5 +2623,5 @@ out_pci_disable_device:
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pci_disable_device(pdev);
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out_no_pci:
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iwl_trans_free(trans);
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return ERR_PTR(err);
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return ERR_PTR(ret);
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}
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