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Merge branch 'clockevents/renesas-timers-dt' into clockevents/3.17
This commit is contained in:
Daniel Lezcano
+87
-148
@@ -24,6 +24,7 @@
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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@@ -114,14 +115,15 @@ struct sh_cmt_device {
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struct platform_device *pdev;
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const struct sh_cmt_info *info;
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bool legacy;
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void __iomem *mapbase_ch;
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void __iomem *mapbase;
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struct clk *clk;
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raw_spinlock_t lock; /* Protect the shared start/stop register */
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struct sh_cmt_channel *channels;
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unsigned int num_channels;
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unsigned int hw_channels;
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bool has_clockevent;
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bool has_clocksource;
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@@ -301,14 +303,12 @@ static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
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return v2;
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}
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static DEFINE_RAW_SPINLOCK(sh_cmt_lock);
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static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
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{
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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raw_spin_lock_irqsave(&sh_cmt_lock, flags);
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raw_spin_lock_irqsave(&ch->cmt->lock, flags);
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value = sh_cmt_read_cmstr(ch);
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if (start)
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@@ -317,7 +317,7 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
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value &= ~(1 << ch->timer_bit);
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sh_cmt_write_cmstr(ch, value);
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raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
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raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
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}
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static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate)
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@@ -792,7 +792,7 @@ static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
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int irq;
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int ret;
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irq = platform_get_irq(ch->cmt->pdev, ch->cmt->legacy ? 0 : ch->index);
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irq = platform_get_irq(ch->cmt->pdev, ch->index);
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if (irq < 0) {
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dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
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ch->index);
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@@ -863,33 +863,26 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
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* Compute the address of the channel control register block. For the
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* timers with a per-channel start/stop register, compute its address
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* as well.
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*
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* For legacy configuration the address has been mapped explicitly.
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*/
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if (cmt->legacy) {
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ch->ioctrl = cmt->mapbase_ch;
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} else {
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switch (cmt->info->model) {
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case SH_CMT_16BIT:
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ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
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break;
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case SH_CMT_32BIT:
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case SH_CMT_48BIT:
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ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
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break;
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case SH_CMT_32BIT_FAST:
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/*
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* The 32-bit "fast" timer has a single channel at hwidx
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* 5 but is located at offset 0x40 instead of 0x60 for
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* some reason.
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*/
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ch->ioctrl = cmt->mapbase + 0x40;
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break;
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case SH_CMT_48BIT_GEN2:
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ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
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ch->ioctrl = ch->iostart + 0x10;
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break;
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}
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switch (cmt->info->model) {
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case SH_CMT_16BIT:
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ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
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break;
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case SH_CMT_32BIT:
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case SH_CMT_48BIT:
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ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
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break;
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case SH_CMT_32BIT_FAST:
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/*
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* The 32-bit "fast" timer has a single channel at hwidx 5 but
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* is located at offset 0x40 instead of 0x60 for some reason.
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*/
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ch->ioctrl = cmt->mapbase + 0x40;
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break;
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case SH_CMT_48BIT_GEN2:
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ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
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ch->ioctrl = ch->iostart + 0x10;
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break;
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}
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if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
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@@ -900,12 +893,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
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ch->match_value = ch->max_match_value;
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raw_spin_lock_init(&ch->lock);
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if (cmt->legacy) {
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ch->timer_bit = ch->hwidx;
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} else {
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ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2
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? 0 : ch->hwidx;
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}
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ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;
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ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
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clockevent, clocksource);
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@@ -938,75 +926,65 @@ static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
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return 0;
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}
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static int sh_cmt_map_memory_legacy(struct sh_cmt_device *cmt)
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static const struct platform_device_id sh_cmt_id_table[] = {
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{ "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
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{ "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
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{ "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] },
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{ "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] },
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{ "sh-cmt-48-gen2", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT_GEN2] },
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{ }
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};
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MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
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static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
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{ .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] },
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{ .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] },
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{ .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
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{ .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
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static int sh_cmt_parse_dt(struct sh_cmt_device *cmt)
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{
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struct sh_timer_config *cfg = cmt->pdev->dev.platform_data;
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struct resource *res, *res2;
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struct device_node *np = cmt->pdev->dev.of_node;
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/* map memory, let mapbase_ch point to our channel */
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res = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
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return -ENXIO;
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}
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cmt->mapbase_ch = ioremap_nocache(res->start, resource_size(res));
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if (cmt->mapbase_ch == NULL) {
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dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
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return -ENXIO;
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}
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/* optional resource for the shared timer start/stop register */
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res2 = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 1);
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/* map second resource for CMSTR */
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cmt->mapbase = ioremap_nocache(res2 ? res2->start :
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res->start - cfg->channel_offset,
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res2 ? resource_size(res2) : 2);
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if (cmt->mapbase == NULL) {
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dev_err(&cmt->pdev->dev, "failed to remap I/O second memory\n");
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iounmap(cmt->mapbase_ch);
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return -ENXIO;
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}
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/* identify the model based on the resources */
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if (resource_size(res) == 6)
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cmt->info = &sh_cmt_info[SH_CMT_16BIT];
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else if (res2 && (resource_size(res2) == 4))
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cmt->info = &sh_cmt_info[SH_CMT_48BIT_GEN2];
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else
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cmt->info = &sh_cmt_info[SH_CMT_32BIT];
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return 0;
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}
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static void sh_cmt_unmap_memory(struct sh_cmt_device *cmt)
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{
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iounmap(cmt->mapbase);
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if (cmt->mapbase_ch)
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iounmap(cmt->mapbase_ch);
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return of_property_read_u32(np, "renesas,channels-mask",
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&cmt->hw_channels);
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}
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static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
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{
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struct sh_timer_config *cfg = pdev->dev.platform_data;
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const struct platform_device_id *id = pdev->id_entry;
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unsigned int hw_channels;
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unsigned int mask;
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unsigned int i;
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int ret;
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memset(cmt, 0, sizeof(*cmt));
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cmt->pdev = pdev;
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raw_spin_lock_init(&cmt->lock);
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if (!cfg) {
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if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
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const struct of_device_id *id;
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id = of_match_node(sh_cmt_of_table, pdev->dev.of_node);
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cmt->info = id->data;
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ret = sh_cmt_parse_dt(cmt);
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if (ret < 0)
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return ret;
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} else if (pdev->dev.platform_data) {
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struct sh_timer_config *cfg = pdev->dev.platform_data;
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const struct platform_device_id *id = pdev->id_entry;
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cmt->info = (const struct sh_cmt_info *)id->driver_data;
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cmt->hw_channels = cfg->channels_mask;
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} else {
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dev_err(&cmt->pdev->dev, "missing platform data\n");
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return -ENXIO;
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}
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cmt->info = (const struct sh_cmt_info *)id->driver_data;
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cmt->legacy = cmt->info ? false : true;
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/* Get hold of clock. */
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cmt->clk = clk_get(&cmt->pdev->dev, cmt->legacy ? "cmt_fck" : "fck");
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cmt->clk = clk_get(&cmt->pdev->dev, "fck");
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if (IS_ERR(cmt->clk)) {
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dev_err(&cmt->pdev->dev, "cannot get clock\n");
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return PTR_ERR(cmt->clk);
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@@ -1016,28 +994,13 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
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if (ret < 0)
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goto err_clk_put;
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/*
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* Map the memory resource(s). We need to support both the legacy
|
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* platform device configuration (with one device per channel) and the
|
||||
* new version (with multiple channels per device).
|
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*/
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if (cmt->legacy)
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ret = sh_cmt_map_memory_legacy(cmt);
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else
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ret = sh_cmt_map_memory(cmt);
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/* Map the memory resource(s). */
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ret = sh_cmt_map_memory(cmt);
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if (ret < 0)
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goto err_clk_unprepare;
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/* Allocate and setup the channels. */
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if (cmt->legacy) {
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cmt->num_channels = 1;
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hw_channels = 0;
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} else {
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cmt->num_channels = hweight8(cfg->channels_mask);
|
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hw_channels = cfg->channels_mask;
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}
|
||||
|
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cmt->num_channels = hweight8(cmt->hw_channels);
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cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),
|
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GFP_KERNEL);
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if (cmt->channels == NULL) {
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@@ -1045,35 +1008,21 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
|
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goto err_unmap;
|
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}
|
||||
|
||||
if (cmt->legacy) {
|
||||
ret = sh_cmt_setup_channel(&cmt->channels[0],
|
||||
cfg->timer_bit, cfg->timer_bit,
|
||||
cfg->clockevent_rating != 0,
|
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cfg->clocksource_rating != 0, cmt);
|
||||
/*
|
||||
* Use the first channel as a clock event device and the second channel
|
||||
* as a clock source. If only one channel is available use it for both.
|
||||
*/
|
||||
for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
|
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unsigned int hwidx = ffs(mask) - 1;
|
||||
bool clocksource = i == 1 || cmt->num_channels == 1;
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bool clockevent = i == 0;
|
||||
|
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ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
|
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clockevent, clocksource, cmt);
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if (ret < 0)
|
||||
goto err_unmap;
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} else {
|
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unsigned int mask = hw_channels;
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unsigned int i;
|
||||
|
||||
/*
|
||||
* Use the first channel as a clock event device and the second
|
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* channel as a clock source. If only one channel is available
|
||||
* use it for both.
|
||||
*/
|
||||
for (i = 0; i < cmt->num_channels; ++i) {
|
||||
unsigned int hwidx = ffs(mask) - 1;
|
||||
bool clocksource = i == 1 || cmt->num_channels == 1;
|
||||
bool clockevent = i == 0;
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||||
|
||||
ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
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||||
clockevent, clocksource,
|
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cmt);
|
||||
if (ret < 0)
|
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goto err_unmap;
|
||||
|
||||
mask &= ~(1 << hwidx);
|
||||
}
|
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mask &= ~(1 << hwidx);
|
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}
|
||||
|
||||
platform_set_drvdata(pdev, cmt);
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||||
@@ -1082,7 +1031,7 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
|
||||
|
||||
err_unmap:
|
||||
kfree(cmt->channels);
|
||||
sh_cmt_unmap_memory(cmt);
|
||||
iounmap(cmt->mapbase);
|
||||
err_clk_unprepare:
|
||||
clk_unprepare(cmt->clk);
|
||||
err_clk_put:
|
||||
@@ -1132,22 +1081,12 @@ static int sh_cmt_remove(struct platform_device *pdev)
|
||||
return -EBUSY; /* cannot unregister clockevent and clocksource */
|
||||
}
|
||||
|
||||
static const struct platform_device_id sh_cmt_id_table[] = {
|
||||
{ "sh_cmt", 0 },
|
||||
{ "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
|
||||
{ "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
|
||||
{ "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] },
|
||||
{ "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] },
|
||||
{ "sh-cmt-48-gen2", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT_GEN2] },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
|
||||
|
||||
static struct platform_driver sh_cmt_device_driver = {
|
||||
.probe = sh_cmt_probe,
|
||||
.remove = sh_cmt_remove,
|
||||
.driver = {
|
||||
.name = "sh_cmt",
|
||||
.of_match_table = of_match_ptr(sh_cmt_of_table),
|
||||
},
|
||||
.id_table = sh_cmt_id_table,
|
||||
};
|
||||
|
||||
+45
-103
@@ -23,6 +23,7 @@
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
@@ -37,7 +38,6 @@ struct sh_mtu2_channel {
|
||||
unsigned int index;
|
||||
|
||||
void __iomem *base;
|
||||
int irq;
|
||||
|
||||
struct clock_event_device ced;
|
||||
};
|
||||
@@ -48,15 +48,14 @@ struct sh_mtu2_device {
|
||||
void __iomem *mapbase;
|
||||
struct clk *clk;
|
||||
|
||||
raw_spinlock_t lock; /* Protect the shared registers */
|
||||
|
||||
struct sh_mtu2_channel *channels;
|
||||
unsigned int num_channels;
|
||||
|
||||
bool legacy;
|
||||
bool has_clockevent;
|
||||
};
|
||||
|
||||
static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
|
||||
|
||||
#define TSTR -1 /* shared register */
|
||||
#define TCR 0 /* channel register */
|
||||
#define TMDR 1 /* channel register */
|
||||
@@ -162,12 +161,8 @@ static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
|
||||
{
|
||||
unsigned long offs;
|
||||
|
||||
if (reg_nr == TSTR) {
|
||||
if (ch->mtu->legacy)
|
||||
return ioread8(ch->mtu->mapbase);
|
||||
else
|
||||
return ioread8(ch->mtu->mapbase + 0x280);
|
||||
}
|
||||
if (reg_nr == TSTR)
|
||||
return ioread8(ch->mtu->mapbase + 0x280);
|
||||
|
||||
offs = mtu2_reg_offs[reg_nr];
|
||||
|
||||
@@ -182,12 +177,8 @@ static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
|
||||
{
|
||||
unsigned long offs;
|
||||
|
||||
if (reg_nr == TSTR) {
|
||||
if (ch->mtu->legacy)
|
||||
return iowrite8(value, ch->mtu->mapbase);
|
||||
else
|
||||
return iowrite8(value, ch->mtu->mapbase + 0x280);
|
||||
}
|
||||
if (reg_nr == TSTR)
|
||||
return iowrite8(value, ch->mtu->mapbase + 0x280);
|
||||
|
||||
offs = mtu2_reg_offs[reg_nr];
|
||||
|
||||
@@ -202,7 +193,7 @@ static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
|
||||
unsigned long flags, value;
|
||||
|
||||
/* start stop register shared by multiple timer channels */
|
||||
raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
|
||||
raw_spin_lock_irqsave(&ch->mtu->lock, flags);
|
||||
value = sh_mtu2_read(ch, TSTR);
|
||||
|
||||
if (start)
|
||||
@@ -211,7 +202,7 @@ static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
|
||||
value &= ~(1 << ch->index);
|
||||
|
||||
sh_mtu2_write(ch, TSTR, value);
|
||||
raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&ch->mtu->lock, flags);
|
||||
}
|
||||
|
||||
static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
|
||||
@@ -331,7 +322,6 @@ static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
|
||||
const char *name)
|
||||
{
|
||||
struct clock_event_device *ced = &ch->ced;
|
||||
int ret;
|
||||
|
||||
ced->name = name;
|
||||
ced->features = CLOCK_EVT_FEAT_PERIODIC;
|
||||
@@ -344,24 +334,12 @@ static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
|
||||
dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",
|
||||
ch->index);
|
||||
clockevents_register_device(ced);
|
||||
|
||||
ret = request_irq(ch->irq, sh_mtu2_interrupt,
|
||||
IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
|
||||
dev_name(&ch->mtu->pdev->dev), ch);
|
||||
if (ret) {
|
||||
dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
|
||||
ch->index, ch->irq);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name,
|
||||
bool clockevent)
|
||||
static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name)
|
||||
{
|
||||
if (clockevent) {
|
||||
ch->mtu->has_clockevent = true;
|
||||
sh_mtu2_register_clockevent(ch, name);
|
||||
}
|
||||
ch->mtu->has_clockevent = true;
|
||||
sh_mtu2_register_clockevent(ch, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -372,40 +350,32 @@ static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,
|
||||
static const unsigned int channel_offsets[] = {
|
||||
0x300, 0x380, 0x000,
|
||||
};
|
||||
bool clockevent;
|
||||
char name[6];
|
||||
int irq;
|
||||
int ret;
|
||||
|
||||
ch->mtu = mtu;
|
||||
|
||||
if (mtu->legacy) {
|
||||
struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
|
||||
|
||||
clockevent = cfg->clockevent_rating != 0;
|
||||
|
||||
ch->irq = platform_get_irq(mtu->pdev, 0);
|
||||
ch->base = mtu->mapbase - cfg->channel_offset;
|
||||
ch->index = cfg->timer_bit;
|
||||
} else {
|
||||
char name[6];
|
||||
|
||||
clockevent = true;
|
||||
|
||||
sprintf(name, "tgi%ua", index);
|
||||
ch->irq = platform_get_irq_byname(mtu->pdev, name);
|
||||
ch->base = mtu->mapbase + channel_offsets[index];
|
||||
ch->index = index;
|
||||
}
|
||||
|
||||
if (ch->irq < 0) {
|
||||
sprintf(name, "tgi%ua", index);
|
||||
irq = platform_get_irq_byname(mtu->pdev, name);
|
||||
if (irq < 0) {
|
||||
/* Skip channels with no declared interrupt. */
|
||||
if (!mtu->legacy)
|
||||
return 0;
|
||||
|
||||
dev_err(&mtu->pdev->dev, "ch%u: failed to get irq\n",
|
||||
ch->index);
|
||||
return ch->irq;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev), clockevent);
|
||||
ret = request_irq(irq, sh_mtu2_interrupt,
|
||||
IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
|
||||
dev_name(&ch->mtu->pdev->dev), ch);
|
||||
if (ret) {
|
||||
dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
|
||||
index, irq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ch->base = mtu->mapbase + channel_offsets[index];
|
||||
ch->index = index;
|
||||
|
||||
return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev));
|
||||
}
|
||||
|
||||
static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu)
|
||||
@@ -422,46 +392,21 @@ static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu)
|
||||
if (mtu->mapbase == NULL)
|
||||
return -ENXIO;
|
||||
|
||||
/*
|
||||
* In legacy platform device configuration (with one device per channel)
|
||||
* the resource points to the channel base address.
|
||||
*/
|
||||
if (mtu->legacy) {
|
||||
struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
|
||||
mtu->mapbase += cfg->channel_offset;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_mtu2_unmap_memory(struct sh_mtu2_device *mtu)
|
||||
{
|
||||
if (mtu->legacy) {
|
||||
struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
|
||||
mtu->mapbase -= cfg->channel_offset;
|
||||
}
|
||||
|
||||
iounmap(mtu->mapbase);
|
||||
}
|
||||
|
||||
static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct sh_timer_config *cfg = pdev->dev.platform_data;
|
||||
const struct platform_device_id *id = pdev->id_entry;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
mtu->pdev = pdev;
|
||||
mtu->legacy = id->driver_data;
|
||||
|
||||
if (mtu->legacy && !cfg) {
|
||||
dev_err(&mtu->pdev->dev, "missing platform data\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
raw_spin_lock_init(&mtu->lock);
|
||||
|
||||
/* Get hold of clock. */
|
||||
mtu->clk = clk_get(&mtu->pdev->dev, mtu->legacy ? "mtu2_fck" : "fck");
|
||||
mtu->clk = clk_get(&mtu->pdev->dev, "fck");
|
||||
if (IS_ERR(mtu->clk)) {
|
||||
dev_err(&mtu->pdev->dev, "cannot get clock\n");
|
||||
return PTR_ERR(mtu->clk);
|
||||
@@ -479,10 +424,7 @@ static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
|
||||
}
|
||||
|
||||
/* Allocate and setup the channels. */
|
||||
if (mtu->legacy)
|
||||
mtu->num_channels = 1;
|
||||
else
|
||||
mtu->num_channels = 3;
|
||||
mtu->num_channels = 3;
|
||||
|
||||
mtu->channels = kzalloc(sizeof(*mtu->channels) * mtu->num_channels,
|
||||
GFP_KERNEL);
|
||||
@@ -491,16 +433,10 @@ static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
|
||||
goto err_unmap;
|
||||
}
|
||||
|
||||
if (mtu->legacy) {
|
||||
ret = sh_mtu2_setup_channel(&mtu->channels[0], 0, mtu);
|
||||
for (i = 0; i < mtu->num_channels; ++i) {
|
||||
ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu);
|
||||
if (ret < 0)
|
||||
goto err_unmap;
|
||||
} else {
|
||||
for (i = 0; i < mtu->num_channels; ++i) {
|
||||
ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu);
|
||||
if (ret < 0)
|
||||
goto err_unmap;
|
||||
}
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, mtu);
|
||||
@@ -509,7 +445,7 @@ static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
|
||||
|
||||
err_unmap:
|
||||
kfree(mtu->channels);
|
||||
sh_mtu2_unmap_memory(mtu);
|
||||
iounmap(mtu->mapbase);
|
||||
err_clk_unprepare:
|
||||
clk_unprepare(mtu->clk);
|
||||
err_clk_put:
|
||||
@@ -560,17 +496,23 @@ static int sh_mtu2_remove(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
static const struct platform_device_id sh_mtu2_id_table[] = {
|
||||
{ "sh_mtu2", 1 },
|
||||
{ "sh-mtu2", 0 },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table);
|
||||
|
||||
static const struct of_device_id sh_mtu2_of_table[] __maybe_unused = {
|
||||
{ .compatible = "renesas,mtu2" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sh_mtu2_of_table);
|
||||
|
||||
static struct platform_driver sh_mtu2_device_driver = {
|
||||
.probe = sh_mtu2_probe,
|
||||
.remove = sh_mtu2_remove,
|
||||
.driver = {
|
||||
.name = "sh_mtu2",
|
||||
.of_match_table = of_match_ptr(sh_mtu2_of_table),
|
||||
},
|
||||
.id_table = sh_mtu2_id_table,
|
||||
};
|
||||
|
||||
@@ -24,6 +24,7 @@
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
@@ -32,7 +33,6 @@
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
enum sh_tmu_model {
|
||||
SH_TMU_LEGACY,
|
||||
SH_TMU,
|
||||
SH_TMU_SH3,
|
||||
};
|
||||
@@ -62,6 +62,8 @@ struct sh_tmu_device {
|
||||
|
||||
enum sh_tmu_model model;
|
||||
|
||||
raw_spinlock_t lock; /* Protect the shared start/stop register */
|
||||
|
||||
struct sh_tmu_channel *channels;
|
||||
unsigned int num_channels;
|
||||
|
||||
@@ -69,8 +71,6 @@ struct sh_tmu_device {
|
||||
bool has_clocksource;
|
||||
};
|
||||
|
||||
static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
|
||||
|
||||
#define TSTR -1 /* shared register */
|
||||
#define TCOR 0 /* channel register */
|
||||
#define TCNT 1 /* channel register */
|
||||
@@ -91,8 +91,6 @@ static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
|
||||
|
||||
if (reg_nr == TSTR) {
|
||||
switch (ch->tmu->model) {
|
||||
case SH_TMU_LEGACY:
|
||||
return ioread8(ch->tmu->mapbase);
|
||||
case SH_TMU_SH3:
|
||||
return ioread8(ch->tmu->mapbase + 2);
|
||||
case SH_TMU:
|
||||
@@ -115,8 +113,6 @@ static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
|
||||
|
||||
if (reg_nr == TSTR) {
|
||||
switch (ch->tmu->model) {
|
||||
case SH_TMU_LEGACY:
|
||||
return iowrite8(value, ch->tmu->mapbase);
|
||||
case SH_TMU_SH3:
|
||||
return iowrite8(value, ch->tmu->mapbase + 2);
|
||||
case SH_TMU:
|
||||
@@ -137,7 +133,7 @@ static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
|
||||
unsigned long flags, value;
|
||||
|
||||
/* start stop register shared by multiple timer channels */
|
||||
raw_spin_lock_irqsave(&sh_tmu_lock, flags);
|
||||
raw_spin_lock_irqsave(&ch->tmu->lock, flags);
|
||||
value = sh_tmu_read(ch, TSTR);
|
||||
|
||||
if (start)
|
||||
@@ -146,7 +142,7 @@ static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
|
||||
value &= ~(1 << ch->index);
|
||||
|
||||
sh_tmu_write(ch, TSTR, value);
|
||||
raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);
|
||||
}
|
||||
|
||||
static int __sh_tmu_enable(struct sh_tmu_channel *ch)
|
||||
@@ -476,27 +472,12 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
|
||||
return 0;
|
||||
|
||||
ch->tmu = tmu;
|
||||
ch->index = index;
|
||||
|
||||
if (tmu->model == SH_TMU_LEGACY) {
|
||||
struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
|
||||
|
||||
/*
|
||||
* The SH3 variant (SH770x, SH7705, SH7710 and SH7720) maps
|
||||
* channel registers blocks at base + 2 + 12 * index, while all
|
||||
* other variants map them at base + 4 + 12 * index. We can
|
||||
* compute the index by just dividing by 12, the 2 bytes or 4
|
||||
* bytes offset being hidden by the integer division.
|
||||
*/
|
||||
ch->index = cfg->channel_offset / 12;
|
||||
ch->base = tmu->mapbase + cfg->channel_offset;
|
||||
} else {
|
||||
ch->index = index;
|
||||
|
||||
if (tmu->model == SH_TMU_SH3)
|
||||
ch->base = tmu->mapbase + 4 + ch->index * 12;
|
||||
else
|
||||
ch->base = tmu->mapbase + 8 + ch->index * 12;
|
||||
}
|
||||
if (tmu->model == SH_TMU_SH3)
|
||||
ch->base = tmu->mapbase + 4 + ch->index * 12;
|
||||
else
|
||||
ch->base = tmu->mapbase + 8 + ch->index * 12;
|
||||
|
||||
ch->irq = platform_get_irq(tmu->pdev, index);
|
||||
if (ch->irq < 0) {
|
||||
@@ -526,46 +507,53 @@ static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
|
||||
if (tmu->mapbase == NULL)
|
||||
return -ENXIO;
|
||||
|
||||
/*
|
||||
* In legacy platform device configuration (with one device per channel)
|
||||
* the resource points to the channel base address.
|
||||
*/
|
||||
if (tmu->model == SH_TMU_LEGACY) {
|
||||
struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
|
||||
tmu->mapbase -= cfg->channel_offset;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
|
||||
{
|
||||
struct device_node *np = tmu->pdev->dev.of_node;
|
||||
|
||||
tmu->model = SH_TMU;
|
||||
tmu->num_channels = 3;
|
||||
|
||||
of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
|
||||
|
||||
if (tmu->num_channels != 2 && tmu->num_channels != 3) {
|
||||
dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
|
||||
tmu->num_channels);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_tmu_unmap_memory(struct sh_tmu_device *tmu)
|
||||
{
|
||||
if (tmu->model == SH_TMU_LEGACY) {
|
||||
struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
|
||||
tmu->mapbase += cfg->channel_offset;
|
||||
}
|
||||
|
||||
iounmap(tmu->mapbase);
|
||||
}
|
||||
|
||||
static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
|
||||
{
|
||||
struct sh_timer_config *cfg = pdev->dev.platform_data;
|
||||
const struct platform_device_id *id = pdev->id_entry;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
if (!cfg) {
|
||||
tmu->pdev = pdev;
|
||||
|
||||
raw_spin_lock_init(&tmu->lock);
|
||||
|
||||
if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
|
||||
ret = sh_tmu_parse_dt(tmu);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
} else if (pdev->dev.platform_data) {
|
||||
const struct platform_device_id *id = pdev->id_entry;
|
||||
struct sh_timer_config *cfg = pdev->dev.platform_data;
|
||||
|
||||
tmu->model = id->driver_data;
|
||||
tmu->num_channels = hweight8(cfg->channels_mask);
|
||||
} else {
|
||||
dev_err(&tmu->pdev->dev, "missing platform data\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
tmu->pdev = pdev;
|
||||
tmu->model = id->driver_data;
|
||||
|
||||
/* Get hold of clock. */
|
||||
tmu->clk = clk_get(&tmu->pdev->dev,
|
||||
tmu->model == SH_TMU_LEGACY ? "tmu_fck" : "fck");
|
||||
tmu->clk = clk_get(&tmu->pdev->dev, "fck");
|
||||
if (IS_ERR(tmu->clk)) {
|
||||
dev_err(&tmu->pdev->dev, "cannot get clock\n");
|
||||
return PTR_ERR(tmu->clk);
|
||||
@@ -583,11 +571,6 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
|
||||
}
|
||||
|
||||
/* Allocate and setup the channels. */
|
||||
if (tmu->model == SH_TMU_LEGACY)
|
||||
tmu->num_channels = 1;
|
||||
else
|
||||
tmu->num_channels = hweight8(cfg->channels_mask);
|
||||
|
||||
tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels,
|
||||
GFP_KERNEL);
|
||||
if (tmu->channels == NULL) {
|
||||
@@ -595,23 +578,15 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
|
||||
goto err_unmap;
|
||||
}
|
||||
|
||||
if (tmu->model == SH_TMU_LEGACY) {
|
||||
ret = sh_tmu_channel_setup(&tmu->channels[0], 0,
|
||||
cfg->clockevent_rating != 0,
|
||||
cfg->clocksource_rating != 0, tmu);
|
||||
/*
|
||||
* Use the first channel as a clock event device and the second channel
|
||||
* as a clock source.
|
||||
*/
|
||||
for (i = 0; i < tmu->num_channels; ++i) {
|
||||
ret = sh_tmu_channel_setup(&tmu->channels[i], i,
|
||||
i == 0, i == 1, tmu);
|
||||
if (ret < 0)
|
||||
goto err_unmap;
|
||||
} else {
|
||||
/*
|
||||
* Use the first channel as a clock event device and the second
|
||||
* channel as a clock source.
|
||||
*/
|
||||
for (i = 0; i < tmu->num_channels; ++i) {
|
||||
ret = sh_tmu_channel_setup(&tmu->channels[i], i,
|
||||
i == 0, i == 1, tmu);
|
||||
if (ret < 0)
|
||||
goto err_unmap;
|
||||
}
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, tmu);
|
||||
@@ -620,7 +595,7 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
|
||||
|
||||
err_unmap:
|
||||
kfree(tmu->channels);
|
||||
sh_tmu_unmap_memory(tmu);
|
||||
iounmap(tmu->mapbase);
|
||||
err_clk_unprepare:
|
||||
clk_unprepare(tmu->clk);
|
||||
err_clk_put:
|
||||
@@ -671,18 +646,24 @@ static int sh_tmu_remove(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
static const struct platform_device_id sh_tmu_id_table[] = {
|
||||
{ "sh_tmu", SH_TMU_LEGACY },
|
||||
{ "sh-tmu", SH_TMU },
|
||||
{ "sh-tmu-sh3", SH_TMU_SH3 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
|
||||
|
||||
static const struct of_device_id sh_tmu_of_table[] __maybe_unused = {
|
||||
{ .compatible = "renesas,tmu" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sh_tmu_of_table);
|
||||
|
||||
static struct platform_driver sh_tmu_device_driver = {
|
||||
.probe = sh_tmu_probe,
|
||||
.remove = sh_tmu_remove,
|
||||
.driver = {
|
||||
.name = "sh_tmu",
|
||||
.of_match_table = of_match_ptr(sh_tmu_of_table),
|
||||
},
|
||||
.id_table = sh_tmu_id_table,
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user