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Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC 64-bit changes from Olof Johansson: "Mostly DT updates for arm64, but also a couple of Kconfig additions. Main contents: - Qualcomm MSM8916/APQ8016 - Spreadtrum SC9836 - Xilinx ZynqMP - pincontrol entries for MediaTek MT8173" * tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: dts: add interrupt-affinity property to pmu node for juno arm64: dts: Add Qualcomm APQ8016 SBC evaluation board dts arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts arm64: dts: sprd: adding coresight entries to Spreadtrum SC9836 arm64: Add support for Spreadtrum's Sharkl64 Platform in Kconfig and defconfig arm64: dts: Add support for Spreadtrum SC9836 SoC in dts and Makefile ARM64: Add new Xilinx ZynqMP SoC arm64: qcom: Add support for Qualcomm MSM8916 SoC arm64: dts: mt8173: Add pinctrl/GPIO/EINT node for mt8173. arm64: mediatek: Select PINCTRL for Mediatek platform
This commit is contained in:
Linus Torvalds
@@ -181,9 +181,16 @@ config ARCH_FSL_LS2085A
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config ARCH_MEDIATEK
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bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
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select ARM_GIC
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select PINCTRL
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help
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Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
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config ARCH_QCOM
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bool "Qualcomm Platforms"
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select PINCTRL
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help
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This enables support for the ARMv8 based Qualcomm chipsets.
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config ARCH_SEATTLE
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bool "AMD Seattle SoC Family"
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help
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@@ -215,6 +222,11 @@ config ARCH_TEGRA_132_SOC
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but contains an NVIDIA Denver CPU complex in place of
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Tegra124's "4+1" Cortex-A15 CPU complex.
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config ARCH_SPRD
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bool "Spreadtrum SoC platform"
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help
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Support for Spreadtrum ARM based SoCs
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config ARCH_THUNDER
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bool "Cavium Inc. Thunder SoC Family"
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help
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@@ -235,6 +247,11 @@ config ARCH_XGENE
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help
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This enables support for AppliedMicro X-Gene SOC Family
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config ARCH_ZYNQMP
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bool "Xilinx ZynqMP Family"
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help
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This enables support for Xilinx ZynqMP Family
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endmenu
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menu "Bus support"
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@@ -5,5 +5,8 @@ dts-dirs += cavium
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dts-dirs += exynos
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dts-dirs += freescale
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dts-dirs += mediatek
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dts-dirs += qcom
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dts-dirs += sprd
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dts-dirs += xilinx
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subdir-y := $(dts-dirs)
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@@ -120,12 +120,18 @@
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&A57_0>,
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<&A57_1>,
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<&A53_0>,
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<&A53_1>,
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<&A53_2>,
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<&A53_3>;
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};
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/include/ "juno-clocks.dtsi"
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File diff suppressed because it is too large
Load Diff
@@ -13,6 +13,7 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "mt8173-pinfunc.h"
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/ {
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compatible = "mediatek,mt8173";
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@@ -105,6 +106,25 @@
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compatible = "simple-bus";
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ranges;
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syscfg_pctl_a: syscfg_pctl_a@10005000 {
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compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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pio: pinctrl@0x10005000 {
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compatible = "mediatek,mt8173-pinctrl";
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reg = <0 0x1000B000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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};
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sysirq: intpol-controller@10200620 {
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compatible = "mediatek,mt8173-sysirq",
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"mediatek,mt6577-sysirq";
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@@ -0,0 +1,5 @@
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dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb
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@@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "apq8016-sbc.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
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compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc";
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};
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@@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "msm8916.dtsi"
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/ {
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aliases {
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serial0 = &blsp1_uart2;
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};
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chosen {
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stdout-path = "serial0";
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};
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soc {
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serial@78b0000 {
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_uart2_default>;
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pinctrl-1 = <&blsp1_uart2_sleep>;
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};
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};
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};
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@@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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||||
* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "msm8916-mtp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
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compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
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"qcom,msm8916", "qcom,mtp";
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};
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@@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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||||
* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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||||
*
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||||
* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "msm8916.dtsi"
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/ {
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aliases {
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serial0 = &blsp1_uart2;
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};
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chosen {
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stdout-path = "serial0";
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};
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soc {
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serial@78b0000 {
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_uart2_default>;
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pinctrl-1 = <&blsp1_uart2_sleep>;
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};
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};
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};
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@@ -0,0 +1,196 @@
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/*
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* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8916.h>
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#include <dt-bindings/reset/qcom,gcc-msm8916.h>
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/ {
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model = "Qualcomm Technologies, Inc. MSM8916";
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compatible = "qcom,msm8916";
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases { };
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chosen { };
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x1>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x2>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x3>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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||||
pinctrl@1000000 {
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compatible = "qcom,msm8916-pinctrl";
|
||||
reg = <0x1000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
blsp1_uart2_default: blsp1_uart2_default {
|
||||
pinmux {
|
||||
function = "blsp_uart2";
|
||||
pins = "gpio4", "gpio5";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
blsp1_uart2_sleep: blsp1_uart2_sleep {
|
||||
pinmux {
|
||||
function = "blsp_uart2";
|
||||
pins = "gpio4", "gpio5";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gcc: qcom,gcc@1800000 {
|
||||
compatible = "qcom,gcc-msm8916";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x1800000 0x80000>;
|
||||
};
|
||||
|
||||
blsp1_uart2: serial@78b0000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78b0000 0x200>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@b000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
|
||||
};
|
||||
|
||||
timer@b020000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0xb020000 0x1000>;
|
||||
clock-frequency = <19200000>;
|
||||
|
||||
frame@b021000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xb021000 0x1000>,
|
||||
<0xb022000 0x1000>;
|
||||
};
|
||||
|
||||
frame@b023000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xb023000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b024000 {
|
||||
frame-number = <2>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xb024000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b025000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xb025000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b026000 {
|
||||
frame-number = <4>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xb026000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b027000 {
|
||||
frame-number = <5>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xb027000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b028000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xb028000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,5 @@
|
||||
dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Spreadtrum SC9836 openphone board DTS file
|
||||
*
|
||||
* Copyright (C) 2014, Spreadtrum Communications Inc.
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or X11 license.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc9836.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Spreadtrum SC9836 Openphone Board";
|
||||
|
||||
compatible = "sprd,sc9836-openphone", "sprd,sc9836";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x80000000 0 0x20000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial1:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,129 @@
|
||||
/*
|
||||
* Spreadtrum SC9836 SoC DTS file
|
||||
*
|
||||
* Copyright (C) 2014, Spreadtrum Communications Inc.
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or X11 license.
|
||||
*/
|
||||
|
||||
#include "sharkl64.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "sprd,sc9836";
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
etf@10003000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x10003000 0 0x1000>;
|
||||
clocks = <&clk26mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
port {
|
||||
etf_in: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&funnel_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@10001000 {
|
||||
compatible = "arm,coresight-funnel", "arm,primecell";
|
||||
reg = <0 0x10001000 0 0x1000>;
|
||||
clocks = <&clk26mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* funnel output port */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel_out_port0: endpoint {
|
||||
remote-endpoint = <&etf_in>;
|
||||
};
|
||||
};
|
||||
|
||||
/* funnel input port 0~3 is reserved for ETMs */
|
||||
port@1 {
|
||||
reg = <4>;
|
||||
funnel_in_port4: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&stm_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
stm@10006000 {
|
||||
compatible = "arm,coresight-stm", "arm,primecell";
|
||||
reg = <0 0x10006000 0 0x1000>,
|
||||
<0 0x01000000 0 0x180000>;
|
||||
reg-names = "stm-base", "stm-stimulus-base";
|
||||
clocks = <&clk26mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
port {
|
||||
stm_out: endpoint {
|
||||
remote-endpoint = <&funnel_in_port4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@12001000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0 0x12001000 0 0x1000>,
|
||||
<0 0x12002000 0 0x2000>,
|
||||
<0 0x12004000 0 0x2000>,
|
||||
<0 0x12006000 0 0x2000>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci";
|
||||
method = "smc";
|
||||
cpu_on = <0xc4000003>;
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_suspend = <0xc4000001>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Spreadtrum Sharkl64 platform DTS file
|
||||
*
|
||||
* Copyright (C) 2014, Spreadtrum Communications Inc.
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or X11 license.
|
||||
*/
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ap-apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
uart0: serial@70000000 {
|
||||
compatible = "sprd,sc9836-uart";
|
||||
reg = <0 0x70000000 0 0x100>;
|
||||
interrupts = <0 2 0xf04>;
|
||||
clocks = <&clk26mhz>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@70100000 {
|
||||
compatible = "sprd,sc9836-uart";
|
||||
reg = <0 0x70100000 0 0x100>;
|
||||
interrupts = <0 3 0xf04>;
|
||||
clocks = <&clk26mhz>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@70200000 {
|
||||
compatible = "sprd,sc9836-uart";
|
||||
reg = <0 0x70200000 0 0x100>;
|
||||
interrupts = <0 4 0xf04>;
|
||||
clocks = <&clk26mhz>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@70300000 {
|
||||
compatible = "sprd,sc9836-uart";
|
||||
reg = <0 0x70300000 0 0x100>;
|
||||
interrupts = <0 5 0xf04>;
|
||||
clocks = <&clk26mhz>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clk26mhz: clk26mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,5 @@
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ep108 development board
|
||||
*
|
||||
* (C) Copyright 2014 - 2015, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "zynqmp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP EP108";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0{
|
||||
reg = <0>;
|
||||
max-speed = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,305 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP
|
||||
*
|
||||
* (C) Copyright 2014 - 2015, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
/ {
|
||||
compatible = "xlnx,zynqmp";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x3>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 143 4>,
|
||||
<0 144 4>,
|
||||
<0 145 4>,
|
||||
<0 146 4>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <1 13 0xf01>,
|
||||
<1 14 0xf01>,
|
||||
<1 11 0xf01>,
|
||||
<1 10 0xf01>;
|
||||
};
|
||||
|
||||
amba_apu {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@f9010000 {
|
||||
compatible = "arm,gic-400", "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x0 0xf9010000 0x10000>,
|
||||
<0x0 0xf902f000 0x2000>,
|
||||
<0x0 0xf9040000 0x20000>,
|
||||
<0x0 0xf906f000 0x2000>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
};
|
||||
|
||||
amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
misc_clk: misc_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
ttc0: timer@ff110000 {
|
||||
compatible = "cdns,ttc";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
|
||||
reg = <0x0 0xff110000 0x1000>;
|
||||
clocks = <&misc_clk>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
ttc1: timer@ff120000 {
|
||||
compatible = "cdns,ttc";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
|
||||
reg = <0x0 0xff120000 0x1000>;
|
||||
clocks = <&misc_clk>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
ttc2: timer@ff130000 {
|
||||
compatible = "cdns,ttc";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
|
||||
reg = <0x0 0xff130000 0x1000>;
|
||||
clocks = <&misc_clk>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
ttc3: timer@ff140000 {
|
||||
compatible = "cdns,ttc";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
|
||||
reg = <0x0 0xff140000 0x1000>;
|
||||
clocks = <&misc_clk>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
uart0: serial@ff000000 {
|
||||
compatible = "cdns,uart-r1p8";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 21 4>;
|
||||
reg = <0x0 0xff000000 0x1000>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
uart1: serial@ff010000 {
|
||||
compatible = "cdns,uart-r1p8";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 22 4>;
|
||||
reg = <0x0 0xff010000 0x1000>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
gpio: gpio@ff0a0000 {
|
||||
compatible = "xlnx,zynq-gpio-1.0";
|
||||
status = "disabled";
|
||||
#gpio-cells = <0x2>;
|
||||
clocks = <&misc_clk>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 16 4>;
|
||||
reg = <0x0 0xff0a0000 0x1000>;
|
||||
};
|
||||
|
||||
gem0: ethernet@ff0b0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 57 4>, <0 57 4>;
|
||||
reg = <0x0 0xff0b0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gem1: ethernet@ff0c0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 59 4>, <0 59 4>;
|
||||
reg = <0x0 0xff0c0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gem2: ethernet@ff0d0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 61 4>, <0 61 4>;
|
||||
reg = <0x0 0xff0d0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gem3: ethernet@ff0e0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 63 4>, <0 63 4>;
|
||||
reg = <0x0 0xff0e0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi0: spi@ff040000 {
|
||||
compatible = "cdns,spi-r1p6";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 19 4>;
|
||||
reg = <0x0 0xff040000 0x1000>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@ff050000 {
|
||||
compatible = "cdns,spi-r1p6";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 20 4>;
|
||||
reg = <0x0 0xff050000 0x1000>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c_clk: i2c_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0x0>;
|
||||
clock-frequency = <111111111>;
|
||||
};
|
||||
|
||||
i2c0: i2c@ff020000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 17 4>;
|
||||
reg = <0x0 0xff020000 0x1000>;
|
||||
clocks = <&i2c_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@ff030000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 18 4>;
|
||||
reg = <0x0 0xff030000 0x1000>;
|
||||
clocks = <&i2c_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
sdhci0: sdhci@ff160000 {
|
||||
compatible = "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 48 4>;
|
||||
reg = <0x0 0xff160000 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
sdhci1: sdhci@ff170000 {
|
||||
compatible = "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 49 4>;
|
||||
reg = <0x0 0xff170000 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
watchdog0: watchdog@fd4d0000 {
|
||||
compatible = "cdns,wdt-r1p2";
|
||||
status = "disabled";
|
||||
clocks= <&misc_clk>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 52 1>;
|
||||
reg = <0x0 0xfd4d0000 0x1000>;
|
||||
timeout-sec = <10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -37,9 +37,12 @@ CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_ARCH_SEATTLE=y
|
||||
CONFIG_ARCH_TEGRA=y
|
||||
CONFIG_ARCH_TEGRA_132_SOC=y
|
||||
CONFIG_ARCH_QCOM=y
|
||||
CONFIG_ARCH_SPRD=y
|
||||
CONFIG_ARCH_THUNDER=y
|
||||
CONFIG_ARCH_VEXPRESS=y
|
||||
CONFIG_ARCH_XGENE=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_XGENE=y
|
||||
@@ -99,11 +102,16 @@ CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_MT6577=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
||||
CONFIG_VIRTIO_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_PINCTRL_MSM8916=y
|
||||
CONFIG_GPIO_PL061=y
|
||||
CONFIG_GPIO_XGENE=y
|
||||
CONFIG_POWER_RESET_XGENE=y
|
||||
@@ -136,6 +144,8 @@ CONFIG_RTC_DRV_XGENE=y
|
||||
CONFIG_VIRTIO_PCI=y
|
||||
CONFIG_VIRTIO_BALLOON=y
|
||||
CONFIG_VIRTIO_MMIO=y
|
||||
CONFIG_COMMON_CLK_QCOM=y
|
||||
CONFIG_MSM_GCC_8916=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_PHY_XGENE=y
|
||||
CONFIG_EXT2_FS=y
|
||||
|
||||
Reference in New Issue
Block a user