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[ARM] 4143/1: AT91: Prepare for AT91SAM9263 support

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The Atmel AT91SAM9263 processor includes many more integrated
peripherals than Atmel's previous ARM9-based AT91 processors, so this
has necessitated a few changes to the core AT91 support.

These changes are:
      * The system peripheral I/O region we remap has increased from
        0xFFFA0000..0xFFFFFFFF to 0xFFF78000..0xFFFFFFFF.
      * The increased I/O region forces changes to entry-macro.S and
        debug-macro.S due to ARM's limited immediate offset addressing
        modes.
      * Maximum number of GPIO banks increases to 5.
      * 2 MMC controllers so the board-setup code needs to specify which
        controller it wishes to use when calling at91_add_device_mmc().

Original patch from Nicolas Ferre.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor
2007-02-08 09:00:39 +01:00
committed by Russell King
parent 9d0412680e
commit d0760b3bc8
18 changed files with 72 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/asm-arm/arch-at91/debug-macro.S
+8 -8
View File
@@ -16,24 +16,24 @@
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =AT91_BASE_SYS @ System peripherals (phys address)
ldrne \rx, =AT91_VA_BASE_SYS @ System peripherals (virt address)
tst \rx, #1 @ MMU enabled?
ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
ldrne \rx, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #AT91_DBGU_THR] @ Write to Transmitter Holding Register
strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register
tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register
tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register
tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register
tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
beq 1001b
.endm