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Merge branches 'at91', 'davinci', 'imx', 'iop', 'ixp', 'ks8695', 'misc', 'pxa' and 's3c' into devel

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This commit is contained in:
Russell King
2007-07-12 21:30:18 +01:00
committed by Russell King
parent feb4722552 83f53220f8 89bba43514 51198ea947 eab03b3f66 8a87a996ea fcae8e0988 46c41e62a1 3c3e69cd4c
commit ca9ced7f67
76 changed files with 2915 additions and 485 deletions
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include/asm-arm/Kbuild
+2
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@@ -1 +1,3 @@
include include/asm-generic/Kbuild.asm
unifdef-y += hwcap.h
include/asm-arm/arch-davinci/clock.h
+22
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@@ -0,0 +1,22 @@
/*
* include/asm-arm/arch-davinci/clock.h
*
* Clock control driver for DaVinci - header file
*
* Authors: Vladimir Barinov <source@mvista.com>
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_DAVINCI_CLOCK_H
#define __ASM_ARCH_DAVINCI_CLOCK_H
struct clk;
extern int clk_register(struct clk *clk);
extern void clk_unregister(struct clk *clk);
extern int davinci_clk_init(void);
#endif
include/asm-arm/arch-davinci/gpio.h
+156
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@@ -0,0 +1,156 @@
/*
* TI DaVinci GPIO Support
*
* Copyright (c) 2006 David Brownell
* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DAVINCI_GPIO_H
#define __DAVINCI_GPIO_H
/*
* basic gpio routines
*
* board-specific init should be done by arch/.../.../board-XXX.c (maybe
* initializing banks together) rather than boot loaders; kexec() won't
* go through boot loaders.
*
* the gpio clock will be turned on when gpios are used, and you may also
* need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
* used as gpios, not with other peripherals.
*
* GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe
* for later updates, code should write GPIO(N) or:
* - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
* - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
*
* For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
* for now, that's != GPIO(N)
*/
#define GPIO(X) (X) /* 0 <= X <= 70 */
#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */
#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */
struct gpio_controller {
u32 dir;
u32 out_data;
u32 set_data;
u32 clr_data;
u32 in_data;
u32 set_rising;
u32 clr_rising;
u32 set_falling;
u32 clr_falling;
u32 intstat;
};
/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
* with constant parameters; or in outlined code they execute at runtime.
*
* You'd access the controller directly when reading or writing more than
* one gpio value at a time, and to support wired logic where the value
* being driven by the cpu need not match the value read back.
*
* These are NOT part of the cross-platform GPIO interface
*/
static inline struct gpio_controller *__iomem
__gpio_to_controller(unsigned gpio)
{
void *__iomem ptr;
if (gpio < 32)
ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
else if (gpio < 64)
ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
else if (gpio < DAVINCI_N_GPIO)
ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
else
ptr = NULL;
return ptr;
}
static inline u32 __gpio_mask(unsigned gpio)
{
return 1 << (gpio % 32);
}
/* The get/set/clear functions will inline when called with constant
* parameters, for low-overhead bitbanging. Illegal constant parameters
* cause link-time errors.
*
* Otherwise, calls with variable parameters use outlined functions.
*/
extern int __error_inval_gpio(void);
extern void __gpio_set(unsigned gpio, int value);
extern int __gpio_get(unsigned gpio);
static inline void gpio_set_value(unsigned gpio, int value)
{
if (__builtin_constant_p(value)) {
struct gpio_controller *__iomem g;
u32 mask;
if (gpio >= DAVINCI_N_GPIO)
__error_inval_gpio();
g = __gpio_to_controller(gpio);
mask = __gpio_mask(gpio);
if (value)
__raw_writel(mask, &g->set_data);
else
__raw_writel(mask, &g->clr_data);
return;
}
__gpio_set(gpio, value);
}
/* Returns zero or nonzero; works for gpios configured as inputs OR
* as outputs.
*
* NOTE: changes in reported values are synchronized to the GPIO clock.
* This is most easily seen after calling gpio_set_value() and then immediatly
* gpio_get_value(), where the gpio_get_value() would return the old value
* until the GPIO clock ticks and the new value gets latched.
*/
static inline int gpio_get_value(unsigned gpio)
{
struct gpio_controller *__iomem g;
if (!__builtin_constant_p(gpio))
return __gpio_get(gpio);
if (gpio >= DAVINCI_N_GPIO)
return __error_inval_gpio();
g = __gpio_to_controller(gpio);
return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
}
/* powerup default direction is IN */
extern int gpio_direction_input(unsigned gpio);
extern int gpio_direction_output(unsigned gpio, int value);
#include <asm-generic/gpio.h> /* cansleep wrappers */
extern int gpio_request(unsigned gpio, const char *tag);
extern void gpio_free(unsigned gpio);
static inline int gpio_to_irq(unsigned gpio)
{
return DAVINCI_N_AINTC_IRQ + gpio;
}
static inline int irq_to_gpio(unsigned irq)
{
return irq - DAVINCI_N_AINTC_IRQ;
}
#endif /* __DAVINCI_GPIO_H */
include/asm-arm/arch-davinci/hardware.h
+38
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@@ -11,4 +11,42 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/*
* Base register addresses
*/
#define DAVINCI_DMA_3PCC_BASE (0x01C00000)
#define DAVINCI_DMA_3PTC0_BASE (0x01C10000)
#define DAVINCI_DMA_3PTC1_BASE (0x01C10400)
#define DAVINCI_I2C_BASE (0x01C21000)
#define DAVINCI_PWM0_BASE (0x01C22000)
#define DAVINCI_PWM1_BASE (0x01C22400)
#define DAVINCI_PWM2_BASE (0x01C22800)
#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000)
#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800)
#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00)
#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000)
#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000)
#define DAVINCI_IEEE1394_BASE (0x01C60000)
#define DAVINCI_USB_OTG_BASE (0x01C64000)
#define DAVINCI_CFC_ATA_BASE (0x01C66000)
#define DAVINCI_SPI_BASE (0x01C66800)
#define DAVINCI_GPIO_BASE (0x01C67000)
#define DAVINCI_UHPI_BASE (0x01C67800)
#define DAVINCI_VPSS_REGS_BASE (0x01C70000)
#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000)
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000)
#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000)
#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000)
#define DAVINCI_IMCOP_BASE (0x01CC0000)
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000)
#define DAVINCI_VLYNQ_BASE (0x01E01000)
#define DAVINCI_MCBSP_BASE (0x01E02000)
#define DAVINCI_MMC_SD_BASE (0x01E10000)
#define DAVINCI_MS_BASE (0x01E20000)
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000)
#endif /* __ASM_ARCH_HARDWARE_H */
include/asm-arm/arch-davinci/mux.h
+55
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@@ -0,0 +1,55 @@
/*
* DaVinci pin multiplexing defines
*
* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_MUX_H
#define __ASM_ARCH_MUX_H
#define DAVINCI_MUX_AEAW0 0
#define DAVINCI_MUX_AEAW1 1
#define DAVINCI_MUX_AEAW2 2
#define DAVINCI_MUX_AEAW3 3
#define DAVINCI_MUX_AEAW4 4
#define DAVINCI_MUX_AECS4 10
#define DAVINCI_MUX_AECS5 11
#define DAVINCI_MUX_VLYNQWD0 12
#define DAVINCI_MUX_VLYNQWD1 13
#define DAVINCI_MUX_VLSCREN 14
#define DAVINCI_MUX_VLYNQEN 15
#define DAVINCI_MUX_HDIREN 16
#define DAVINCI_MUX_ATAEN 17
#define DAVINCI_MUX_RGB666 22
#define DAVINCI_MUX_RGB888 23
#define DAVINCI_MUX_LOEEN 24
#define DAVINCI_MUX_LFLDEN 25
#define DAVINCI_MUX_CWEN 26
#define DAVINCI_MUX_CFLDEN 27
#define DAVINCI_MUX_HPIEN 29
#define DAVINCI_MUX_1394EN 30
#define DAVINCI_MUX_EMACEN 31
#define DAVINCI_MUX_LEVEL2 32
#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0)
#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1)
#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2)
#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3)
#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4)
#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5)
#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6)
#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7)
#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8)
#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9)
#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10)
#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16)
#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17)
#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18)
extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable);
#endif /* __ASM_ARCH_MUX_H */
include/asm-arm/arch-imx/gpio.h
+102
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@@ -0,0 +1,102 @@
#ifndef _IMX_GPIO_H
#include <asm/arch/imx-regs.h>
#define IMX_GPIO_ALLOC_MODE_NORMAL 0
#define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1
#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2
#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4
#define IMX_GPIO_ALLOC_MODE_RELEASE 8
extern int imx_gpio_request(unsigned gpio, const char *label);
extern void imx_gpio_free(unsigned gpio);
extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
int alloc_mode, const char *label);
extern int imx_gpio_direction_input(unsigned gpio);
extern int imx_gpio_direction_output(unsigned gpio, int value);
extern void __imx_gpio_set_value(unsigned gpio, int value);
static inline int imx_gpio_get_value(unsigned gpio)
{
return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK));
}
static inline void imx_gpio_set_value_inline(unsigned gpio, int value)
{
unsigned long flags;
raw_local_irq_save(flags);
if(value)
DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK));
else
DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK));
raw_local_irq_restore(flags);
}
static inline void imx_gpio_set_value(unsigned gpio, int value)
{
if(__builtin_constant_p(gpio))
imx_gpio_set_value_inline(gpio, value);
else
__imx_gpio_set_value(gpio, value);
}
extern int imx_gpio_to_irq(unsigned gpio);
extern int imx_irq_to_gpio(unsigned irq);
/*-------------------------------------------------------------------------*/
/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions
* to allow future extension of GPIO logic.
*/
static inline int gpio_request(unsigned gpio, const char *label)
{
return imx_gpio_request(gpio, label);
}
static inline void gpio_free(unsigned gpio)
{
imx_gpio_free(gpio);
}
static inline int gpio_direction_input(unsigned gpio)
{
return imx_gpio_direction_input(gpio);
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
return imx_gpio_direction_output(gpio, value);
}
static inline int gpio_get_value(unsigned gpio)
{
return imx_gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
imx_gpio_set_value(gpio, value);
}
#include <asm-generic/gpio.h> /* cansleep wrappers */
static inline int gpio_to_irq(unsigned gpio)
{
return imx_gpio_to_irq(gpio);
}
static inline int irq_to_gpio(unsigned irq)
{
return imx_irq_to_gpio(irq);
}
#endif
include/asm-arm/arch-imx/imx-regs.h
+2
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@@ -77,6 +77,8 @@
#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
#define GPIO_PORT_MAX 3
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_MASK (0x3 << 5)
include/asm-arm/arch-ixp4xx/ixdp425.h
+4
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@@ -32,4 +32,8 @@
#define IXDP425_PCI_INTC_PIN 9
#define IXDP425_PCI_INTD_PIN 8
/* NAND Flash pins */
#define IXDP425_NAND_NCE_PIN 12
#define IXDP425_NAND_CMD_BYTE 0x01
#define IXDP425_NAND_ADDR_BYTE 0x02
include/asm-arm/arch-ixp4xx/uncompress.h
+3 -2
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@@ -38,9 +38,10 @@ static void flush(void)
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
/*
* Coyote and gtwx5715 only have UART2 connected
* Some boards are using UART2 as console
*/
if (machine_is_adi_coyote() || machine_is_gtwx5715())
if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
machine_is_gateway7001() || machine_is_wg302v2())
uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
else
uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
include/asm-arm/arch-ks8695/gpio.h
+79
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@@ -0,0 +1,79 @@
/*
* include/asm-arm/arch-ks8695/gpio.h
*
* Copyright (C) 2006 Andrew Victor
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H_
#define __ASM_ARCH_GPIO_H_
#define KS8695_GPIO_0 0
#define KS8695_GPIO_1 1
#define KS8695_GPIO_2 2
#define KS8695_GPIO_3 3
#define KS8695_GPIO_4 4
#define KS8695_GPIO_5 5
#define KS8695_GPIO_6 6
#define KS8695_GPIO_7 7
#define KS8695_GPIO_8 8
#define KS8695_GPIO_9 9
#define KS8695_GPIO_10 10
#define KS8695_GPIO_11 11
#define KS8695_GPIO_12 12
#define KS8695_GPIO_13 13
#define KS8695_GPIO_14 14
#define KS8695_GPIO_15 15
/*
* Configure GPIO pin as external interrupt source.
*/
int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type);
/*
* Configure the GPIO line as an input.
*/
int __init_or_module gpio_direction_input(unsigned int pin);
/*
* Configure the GPIO line as an output, with default state.
*/
int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state);
/*
* Set the state of an output GPIO line.
*/
void gpio_set_value(unsigned int pin, unsigned int state);
/*
* Read the state of a GPIO line.
*/
int gpio_get_value(unsigned int pin);
/*
* Map GPIO line to IRQ number.
*/
int gpio_to_irq(unsigned int pin);
/*
* Map IRQ number to GPIO line.
*/
int irq_to_gpio(unsigned int irq);
#include <asm-generic/gpio.h>
static inline int gpio_request(unsigned int pin, const char *label)
{
return 0;
}
static inline void gpio_free(unsigned int pin)
{
}
#endif
include/asm-arm/arch-pxa/dma.h
+2 -20
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@@ -30,30 +30,12 @@ typedef enum {
DMA_PRIO_LOW = 2
} pxa_dma_prio;
#if defined(CONFIG_PXA27x)
#define PXA_DMA_CHANNELS 32
#define pxa_for_each_dma_prio(ch, prio) \
for ( \
ch = prio * 4; \
ch != (4 << prio) + 16; \
ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \
)
#elif defined(CONFIG_PXA25x)
#define PXA_DMA_CHANNELS 16
#define pxa_for_each_dma_prio(ch, prio) \
for (ch = prio * 4; ch != (4 << prio); ch++)
#endif
/*
* DMA registration
*/
int __init pxa_init_dma(int num_ch);
int pxa_request_dma (char *name,
pxa_dma_prio prio,
void (*irq_handler)(int, void *),
include/asm-arm/arch-pxa/entry-macro.S
+24 -6
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@@ -20,20 +20,38 @@
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#ifdef CONFIG_PXA27x
mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
#else
mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
mov \tmp, \tmp, lsr #13
and \tmp, \tmp, #0x7 @ Core G
cmp \tmp, #1
bhi 1004f
mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
add \base, \base, #0x00d00000
ldr \irqstat, [\base, #0] @ ICIP
ldr \irqnr, [\base, #4] @ ICMR
#endif
b 1002f
1004:
mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2
mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2
ands \irqstat, \irqstat, \irqnr
beq 1003f
rsb \irqstat, \irqnr, #0
and \irqstat, \irqstat, \irqnr
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #31
add \irqnr, \irqnr, #32
b 1001f
1003:
mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
1002:
ands \irqnr, \irqstat, \irqnr
beq 1001f
rsb \irqstat, \irqnr, #0
and \irqstat, \irqstat, \irqnr
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP)
rsb \irqnr, \irqnr, #31
1001:
.endm
include/asm-arm/arch-pxa/hardware.h
+36
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@@ -62,6 +62,42 @@
#ifndef __ASSEMBLY__
#define __cpu_is_pxa21x(id) \
({ \
unsigned int _id = (id) >> 4 & 0xf3f; \
_id == 0x212; \
})
#define __cpu_is_pxa25x(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
_id == 0x2d0 || _id == 0x290; \
})
#define __cpu_is_pxa27x(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
_id == 0x411; \
})
#define cpu_is_pxa21x() \
({ \
unsigned int id = read_cpuid(CPUID_ID); \
__cpu_is_pxa21x(id); \
})
#define cpu_is_pxa25x() \
({ \
unsigned int id = read_cpuid(CPUID_ID); \
__cpu_is_pxa25x(id); \
})
#define cpu_is_pxa27x() \
({ \
unsigned int id = read_cpuid(CPUID_ID); \
__cpu_is_pxa27x(id); \
})
/*
* Handy routine to set GPIO alternate functions
*/
include/asm-arm/arch-pxa/irqs.h
+10 -16
View File
@@ -11,14 +11,9 @@
*/
#define PXA_IRQ(x) (x)
#ifdef CONFIG_PXA27x
#define PXA_IRQ_SKIP 0
#else
#define PXA_IRQ_SKIP 7
#endif
#define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP)
#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */
@@ -26,6 +21,8 @@
#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */
#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
#endif
#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
@@ -58,18 +55,15 @@
#ifdef CONFIG_PXA27x
#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
#define PXA_INTERNAL_IRQS 34
#else
#define PXA_INTERNAL_IRQS 32
#endif
#define GPIO_2_x_TO_IRQ(x) \
PXA_IRQ((x) - 2 + PXA_INTERNAL_IRQS)
#define PXA_GPIO_IRQ_BASE (64)
#define PXA_GPIO_IRQ_NUM (128)
#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
#define IRQ_TO_GPIO_2_x(i) \
((i) - IRQ_GPIO(2) + 2)
#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE)
#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
#if defined(CONFIG_PXA25x)
@@ -84,7 +78,7 @@
* these. If you need more, increase IRQ_BOARD_END, but keep it
* within sensible limits.
*/
#define IRQ_BOARD_START (IRQ_GPIO(PXA_LAST_GPIO) + 1)
#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
#define IRQ_SA1111_START (IRQ_BOARD_END)
include/asm-arm/arch-pxa/pm.h
-1
View File
@@ -9,4 +9,3 @@
extern int pxa_pm_prepare(suspend_state_t state);
extern int pxa_pm_enter(suspend_state_t state);
extern int pxa_pm_finish(suspend_state_t state);
include/asm-arm/arch-pxa/pxa-regs.h
+1 -21
View File
@@ -1765,29 +1765,9 @@
#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
/*
* MultiMediaCard (MMC) controller
* MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
*/
#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
#define MMC_RESTO __REG(0x41100014) /* Expected response time out */
#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
#define MMC_CMD __REG(0x41100030) /* Index of current command */
#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
/*
* Core Clock
*/
include/asm-arm/elf.h
+1 -22
View File
@@ -7,6 +7,7 @@
*/
#include <asm/ptrace.h>
#include <asm/user.h>
#include <asm/hwcap.h>
typedef unsigned long elf_greg_t;
typedef unsigned long elf_freg_t[3];
@@ -39,30 +40,8 @@ typedef struct user_fp elf_fpregset_t;
#endif
#define ELF_ARCH EM_ARM
/*
* HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
*/
#define HWCAP_SWP 1
#define HWCAP_HALF 2
#define HWCAP_THUMB 4
#define HWCAP_26BIT 8 /* Play it safe */
#define HWCAP_FAST_MULT 16
#define HWCAP_FPA 32
#define HWCAP_VFP 64
#define HWCAP_EDSP 128
#define HWCAP_JAVA 256
#define HWCAP_IWMMXT 512
#define HWCAP_CRUNCH 1024
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
/*
* This yields a mask that user programs can use to figure out what
* instruction set this cpu supports.
*/
#define ELF_HWCAP (elf_hwcap)
extern unsigned int elf_hwcap;
/*
* This yields a string that ld.so will use to load implementation
* specific libraries for optimization. This is more specific in
include/asm-arm/hwcap.h
+28
View File
@@ -0,0 +1,28 @@
#ifndef __ASMARM_HWCAP_H
#define __ASMARM_HWCAP_H
/*
* HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
*/
#define HWCAP_SWP 1
#define HWCAP_HALF 2
#define HWCAP_THUMB 4
#define HWCAP_26BIT 8 /* Play it safe */
#define HWCAP_FAST_MULT 16
#define HWCAP_FPA 32
#define HWCAP_VFP 64
#define HWCAP_EDSP 128
#define HWCAP_JAVA 256
#define HWCAP_IWMMXT 512
#define HWCAP_CRUNCH 1024
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
/*
* This yields a mask that user programs can use to figure out what
* instruction set this cpu supports.
*/
#define ELF_HWCAP (elf_hwcap)
extern unsigned int elf_hwcap;
#endif
#endif
include/asm-arm/ptrace.h
+13 -3
View File
@@ -10,6 +10,8 @@
#ifndef __ASM_ARM_PTRACE_H
#define __ASM_ARM_PTRACE_H
#include <asm/hwcap.h>
#define PTRACE_GETREGS 12
#define PTRACE_SETREGS 13
#define PTRACE_GETFPREGS 14
@@ -45,6 +47,7 @@
#define PSR_T_BIT 0x00000020
#define PSR_F_BIT 0x00000040
#define PSR_I_BIT 0x00000080
#define PSR_A_BIT 0x00000100
#define PSR_J_BIT 0x01000000
#define PSR_Q_BIT 0x08000000
#define PSR_V_BIT 0x10000000
@@ -103,6 +106,10 @@ struct pt_regs {
#define thumb_mode(regs) (0)
#endif
#define isa_mode(regs) \
((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
(((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
#define processor_mode(regs) \
((regs)->ARM_cpsr & MODE_MASK)
@@ -117,14 +124,17 @@ struct pt_regs {
*/
static inline int valid_user_regs(struct pt_regs *regs)
{
if (user_mode(regs) &&
(regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0)
if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
return 1;
}
/*
* Force CPSR to something logical...
*/
regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT;
if (!(elf_hwcap & HWCAP_26BIT))
regs->ARM_cpsr |= USR_MODE;
return 0;
}