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Merge branch 'sh/clkfwk'
This commit is contained in:
Paul Mundt
@@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
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# Common interfaces.
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obj-$(CONFIG_SH_ADC) += adc.o
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obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o
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obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
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obj-$(CONFIG_SH_FPU) += fpu.o
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obj-$(CONFIG_SH_FPU_EMU) += fpu.o
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+13
-294
@@ -2,317 +2,25 @@
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#include <linux/compiler.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <asm/clkdev.h>
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#include <asm/clock.h>
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static int sh_clk_mstp32_enable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
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clk->enable_reg);
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return 0;
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}
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static void sh_clk_mstp32_disable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
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clk->enable_reg);
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}
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static struct clk_ops sh_clk_mstp32_clk_ops = {
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.enable = sh_clk_mstp32_enable,
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.disable = sh_clk_mstp32_disable,
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.recalc = followparent_recalc,
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};
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int __init sh_clk_mstp32_register(struct clk *clks, int nr)
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{
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struct clk *clkp;
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int ret = 0;
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int k;
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = &sh_clk_mstp32_clk_ops;
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ret |= clk_register(clkp);
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}
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return ret;
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}
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static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_table_round(clk, clk->freq_table, rate);
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}
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static int sh_clk_div6_divisors[64] = {
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
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33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
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};
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static struct clk_div_mult_table sh_clk_div6_table = {
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.divisors = sh_clk_div6_divisors,
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.nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
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};
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static unsigned long sh_clk_div6_recalc(struct clk *clk)
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{
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struct clk_div_mult_table *table = &sh_clk_div6_table;
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unsigned int idx;
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, NULL);
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idx = __raw_readl(clk->enable_reg) & 0x003f;
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return clk->freq_table[idx].frequency;
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}
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static int sh_clk_div6_set_rate(struct clk *clk,
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unsigned long rate, int algo_id)
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{
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unsigned long value;
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int idx;
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idx = clk_rate_table_find(clk, clk->freq_table, rate);
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if (idx < 0)
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return idx;
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value = __raw_readl(clk->enable_reg);
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value &= ~0x3f;
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value |= idx;
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__raw_writel(value, clk->enable_reg);
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return 0;
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}
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static int sh_clk_div6_enable(struct clk *clk)
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{
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unsigned long value;
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int ret;
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ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
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if (ret == 0) {
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value = __raw_readl(clk->enable_reg);
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value &= ~0x100; /* clear stop bit to enable clock */
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__raw_writel(value, clk->enable_reg);
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}
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return ret;
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}
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static void sh_clk_div6_disable(struct clk *clk)
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{
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unsigned long value;
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value = __raw_readl(clk->enable_reg);
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value |= 0x100; /* stop clock */
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value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
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__raw_writel(value, clk->enable_reg);
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}
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static struct clk_ops sh_clk_div6_clk_ops = {
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.recalc = sh_clk_div6_recalc,
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.round_rate = sh_clk_div_round_rate,
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.set_rate = sh_clk_div6_set_rate,
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.enable = sh_clk_div6_enable,
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.disable = sh_clk_div6_disable,
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};
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int __init sh_clk_div6_register(struct clk *clks, int nr)
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{
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struct clk *clkp;
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void *freq_table;
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int nr_divs = sh_clk_div6_table.nr_divisors;
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int freq_table_size = sizeof(struct cpufreq_frequency_table);
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int ret = 0;
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int k;
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freq_table_size *= (nr_divs + 1);
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freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
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if (!freq_table) {
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pr_err("sh_clk_div6_register: unable to alloc memory\n");
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return -ENOMEM;
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}
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = &sh_clk_div6_clk_ops;
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clkp->id = -1;
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clkp->freq_table = freq_table + (k * freq_table_size);
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clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
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ret = clk_register(clkp);
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}
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return ret;
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}
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static unsigned long sh_clk_div4_recalc(struct clk *clk)
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{
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struct clk_div4_table *d4t = clk->priv;
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struct clk_div_mult_table *table = d4t->div_mult_table;
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unsigned int idx;
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, &clk->arch_flags);
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idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
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return clk->freq_table[idx].frequency;
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}
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static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_div4_table *d4t = clk->priv;
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struct clk_div_mult_table *table = d4t->div_mult_table;
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u32 value;
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int ret;
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if (!strcmp("pll_clk", parent->name))
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value = __raw_readl(clk->enable_reg) & ~(1 << 7);
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else
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value = __raw_readl(clk->enable_reg) | (1 << 7);
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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__raw_writel(value, clk->enable_reg);
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/* Rebiuld the frequency table */
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, &clk->arch_flags);
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return 0;
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}
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static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
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{
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struct clk_div4_table *d4t = clk->priv;
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unsigned long value;
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int idx = clk_rate_table_find(clk, clk->freq_table, rate);
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if (idx < 0)
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return idx;
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value = __raw_readl(clk->enable_reg);
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value &= ~(0xf << clk->enable_bit);
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value |= (idx << clk->enable_bit);
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__raw_writel(value, clk->enable_reg);
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if (d4t->kick)
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d4t->kick(clk);
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return 0;
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}
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static int sh_clk_div4_enable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
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return 0;
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}
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static void sh_clk_div4_disable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
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}
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static struct clk_ops sh_clk_div4_clk_ops = {
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.recalc = sh_clk_div4_recalc,
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.set_rate = sh_clk_div4_set_rate,
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.round_rate = sh_clk_div_round_rate,
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};
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static struct clk_ops sh_clk_div4_enable_clk_ops = {
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.recalc = sh_clk_div4_recalc,
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.set_rate = sh_clk_div4_set_rate,
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.round_rate = sh_clk_div_round_rate,
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.enable = sh_clk_div4_enable,
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.disable = sh_clk_div4_disable,
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};
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static struct clk_ops sh_clk_div4_reparent_clk_ops = {
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.recalc = sh_clk_div4_recalc,
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.set_rate = sh_clk_div4_set_rate,
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.round_rate = sh_clk_div_round_rate,
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.enable = sh_clk_div4_enable,
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.disable = sh_clk_div4_disable,
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.set_parent = sh_clk_div4_set_parent,
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};
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static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
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struct clk_div4_table *table, struct clk_ops *ops)
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{
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struct clk *clkp;
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void *freq_table;
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int nr_divs = table->div_mult_table->nr_divisors;
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int freq_table_size = sizeof(struct cpufreq_frequency_table);
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int ret = 0;
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int k;
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freq_table_size *= (nr_divs + 1);
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freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
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if (!freq_table) {
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pr_err("sh_clk_div4_register: unable to alloc memory\n");
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return -ENOMEM;
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}
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = ops;
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clkp->id = -1;
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clkp->priv = table;
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clkp->freq_table = freq_table + (k * freq_table_size);
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clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
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ret = clk_register(clkp);
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}
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return ret;
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}
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int __init sh_clk_div4_register(struct clk *clks, int nr,
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struct clk_div4_table *table)
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{
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return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
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}
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int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
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struct clk_div4_table *table)
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{
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return sh_clk_div4_register_ops(clks, nr, table,
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&sh_clk_div4_enable_clk_ops);
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}
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int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
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struct clk_div4_table *table)
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{
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return sh_clk_div4_register_ops(clks, nr, table,
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&sh_clk_div4_reparent_clk_ops);
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}
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#ifdef CONFIG_SH_CLK_CPG_LEGACY
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static struct clk master_clk = {
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.name = "master_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.rate = CONFIG_SH_PCLK_FREQ,
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};
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static struct clk peripheral_clk = {
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.name = "peripheral_clk",
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk bus_clk = {
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.name = "bus_clk",
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk cpu_clk = {
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.name = "cpu_clk",
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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@@ -327,6 +35,16 @@ static struct clk *onchip_clocks[] = {
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&cpu_clk,
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};
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#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("master_clk", &master_clk),
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CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
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CLKDEV_CON_ID("bus_clk", &bus_clk),
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CLKDEV_CON_ID("cpu_clk", &cpu_clk),
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};
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int __init __deprecated cpg_clk_init(void)
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{
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int i, ret = 0;
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@@ -338,6 +56,8 @@ int __init __deprecated cpg_clk_init(void)
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ret |= clk_register(clk);
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}
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
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clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
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clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
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@@ -354,4 +74,3 @@ int __init __weak arch_clk_init(void)
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{
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return cpg_clk_init();
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}
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#endif /* CONFIG_SH_CPG_CLK_LEGACY */
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+8
-568
File diff suppressed because it is too large
Load Diff
@@ -12,9 +12,10 @@
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <asm/clkdev.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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#define CPG2_FRQCR3 0xfe0a0018
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@@ -45,7 +46,6 @@ static struct clk_ops sh4202_emi_clk_ops = {
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};
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static struct clk sh4202_emi_clk = {
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.name = "emi_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh4202_emi_clk_ops,
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};
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@@ -61,7 +61,6 @@ static struct clk_ops sh4202_femi_clk_ops = {
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};
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static struct clk sh4202_femi_clk = {
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.name = "femi_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh4202_femi_clk_ops,
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};
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@@ -139,7 +138,6 @@ static struct clk_ops sh4202_shoc_clk_ops = {
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};
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static struct clk sh4202_shoc_clk = {
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.name = "shoc_clk",
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.flags = CLK_ENABLE_ON_INIT,
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||||
.ops = &sh4202_shoc_clk_ops,
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};
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@@ -150,6 +148,15 @@ static struct clk *sh4202_onchip_clocks[] = {
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&sh4202_shoc_clk,
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};
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||||
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#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
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static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk),
|
||||
CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk),
|
||||
CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk),
|
||||
};
|
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|
||||
int __init arch_clk_init(void)
|
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{
|
||||
struct clk *clk;
|
||||
@@ -167,5 +174,7 @@ int __init arch_clk_init(void)
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|
||||
clk_put(clk);
|
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
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|
||||
return ret;
|
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}
|
||||
|
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@@ -37,8 +37,6 @@
|
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|
||||
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
|
||||
static struct clk r_clk = {
|
||||
.name = "rclk",
|
||||
.id = -1,
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
@@ -47,8 +45,6 @@ static struct clk r_clk = {
|
||||
* from the platform code.
|
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*/
|
||||
struct clk extal_clk = {
|
||||
.name = "extal",
|
||||
.id = -1,
|
||||
.rate = 33333333,
|
||||
};
|
||||
|
||||
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk dll_clk = {
|
||||
.name = "dll_clk",
|
||||
.id = -1,
|
||||
.ops = &dll_clk_ops,
|
||||
.parent = &r_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
@@ -92,8 +86,6 @@ static struct clk_ops pll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.name = "pll_clk",
|
||||
.id = -1,
|
||||
.ops = &pll_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
@@ -122,18 +114,18 @@ static struct clk_div4_table div4_table = {
|
||||
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
|
||||
DIV4_SIUA, DIV4_SIUB, DIV4_NR };
|
||||
|
||||
#define DIV4(_str, _reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
|
||||
[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
|
||||
};
|
||||
|
||||
enum { DIV6_V, DIV6_NR };
|
||||
@@ -142,61 +134,148 @@ struct clk div6_clks[DIV6_NR] = {
|
||||
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
|
||||
};
|
||||
|
||||
#define MSTP(_str, _parent, _reg, _bit, _flags) \
|
||||
SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
|
||||
#define MSTP(_parent, _reg, _bit, _flags) \
|
||||
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
|
||||
|
||||
static struct clk mstp_clks[] = {
|
||||
MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
|
||||
MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
|
||||
MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
|
||||
MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
|
||||
MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
|
||||
MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
|
||||
MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
|
||||
MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
||||
MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||
MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
|
||||
MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||
MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
|
||||
MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
|
||||
MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
|
||||
MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
|
||||
MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
|
||||
MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
|
||||
MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
||||
MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
|
||||
enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
|
||||
MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
|
||||
MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
|
||||
MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
|
||||
MSTP109, MSTP108, MSTP100,
|
||||
MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
|
||||
MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
|
||||
MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
MSTP_NR };
|
||||
|
||||
MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
|
||||
MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0),
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
|
||||
[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
|
||||
[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
|
||||
[MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
|
||||
[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
|
||||
[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
|
||||
[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
|
||||
[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
||||
[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||
[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
|
||||
[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||
[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
|
||||
[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
|
||||
[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
|
||||
[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
|
||||
[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
|
||||
[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
|
||||
[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
|
||||
[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
|
||||
[MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
|
||||
[MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
|
||||
[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
||||
[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
|
||||
|
||||
MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0),
|
||||
MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
|
||||
MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
|
||||
MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
|
||||
MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0),
|
||||
MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
|
||||
MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0),
|
||||
MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0),
|
||||
MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
|
||||
MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
|
||||
MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
|
||||
MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
|
||||
MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
|
||||
MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
|
||||
MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
|
||||
MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
|
||||
MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
|
||||
[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
|
||||
[MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
|
||||
|
||||
[MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
|
||||
[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
|
||||
[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
|
||||
[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
|
||||
[MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
|
||||
[MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
|
||||
[MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
|
||||
[MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
|
||||
[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
|
||||
[MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
|
||||
[MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
|
||||
[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
|
||||
[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
|
||||
[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
|
||||
[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
|
||||
[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
|
||||
[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
|
||||
};
|
||||
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("rclk", &r_clk),
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("dll_clk", &dll_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
|
||||
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
|
||||
CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
|
||||
CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
|
||||
CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
|
||||
CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
|
||||
CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
|
||||
CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
|
||||
CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
|
||||
CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
|
||||
CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
|
||||
CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
|
||||
CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
|
||||
CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
|
||||
CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
|
||||
CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
|
||||
CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
|
||||
CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
|
||||
CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
|
||||
{
|
||||
/* SCIF0 */
|
||||
.dev_id = "sh-sci.0",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP007],
|
||||
}, {
|
||||
/* SCIF1 */
|
||||
.dev_id = "sh-sci.1",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP006],
|
||||
}, {
|
||||
/* SCIF2 */
|
||||
.dev_id = "sh-sci.2",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP005],
|
||||
}, {
|
||||
/* SCIF3 */
|
||||
.dev_id = "sh-sci.3",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP004],
|
||||
},
|
||||
CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
|
||||
CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
|
||||
CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
|
||||
CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
|
||||
CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]),
|
||||
CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
|
||||
CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
|
||||
CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
|
||||
CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
|
||||
CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
|
||||
CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
|
||||
CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
|
||||
CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
|
||||
CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
|
||||
CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
|
||||
CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
|
||||
CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
|
||||
CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
|
||||
CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
|
||||
CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
|
||||
CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
|
||||
CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
|
||||
};
|
||||
|
||||
int __init arch_clk_init(void)
|
||||
@@ -221,7 +300,7 @@ int __init arch_clk_init(void)
|
||||
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
|
||||
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -37,8 +37,6 @@
|
||||
|
||||
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
|
||||
static struct clk r_clk = {
|
||||
.name = "rclk",
|
||||
.id = -1,
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
@@ -47,8 +45,6 @@ static struct clk r_clk = {
|
||||
* from the platform code.
|
||||
*/
|
||||
struct clk extal_clk = {
|
||||
.name = "extal",
|
||||
.id = -1,
|
||||
.rate = 33333333,
|
||||
};
|
||||
|
||||
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk dll_clk = {
|
||||
.name = "dll_clk",
|
||||
.id = -1,
|
||||
.ops = &dll_clk_ops,
|
||||
.parent = &r_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.name = "pll_clk",
|
||||
.id = -1,
|
||||
.ops = &pll_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
@@ -125,18 +117,18 @@ static struct clk_div4_table div4_table = {
|
||||
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
|
||||
DIV4_SIUA, DIV4_SIUB, DIV4_NR };
|
||||
|
||||
#define DIV4(_str, _reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
|
||||
[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
|
||||
};
|
||||
|
||||
enum { DIV6_V, DIV6_NR };
|
||||
@@ -145,58 +137,134 @@ struct clk div6_clks[DIV6_NR] = {
|
||||
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
|
||||
};
|
||||
|
||||
#define MSTP(_str, _parent, _reg, _bit, _flags) \
|
||||
SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
|
||||
#define MSTP(_parent, _reg, _bit, _flags) \
|
||||
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
|
||||
|
||||
static struct clk mstp_clks[] = {
|
||||
enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
|
||||
MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
|
||||
MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
|
||||
MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
|
||||
MSTP109, MSTP100,
|
||||
MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
|
||||
MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
|
||||
MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
|
||||
MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
|
||||
MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
|
||||
MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
|
||||
MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
|
||||
MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
|
||||
MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
|
||||
MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
||||
MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||
MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
|
||||
MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||
MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
|
||||
MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
|
||||
MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
|
||||
MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
|
||||
MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
|
||||
MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
||||
MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
|
||||
[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
|
||||
[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
|
||||
[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
|
||||
[MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
|
||||
[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
|
||||
[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
|
||||
[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
|
||||
[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
||||
[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||
[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
|
||||
[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||
[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
|
||||
[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
|
||||
[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
|
||||
[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
|
||||
[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
|
||||
[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
|
||||
[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
|
||||
[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
|
||||
[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
||||
[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
|
||||
|
||||
MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
|
||||
[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
|
||||
|
||||
MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0),
|
||||
MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0),
|
||||
MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
|
||||
MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0),
|
||||
MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0),
|
||||
MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
|
||||
MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
|
||||
MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
|
||||
MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
|
||||
MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
|
||||
MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
|
||||
MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
|
||||
MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
|
||||
MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
|
||||
MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
|
||||
MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
|
||||
[MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
|
||||
[MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
|
||||
[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
|
||||
[MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
|
||||
[MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
|
||||
[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
|
||||
[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
|
||||
[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
|
||||
[MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
|
||||
[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
|
||||
[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
|
||||
[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
|
||||
[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
|
||||
[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
|
||||
[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
|
||||
};
|
||||
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("rclk", &r_clk),
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("dll_clk", &dll_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
|
||||
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
|
||||
CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
|
||||
CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
|
||||
CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
|
||||
CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
|
||||
CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
|
||||
CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
|
||||
CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
|
||||
CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
|
||||
CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
|
||||
CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
|
||||
CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
|
||||
CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
|
||||
CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
|
||||
CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
|
||||
CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
|
||||
CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
|
||||
CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
|
||||
{
|
||||
/* SCIF0 */
|
||||
.dev_id = "sh-sci.0",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP007],
|
||||
}, {
|
||||
/* SCIF1 */
|
||||
.dev_id = "sh-sci.1",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP006],
|
||||
}, {
|
||||
/* SCIF2 */
|
||||
.dev_id = "sh-sci.2",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP005],
|
||||
},
|
||||
CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
|
||||
CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
|
||||
CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
|
||||
CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
|
||||
CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
|
||||
CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
|
||||
CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
|
||||
CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
|
||||
CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
|
||||
CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
|
||||
CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
|
||||
CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
|
||||
CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
|
||||
CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
|
||||
CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
|
||||
CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
|
||||
CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
|
||||
CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
|
||||
};
|
||||
|
||||
int __init arch_clk_init(void)
|
||||
@@ -221,7 +289,7 @@ int __init arch_clk_init(void)
|
||||
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
|
||||
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -37,8 +37,6 @@
|
||||
|
||||
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
|
||||
static struct clk r_clk = {
|
||||
.name = "rclk",
|
||||
.id = -1,
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
@@ -47,8 +45,6 @@ static struct clk r_clk = {
|
||||
* from the platform code.
|
||||
*/
|
||||
struct clk extal_clk = {
|
||||
.name = "extal",
|
||||
.id = -1,
|
||||
.rate = 33333333,
|
||||
};
|
||||
|
||||
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk dll_clk = {
|
||||
.name = "dll_clk",
|
||||
.id = -1,
|
||||
.ops = &dll_clk_ops,
|
||||
.parent = &r_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.name = "pll_clk",
|
||||
.id = -1,
|
||||
.ops = &pll_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
@@ -122,31 +114,31 @@ static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
};
|
||||
|
||||
#define DIV4(_str, _reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
|
||||
[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
|
||||
};
|
||||
|
||||
enum { DIV4_IRDA, DIV4_ENABLE_NR };
|
||||
|
||||
struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
|
||||
[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
|
||||
[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
|
||||
};
|
||||
|
||||
enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
|
||||
|
||||
struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
|
||||
[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
|
||||
[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
|
||||
};
|
||||
|
||||
enum { DIV6_V, DIV6_NR };
|
||||
@@ -186,6 +178,23 @@ static struct clk mstp_clks[HWBLK_NR] = {
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("rclk", &r_clk),
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("dll_clk", &dll_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
|
||||
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
|
||||
CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
|
||||
CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
|
||||
CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
|
||||
|
||||
|
||||
@@ -38,8 +38,6 @@
|
||||
|
||||
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
|
||||
static struct clk r_clk = {
|
||||
.name = "rclk",
|
||||
.id = -1,
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
@@ -48,8 +46,6 @@ static struct clk r_clk = {
|
||||
* from the platform code.
|
||||
*/
|
||||
struct clk extal_clk = {
|
||||
.name = "extal",
|
||||
.id = -1,
|
||||
.rate = 33333333,
|
||||
};
|
||||
|
||||
@@ -71,8 +67,6 @@ static struct clk_ops dll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk dll_clk = {
|
||||
.name = "dll_clk",
|
||||
.id = -1,
|
||||
.ops = &dll_clk_ops,
|
||||
.parent = &r_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
@@ -96,8 +90,6 @@ static struct clk_ops pll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.name = "pll_clk",
|
||||
.id = -1,
|
||||
.ops = &pll_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
@@ -125,29 +117,29 @@ static struct clk_div4_table div4_table = {
|
||||
|
||||
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
|
||||
|
||||
#define DIV4(_str, _reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
|
||||
[DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
|
||||
};
|
||||
|
||||
enum { DIV4_IRDA, DIV4_ENABLE_NR };
|
||||
|
||||
struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
|
||||
[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
|
||||
[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
|
||||
};
|
||||
|
||||
enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
|
||||
|
||||
struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
|
||||
[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
|
||||
[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
|
||||
[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
|
||||
[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
|
||||
};
|
||||
enum { DIV6_V, DIV6_NR };
|
||||
|
||||
@@ -211,6 +203,23 @@ static struct clk mstp_clks[] = {
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("rclk", &r_clk),
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("dll_clk", &dll_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
|
||||
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
|
||||
CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
|
||||
CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
|
||||
CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
|
||||
|
||||
|
||||
@@ -41,8 +41,6 @@
|
||||
|
||||
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
|
||||
static struct clk r_clk = {
|
||||
.name = "rclk",
|
||||
.id = -1,
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
@@ -51,8 +49,6 @@ static struct clk r_clk = {
|
||||
* from the platform code.
|
||||
*/
|
||||
struct clk extal_clk = {
|
||||
.name = "extal",
|
||||
.id = -1,
|
||||
.rate = 33333333,
|
||||
};
|
||||
|
||||
@@ -76,8 +72,6 @@ static struct clk_ops fll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk fll_clk = {
|
||||
.name = "fll_clk",
|
||||
.id = -1,
|
||||
.ops = &fll_clk_ops,
|
||||
.parent = &r_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
@@ -98,8 +92,6 @@ static struct clk_ops pll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.name = "pll_clk",
|
||||
.id = -1,
|
||||
.ops = &pll_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
@@ -115,8 +107,6 @@ static struct clk_ops div3_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk div3_clk = {
|
||||
.name = "div3_clk",
|
||||
.id = -1,
|
||||
.ops = &div3_clk_ops,
|
||||
.parent = &pll_clk,
|
||||
};
|
||||
@@ -153,15 +143,15 @@ static struct clk_div4_table div4_table = {
|
||||
|
||||
enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
|
||||
|
||||
#define DIV4(_str, _reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
|
||||
[DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
|
||||
[DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
|
||||
@@ -234,6 +224,20 @@ static struct clk mstp_clks[HWBLK_NR] = {
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("rclk", &r_clk),
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("fll_clk", &fll_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
CLKDEV_CON_ID("div3_clk", &div3_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
|
||||
CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
|
||||
|
||||
@@ -12,6 +12,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/clkdev.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/freq.h>
|
||||
|
||||
@@ -87,7 +88,6 @@ static struct clk_ops sh7757_shyway_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk sh7757_shyway_clk = {
|
||||
.name = "shyway_clk",
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.ops = &sh7757_shyway_clk_ops,
|
||||
};
|
||||
@@ -100,6 +100,13 @@ static struct clk *sh7757_onchip_clocks[] = {
|
||||
&sh7757_shyway_clk,
|
||||
};
|
||||
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk),
|
||||
};
|
||||
|
||||
static int __init sh7757_clk_init(void)
|
||||
{
|
||||
struct clk *clk = clk_get(NULL, "master_clk");
|
||||
@@ -123,6 +130,8 @@ static int __init sh7757_clk_init(void)
|
||||
|
||||
clk_put(clk);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -12,6 +12,8 @@
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/clkdev.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/freq.h>
|
||||
#include <asm/io.h>
|
||||
@@ -77,7 +79,6 @@ static struct clk_ops sh7763_shyway_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk sh7763_shyway_clk = {
|
||||
.name = "shyway_clk",
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.ops = &sh7763_shyway_clk_ops,
|
||||
};
|
||||
@@ -90,6 +91,13 @@ static struct clk *sh7763_onchip_clocks[] = {
|
||||
&sh7763_shyway_clk,
|
||||
};
|
||||
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
|
||||
};
|
||||
|
||||
int __init arch_clk_init(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
@@ -107,5 +115,7 @@ int __init arch_clk_init(void)
|
||||
|
||||
clk_put(clk);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -11,6 +11,8 @@
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/clkdev.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/freq.h>
|
||||
#include <asm/io.h>
|
||||
@@ -83,7 +85,6 @@ static struct clk_ops sh7780_shyway_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk sh7780_shyway_clk = {
|
||||
.name = "shyway_clk",
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.ops = &sh7780_shyway_clk_ops,
|
||||
};
|
||||
@@ -96,6 +97,13 @@ static struct clk *sh7780_onchip_clocks[] = {
|
||||
&sh7780_shyway_clk,
|
||||
};
|
||||
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk),
|
||||
};
|
||||
|
||||
int __init arch_clk_init(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
@@ -113,5 +121,7 @@ int __init arch_clk_init(void)
|
||||
|
||||
clk_put(clk);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -24,8 +24,6 @@
|
||||
* from the platform code.
|
||||
*/
|
||||
static struct clk extal_clk = {
|
||||
.name = "extal",
|
||||
.id = -1,
|
||||
.rate = 33333333,
|
||||
};
|
||||
|
||||
@@ -43,8 +41,6 @@ static struct clk_ops pll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.name = "pll_clk",
|
||||
.id = -1,
|
||||
.ops = &pll_clk_ops,
|
||||
.parent = &extal_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
@@ -70,82 +66,149 @@ static struct clk_div4_table div4_table = {
|
||||
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
|
||||
DIV4_DU, DIV4_P, DIV4_NR };
|
||||
|
||||
#define DIV4(_str, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
|
||||
#define DIV4(_bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0),
|
||||
[DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0),
|
||||
[DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0),
|
||||
[DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4(0, 0x0f80, 0),
|
||||
[DIV4_DU] = DIV4(4, 0x0ff0, 0),
|
||||
[DIV4_GA] = DIV4(8, 0x0030, 0),
|
||||
[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
#define MSTPCR0 0xffc80030
|
||||
#define MSTPCR1 0xffc80034
|
||||
|
||||
static struct clk mstp_clks[] = {
|
||||
enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
|
||||
MSTP021, MSTP020, MSTP017, MSTP016,
|
||||
MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002,
|
||||
MSTP119, MSTP117, MSTP105, MSTP104, MSTP100,
|
||||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
/* MSTPCR0 */
|
||||
SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
|
||||
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
||||
SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||
SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||
SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
|
||||
SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0),
|
||||
SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0),
|
||||
SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
|
||||
SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
|
||||
SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0),
|
||||
SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
||||
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
|
||||
[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
|
||||
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
|
||||
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
|
||||
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
|
||||
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
|
||||
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
||||
[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||
[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
|
||||
[MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
|
||||
[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
|
||||
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
|
||||
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
|
||||
[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
|
||||
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
||||
|
||||
/* MSTPCR1 */
|
||||
SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
|
||||
SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
|
||||
SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
|
||||
SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
|
||||
SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
|
||||
[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
|
||||
[MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
|
||||
[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
|
||||
[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
|
||||
[MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
|
||||
};
|
||||
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
|
||||
CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
|
||||
CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
|
||||
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
|
||||
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
{
|
||||
/* SCIF5 */
|
||||
.dev_id = "sh-sci.5",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP029],
|
||||
}, {
|
||||
/* SCIF4 */
|
||||
.dev_id = "sh-sci.4",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP028],
|
||||
}, {
|
||||
/* SCIF3 */
|
||||
.dev_id = "sh-sci.3",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP027],
|
||||
}, {
|
||||
/* SCIF2 */
|
||||
.dev_id = "sh-sci.2",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP026],
|
||||
}, {
|
||||
/* SCIF1 */
|
||||
.dev_id = "sh-sci.1",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP025],
|
||||
}, {
|
||||
/* SCIF0 */
|
||||
.dev_id = "sh-sci.0",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP024],
|
||||
},
|
||||
CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
|
||||
CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
|
||||
CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
|
||||
CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
|
||||
CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
|
||||
CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
|
||||
{
|
||||
/* TMU0 */
|
||||
.dev_id = "sh_tmu.0",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[13], /* tmu012_fck */
|
||||
.clk = &mstp_clks[MSTP008],
|
||||
}, {
|
||||
/* TMU1 */
|
||||
.dev_id = "sh_tmu.1",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[13],
|
||||
.clk = &mstp_clks[MSTP008],
|
||||
}, {
|
||||
/* TMU2 */
|
||||
.dev_id = "sh_tmu.2",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[13],
|
||||
.clk = &mstp_clks[MSTP008],
|
||||
}, {
|
||||
/* TMU3 */
|
||||
.dev_id = "sh_tmu.3",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[12], /* tmu345_fck */
|
||||
.clk = &mstp_clks[MSTP009],
|
||||
}, {
|
||||
/* TMU4 */
|
||||
.dev_id = "sh_tmu.4",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[12],
|
||||
.clk = &mstp_clks[MSTP009],
|
||||
}, {
|
||||
/* TMU5 */
|
||||
.dev_id = "sh_tmu.5",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[12],
|
||||
.clk = &mstp_clks[MSTP009],
|
||||
},
|
||||
CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
|
||||
CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
|
||||
CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
|
||||
CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
|
||||
CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
|
||||
CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
|
||||
CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),
|
||||
};
|
||||
|
||||
int __init arch_clk_init(void)
|
||||
@@ -161,7 +224,7 @@ int __init arch_clk_init(void)
|
||||
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
|
||||
&div4_table);
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
|
||||
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -23,8 +23,6 @@
|
||||
* from the platform code.
|
||||
*/
|
||||
static struct clk extal_clk = {
|
||||
.name = "extal",
|
||||
.id = -1,
|
||||
.rate = 33333333,
|
||||
};
|
||||
|
||||
@@ -46,8 +44,6 @@ static struct clk_ops pll_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.name = "pll_clk",
|
||||
.id = -1,
|
||||
.ops = &pll_clk_ops,
|
||||
.parent = &extal_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
@@ -72,118 +68,191 @@ static struct clk_div4_table div4_table = {
|
||||
|
||||
enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
|
||||
|
||||
#define DIV4(_str, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
|
||||
#define DIV4(_bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0),
|
||||
[DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0),
|
||||
[DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4(0, 0x0b40, 0),
|
||||
[DIV4_DU] = DIV4(4, 0x0010, 0),
|
||||
[DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
#define MSTPCR0 0xffc40030
|
||||
#define MSTPCR1 0xffc40034
|
||||
|
||||
static struct clk mstp_clks[] = {
|
||||
enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
|
||||
MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
|
||||
MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
|
||||
MSTP005, MSTP004, MSTP002,
|
||||
MSTP112, MSTP110, MSTP109, MSTP108,
|
||||
MSTP105, MSTP104, MSTP103, MSTP102,
|
||||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
/* MSTPCR0 */
|
||||
SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
|
||||
SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
|
||||
SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
|
||||
SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
|
||||
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
||||
SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||
SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||
SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
|
||||
SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
|
||||
SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
|
||||
SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
|
||||
SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
|
||||
SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
|
||||
SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
|
||||
SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
|
||||
SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
|
||||
SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
||||
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
|
||||
[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
|
||||
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
|
||||
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
|
||||
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
|
||||
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
|
||||
[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
|
||||
[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
|
||||
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
||||
[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||
[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
|
||||
[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
|
||||
[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
|
||||
[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
|
||||
[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
|
||||
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
|
||||
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
|
||||
[MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
|
||||
[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
|
||||
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
||||
|
||||
/* MSTPCR1 */
|
||||
SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
|
||||
SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
|
||||
SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
|
||||
SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
|
||||
SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
|
||||
SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
|
||||
SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
|
||||
SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
|
||||
[MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
|
||||
[MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
|
||||
[MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
|
||||
[MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
|
||||
[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
|
||||
[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
|
||||
[MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
|
||||
[MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
|
||||
};
|
||||
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
|
||||
CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
|
||||
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
{
|
||||
/* SCIF5 */
|
||||
.dev_id = "sh-sci.5",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP029],
|
||||
}, {
|
||||
/* SCIF4 */
|
||||
.dev_id = "sh-sci.4",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP028],
|
||||
}, {
|
||||
/* SCIF3 */
|
||||
.dev_id = "sh-sci.3",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP027],
|
||||
}, {
|
||||
/* SCIF2 */
|
||||
.dev_id = "sh-sci.2",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP026],
|
||||
}, {
|
||||
/* SCIF1 */
|
||||
.dev_id = "sh-sci.1",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP025],
|
||||
}, {
|
||||
/* SCIF0 */
|
||||
.dev_id = "sh-sci.0",
|
||||
.con_id = "sci_fck",
|
||||
.clk = &mstp_clks[MSTP024],
|
||||
},
|
||||
CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
|
||||
CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
|
||||
CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
|
||||
CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
|
||||
CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
|
||||
CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
|
||||
CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
|
||||
CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
|
||||
{
|
||||
/* TMU0 */
|
||||
.dev_id = "sh_tmu.0",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[17], /* tmu012_fck */
|
||||
.clk = &mstp_clks[MSTP008],
|
||||
}, {
|
||||
/* TMU1 */
|
||||
.dev_id = "sh_tmu.1",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[17],
|
||||
.clk = &mstp_clks[MSTP008],
|
||||
}, {
|
||||
/* TMU2 */
|
||||
.dev_id = "sh_tmu.2",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[17],
|
||||
.clk = &mstp_clks[MSTP008],
|
||||
}, {
|
||||
/* TMU3 */
|
||||
.dev_id = "sh_tmu.3",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[16], /* tmu345_fck */
|
||||
.clk = &mstp_clks[MSTP009],
|
||||
}, {
|
||||
/* TMU4 */
|
||||
.dev_id = "sh_tmu.4",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[16],
|
||||
.clk = &mstp_clks[MSTP009],
|
||||
}, {
|
||||
/* TMU5 */
|
||||
.dev_id = "sh_tmu.5",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[16],
|
||||
.clk = &mstp_clks[MSTP009],
|
||||
}, {
|
||||
/* TMU6 */
|
||||
.dev_id = "sh_tmu.6",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[15], /* tmu678_fck */
|
||||
.clk = &mstp_clks[MSTP010],
|
||||
}, {
|
||||
/* TMU7 */
|
||||
.dev_id = "sh_tmu.7",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[15],
|
||||
.clk = &mstp_clks[MSTP010],
|
||||
}, {
|
||||
/* TMU8 */
|
||||
.dev_id = "sh_tmu.8",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[15],
|
||||
.clk = &mstp_clks[MSTP010],
|
||||
}, {
|
||||
/* TMU9 */
|
||||
.dev_id = "sh_tmu.9",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[14], /* tmu9_11_fck */
|
||||
.clk = &mstp_clks[MSTP011],
|
||||
}, {
|
||||
/* TMU10 */
|
||||
.dev_id = "sh_tmu.10",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[14],
|
||||
.clk = &mstp_clks[MSTP011],
|
||||
}, {
|
||||
/* TMU11 */
|
||||
.dev_id = "sh_tmu.11",
|
||||
.con_id = "tmu_fck",
|
||||
.clk = &mstp_clks[14],
|
||||
}
|
||||
.clk = &mstp_clks[MSTP011],
|
||||
},
|
||||
CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
|
||||
CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
|
||||
CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
|
||||
CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
|
||||
CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
|
||||
CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
|
||||
CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
|
||||
CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
|
||||
CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
|
||||
CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
|
||||
CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
|
||||
};
|
||||
|
||||
int __init arch_clk_init(void)
|
||||
@@ -199,7 +268,7 @@ int __init arch_clk_init(void)
|
||||
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
|
||||
&div4_table);
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
|
||||
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -13,9 +13,10 @@
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/clkdev.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/freq.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
static int ifc_divisors[] = { 1, 2, 4 ,6 };
|
||||
static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
|
||||
@@ -94,7 +95,6 @@ static struct clk_ops shx3_shyway_clk_ops = {
|
||||
};
|
||||
|
||||
static struct clk shx3_shyway_clk = {
|
||||
.name = "shyway_clk",
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.ops = &shx3_shyway_clk_ops,
|
||||
};
|
||||
@@ -107,6 +107,13 @@ static struct clk *shx3_onchip_clocks[] = {
|
||||
&shx3_shyway_clk,
|
||||
};
|
||||
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk),
|
||||
};
|
||||
|
||||
int __init arch_clk_init(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
@@ -124,5 +131,7 @@ int __init arch_clk_init(void)
|
||||
|
||||
clk_put(clk);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user