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x86: create tlb files
this patch creates tlb_32.c and tlb_64.c, with tlb-related functions that used to live in smp*.c files. Signed-off-by: Glauber Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Glauber Costa
committed by
Ingo Molnar
Ingo Molnar
parent
8202350367
commit
c048fdfe61
@@ -0,0 +1,243 @@
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#include <linux/spinlock.h>
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <asm/tlbflush.h>
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DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate)
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____cacheline_aligned = { &init_mm, 0, };
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/* must come after the send_IPI functions above for inlining */
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#include <mach_ipi.h>
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/*
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* Smarter SMP flushing macros.
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* c/o Linus Torvalds.
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*
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* These mean you can really definitely utterly forget about
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* writing to user space from interrupts. (Its not allowed anyway).
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*
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* Optimizations Manfred Spraul <manfred@colorfullife.com>
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*/
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static cpumask_t flush_cpumask;
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static struct mm_struct *flush_mm;
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static unsigned long flush_va;
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static DEFINE_SPINLOCK(tlbstate_lock);
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/*
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* We cannot call mmdrop() because we are in interrupt context,
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* instead update mm->cpu_vm_mask.
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*
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* We need to reload %cr3 since the page tables may be going
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* away from under us..
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*/
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void leave_mm(int cpu)
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{
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if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
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BUG();
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cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
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load_cr3(swapper_pg_dir);
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}
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EXPORT_SYMBOL_GPL(leave_mm);
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/*
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*
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* The flush IPI assumes that a thread switch happens in this order:
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* [cpu0: the cpu that switches]
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* 1) switch_mm() either 1a) or 1b)
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* 1a) thread switch to a different mm
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* 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
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* Stop ipi delivery for the old mm. This is not synchronized with
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* the other cpus, but smp_invalidate_interrupt ignore flush ipis
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* for the wrong mm, and in the worst case we perform a superfluous
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* tlb flush.
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* 1a2) set cpu_tlbstate to TLBSTATE_OK
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* Now the smp_invalidate_interrupt won't call leave_mm if cpu0
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* was in lazy tlb mode.
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* 1a3) update cpu_tlbstate[].active_mm
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* Now cpu0 accepts tlb flushes for the new mm.
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* 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
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* Now the other cpus will send tlb flush ipis.
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* 1a4) change cr3.
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* 1b) thread switch without mm change
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* cpu_tlbstate[].active_mm is correct, cpu0 already handles
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* flush ipis.
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* 1b1) set cpu_tlbstate to TLBSTATE_OK
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* 1b2) test_and_set the cpu bit in cpu_vm_mask.
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* Atomically set the bit [other cpus will start sending flush ipis],
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* and test the bit.
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* 1b3) if the bit was 0: leave_mm was called, flush the tlb.
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* 2) switch %%esp, ie current
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*
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* The interrupt must handle 2 special cases:
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* - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
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* - the cpu performs speculative tlb reads, i.e. even if the cpu only
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* runs in kernel space, the cpu could load tlb entries for user space
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* pages.
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*
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* The good news is that cpu_tlbstate is local to each cpu, no
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* write/read ordering problems.
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*/
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/*
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* TLB flush IPI:
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*
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* 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
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* 2) Leave the mm if we are in the lazy tlb mode.
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*/
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void smp_invalidate_interrupt(struct pt_regs *regs)
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{
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unsigned long cpu;
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cpu = get_cpu();
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if (!cpu_isset(cpu, flush_cpumask))
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goto out;
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/*
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* This was a BUG() but until someone can quote me the
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* line from the intel manual that guarantees an IPI to
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* multiple CPUs is retried _only_ on the erroring CPUs
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* its staying as a return
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*
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* BUG();
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*/
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if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
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if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
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if (flush_va == TLB_FLUSH_ALL)
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local_flush_tlb();
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else
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__flush_tlb_one(flush_va);
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} else
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leave_mm(cpu);
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}
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ack_APIC_irq();
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smp_mb__before_clear_bit();
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cpu_clear(cpu, flush_cpumask);
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smp_mb__after_clear_bit();
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out:
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put_cpu_no_resched();
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__get_cpu_var(irq_stat).irq_tlb_count++;
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}
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void native_flush_tlb_others(const cpumask_t *cpumaskp, struct mm_struct *mm,
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unsigned long va)
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{
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cpumask_t cpumask = *cpumaskp;
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/*
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* A couple of (to be removed) sanity checks:
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*
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* - current CPU must not be in mask
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* - mask must exist :)
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*/
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BUG_ON(cpus_empty(cpumask));
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BUG_ON(cpu_isset(smp_processor_id(), cpumask));
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BUG_ON(!mm);
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#ifdef CONFIG_HOTPLUG_CPU
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/* If a CPU which we ran on has gone down, OK. */
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cpus_and(cpumask, cpumask, cpu_online_map);
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if (unlikely(cpus_empty(cpumask)))
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return;
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#endif
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/*
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* i'm not happy about this global shared spinlock in the
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* MM hot path, but we'll see how contended it is.
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* AK: x86-64 has a faster method that could be ported.
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*/
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spin_lock(&tlbstate_lock);
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flush_mm = mm;
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flush_va = va;
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cpus_or(flush_cpumask, cpumask, flush_cpumask);
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/*
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* We have to send the IPI only to
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* CPUs affected.
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*/
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send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
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while (!cpus_empty(flush_cpumask))
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/* nothing. lockup detection does not belong here */
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cpu_relax();
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flush_mm = NULL;
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flush_va = 0;
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spin_unlock(&tlbstate_lock);
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}
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void flush_tlb_current_task(void)
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{
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struct mm_struct *mm = current->mm;
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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local_flush_tlb();
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
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preempt_enable();
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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if (current->active_mm == mm) {
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if (current->mm)
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local_flush_tlb();
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else
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leave_mm(smp_processor_id());
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}
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
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preempt_enable();
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
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{
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struct mm_struct *mm = vma->vm_mm;
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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if (current->active_mm == mm) {
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if (current->mm)
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__flush_tlb_one(va);
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else
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leave_mm(smp_processor_id());
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}
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, va);
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preempt_enable();
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}
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EXPORT_SYMBOL(flush_tlb_page);
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static void do_flush_tlb_all(void *info)
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{
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unsigned long cpu = smp_processor_id();
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__flush_tlb_all();
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if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
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leave_mm(cpu);
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}
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void flush_tlb_all(void)
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{
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on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
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}
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