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Merge branch 'next-spi' of git://git.secretlab.ca/git/linux-2.6
* 'next-spi' of git://git.secretlab.ca/git/linux-2.6: spi: spi_txx9.c: use resource_size() spi: spi_sh_sci.c: use resource_size() spi: spi_mpc8xxx.c: use resource_size() spi: spi_bfin5xx.c: use resource_size() spi: atmel_spi.c: use resource_size() spi: Add s3c64xx SPI Controller driver atmel_spi: fix dma addr calculation for len > BUFFER_SIZE spi_s3c24xx: add FIQ pseudo-DMA support spi: controller driver for Designware SPI core spidev: add proper section markers spidev: use DECLARE_BITMAP instead of declaring the array
This commit is contained in:
Linus Torvalds
@@ -216,6 +216,17 @@ config SPI_S3C24XX
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help
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SPI driver for Samsung S3C24XX series ARM SoCs
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config SPI_S3C24XX_FIQ
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bool "S3C24XX driver with FIQ pseudo-DMA"
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depends on SPI_S3C24XX
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select FIQ
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help
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Enable FIQ support for the S3C24XX SPI driver to provide pseudo
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DMA by using the fast-interrupt request framework, This allows
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the driver to get DMA-like performance when there are either
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no free DMA channels, or when doing transfers that required both
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TX and RX data paths.
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config SPI_S3C24XX_GPIO
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tristate "Samsung S3C24XX series SPI by GPIO"
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depends on ARCH_S3C2410 && EXPERIMENTAL
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@@ -226,6 +237,13 @@ config SPI_S3C24XX_GPIO
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the inbuilt hardware cannot provide the transfer mode, or
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where the board is using non hardware connected pins.
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config SPI_S3C64XX
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tristate "Samsung S3C64XX series type SPI"
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depends on ARCH_S3C64XX && EXPERIMENTAL
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select S3C64XX_DMA
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help
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SPI driver for Samsung S3C64XX and newer SoCs.
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config SPI_SH_MSIOF
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tristate "SuperH MSIOF SPI controller"
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depends on SUPERH && HAVE_CLK
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@@ -289,6 +307,16 @@ config SPI_NUC900
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# Add new SPI master controllers in alphabetical order above this line
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#
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config SPI_DESIGNWARE
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bool "DesignWare SPI controller core support"
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depends on SPI_MASTER
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help
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general driver for SPI controller core from DesignWare
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config SPI_DW_PCI
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tristate "PCI interface driver for DW SPI core"
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depends on SPI_DESIGNWARE && PCI
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#
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# There are lots of SPI device types, with sensors and memory
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# being probably the most widely used ones.
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@@ -16,6 +16,8 @@ obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
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obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
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obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
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obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
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obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o
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obj-$(CONFIG_SPI_DW_PCI) += dw_spi_pci.o
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obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
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obj-$(CONFIG_SPI_IMX) += spi_imx.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
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@@ -30,7 +32,8 @@ obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
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obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o
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obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
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obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
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obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o
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obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx_hw.o
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obj-$(CONFIG_SPI_S3C64XX) += spi_s3c64xx.o
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obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
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obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
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obj-$(CONFIG_SPI_XILINX_OF) += xilinx_spi_of.o
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@@ -39,6 +42,11 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
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obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
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obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
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# special build for s3c24xx spi driver with fiq support
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spi_s3c24xx_hw-y := spi_s3c24xx.o
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spi_s3c24xx_hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi_s3c24xx_fiq.o
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# ... add above this line ...
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# SPI protocol drivers (device/link on bus)
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@@ -189,14 +189,14 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
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/* use scratch buffer only when rx or tx data is unspecified */
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if (xfer->rx_buf)
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*rx_dma = xfer->rx_dma + xfer->len - len;
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*rx_dma = xfer->rx_dma + xfer->len - *plen;
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else {
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*rx_dma = as->buffer_dma;
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if (len > BUFFER_SIZE)
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len = BUFFER_SIZE;
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}
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if (xfer->tx_buf)
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*tx_dma = xfer->tx_dma + xfer->len - len;
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*tx_dma = xfer->tx_dma + xfer->len - *plen;
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else {
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*tx_dma = as->buffer_dma;
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if (len > BUFFER_SIZE)
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@@ -788,7 +788,7 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
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spin_lock_init(&as->lock);
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INIT_LIST_HEAD(&as->queue);
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as->pdev = pdev;
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as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
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as->regs = ioremap(regs->start, resource_size(regs));
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if (!as->regs)
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goto out_free_buffer;
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as->irq = irq;
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,169 @@
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/*
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* mrst_spi_pci.c - PCI interface driver for DW SPI Core
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*
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* Copyright (c) 2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/spi/dw_spi.h>
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#include <linux/spi/spi.h>
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#define DRIVER_NAME "dw_spi_pci"
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struct dw_spi_pci {
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struct pci_dev *pdev;
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struct dw_spi dws;
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};
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static int __devinit spi_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct dw_spi_pci *dwpci;
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struct dw_spi *dws;
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int pci_bar = 0;
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int ret;
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printk(KERN_INFO "DW: found PCI SPI controller(ID: %04x:%04x)\n",
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pdev->vendor, pdev->device);
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ret = pci_enable_device(pdev);
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if (ret)
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return ret;
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dwpci = kzalloc(sizeof(struct dw_spi_pci), GFP_KERNEL);
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if (!dwpci) {
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ret = -ENOMEM;
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goto err_disable;
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}
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dwpci->pdev = pdev;
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dws = &dwpci->dws;
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/* Get basic io resource and map it */
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dws->paddr = pci_resource_start(pdev, pci_bar);
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dws->iolen = pci_resource_len(pdev, pci_bar);
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ret = pci_request_region(pdev, pci_bar, dev_name(&pdev->dev));
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if (ret)
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goto err_kfree;
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dws->regs = ioremap_nocache((unsigned long)dws->paddr,
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pci_resource_len(pdev, pci_bar));
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if (!dws->regs) {
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ret = -ENOMEM;
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goto err_release_reg;
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}
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dws->parent_dev = &pdev->dev;
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dws->bus_num = 0;
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dws->num_cs = 4;
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dws->max_freq = 25000000; /* for Moorestwon */
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dws->irq = pdev->irq;
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ret = dw_spi_add_host(dws);
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if (ret)
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goto err_unmap;
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/* PCI hook and SPI hook use the same drv data */
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pci_set_drvdata(pdev, dwpci);
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return 0;
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err_unmap:
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iounmap(dws->regs);
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err_release_reg:
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pci_release_region(pdev, pci_bar);
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err_kfree:
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kfree(dwpci);
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err_disable:
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pci_disable_device(pdev);
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return ret;
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}
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static void __devexit spi_pci_remove(struct pci_dev *pdev)
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{
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struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
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pci_set_drvdata(pdev, NULL);
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iounmap(dwpci->dws.regs);
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pci_release_region(pdev, 0);
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kfree(dwpci);
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pci_disable_device(pdev);
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}
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#ifdef CONFIG_PM
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static int spi_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
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int ret;
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ret = dw_spi_suspend_host(&dwpci->dws);
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if (ret)
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return ret;
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pci_save_state(pdev);
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pci_disable_device(pdev);
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pci_set_power_state(pdev, pci_choose_state(pdev, state));
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return ret;
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}
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static int spi_resume(struct pci_dev *pdev)
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{
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struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
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int ret;
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pci_set_power_state(pdev, PCI_D0);
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pci_restore_state(pdev);
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ret = pci_enable_device(pdev);
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if (ret)
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return ret;
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return dw_spi_resume_host(&dwpci->dws);
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}
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#else
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#define spi_suspend NULL
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#define spi_resume NULL
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#endif
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static const struct pci_device_id pci_ids[] __devinitdata = {
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/* Intel Moorestown platform SPI controller 0 */
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) },
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{},
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};
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static struct pci_driver dw_spi_driver = {
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.name = DRIVER_NAME,
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.id_table = pci_ids,
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.probe = spi_pci_probe,
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.remove = __devexit_p(spi_pci_remove),
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.suspend = spi_suspend,
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.resume = spi_resume,
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};
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static int __init mrst_spi_init(void)
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{
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return pci_register_driver(&dw_spi_driver);
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}
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static void __exit mrst_spi_exit(void)
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{
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pci_unregister_driver(&dw_spi_driver);
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}
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module_init(mrst_spi_init);
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module_exit(mrst_spi_exit);
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MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
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MODULE_DESCRIPTION("PCI interface driver for DW SPI Core");
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MODULE_LICENSE("GPL v2");
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@@ -1294,7 +1294,7 @@ static int __init bfin_spi_probe(struct platform_device *pdev)
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goto out_error_get_res;
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}
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drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
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drv_data->regs_base = ioremap(res->start, resource_size(res));
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if (drv_data->regs_base == NULL) {
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dev_err(dev, "Cannot map IO\n");
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status = -ENXIO;
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@@ -1013,7 +1013,7 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
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init_completion(&mpc8xxx_spi->done);
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mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
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mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
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if (mpc8xxx_spi->base == NULL) {
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ret = -ENOMEM;
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goto err_ioremap;
|
||||
|
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+231
-13
@@ -1,7 +1,7 @@
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/* linux/drivers/spi/spi_s3c24xx.c
|
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*
|
||||
* Copyright (c) 2006 Ben Dooks
|
||||
* Copyright (c) 2006 Simtec Electronics
|
||||
* Copyright 2006-2009 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
@@ -28,6 +28,11 @@
|
||||
#include <plat/regs-spi.h>
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#include <mach/spi.h>
|
||||
|
||||
#include <plat/fiq.h>
|
||||
#include <asm/fiq.h>
|
||||
|
||||
#include "spi_s3c24xx_fiq.h"
|
||||
|
||||
/**
|
||||
* s3c24xx_spi_devstate - per device data
|
||||
* @hz: Last frequency calculated for @sppre field.
|
||||
@@ -42,6 +47,13 @@ struct s3c24xx_spi_devstate {
|
||||
u8 sppre;
|
||||
};
|
||||
|
||||
enum spi_fiq_mode {
|
||||
FIQ_MODE_NONE = 0,
|
||||
FIQ_MODE_TX = 1,
|
||||
FIQ_MODE_RX = 2,
|
||||
FIQ_MODE_TXRX = 3,
|
||||
};
|
||||
|
||||
struct s3c24xx_spi {
|
||||
/* bitbang has to be first */
|
||||
struct spi_bitbang bitbang;
|
||||
@@ -52,6 +64,11 @@ struct s3c24xx_spi {
|
||||
int len;
|
||||
int count;
|
||||
|
||||
struct fiq_handler fiq_handler;
|
||||
enum spi_fiq_mode fiq_mode;
|
||||
unsigned char fiq_inuse;
|
||||
unsigned char fiq_claimed;
|
||||
|
||||
void (*set_cs)(struct s3c2410_spi_info *spi,
|
||||
int cs, int pol);
|
||||
|
||||
@@ -67,6 +84,7 @@ struct s3c24xx_spi {
|
||||
struct s3c2410_spi_info *pdata;
|
||||
};
|
||||
|
||||
|
||||
#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
|
||||
#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
|
||||
|
||||
@@ -127,7 +145,7 @@ static int s3c24xx_spi_update_state(struct spi_device *spi,
|
||||
}
|
||||
|
||||
if (spi->mode != cs->mode) {
|
||||
u8 spcon = SPCON_DEFAULT;
|
||||
u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
|
||||
|
||||
if (spi->mode & SPI_CPHA)
|
||||
spcon |= S3C2410_SPCON_CPHA_FMTB;
|
||||
@@ -214,13 +232,196 @@ static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
|
||||
return hw->tx ? hw->tx[count] : 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_S3C24XX_FIQ
|
||||
/* Support for FIQ based pseudo-DMA to improve the transfer speed.
|
||||
*
|
||||
* This code uses the assembly helper in spi_s3c24xx_spi.S which is
|
||||
* used by the FIQ core to move data between main memory and the peripheral
|
||||
* block. Since this is code running on the processor, there is no problem
|
||||
* with cache coherency of the buffers, so we can use any buffer we like.
|
||||
*/
|
||||
|
||||
/**
|
||||
* struct spi_fiq_code - FIQ code and header
|
||||
* @length: The length of the code fragment, excluding this header.
|
||||
* @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
|
||||
* @data: The code itself to install as a FIQ handler.
|
||||
*/
|
||||
struct spi_fiq_code {
|
||||
u32 length;
|
||||
u32 ack_offset;
|
||||
u8 data[0];
|
||||
};
|
||||
|
||||
extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
|
||||
extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
|
||||
extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
|
||||
|
||||
/**
|
||||
* ack_bit - turn IRQ into IRQ acknowledgement bit
|
||||
* @irq: The interrupt number
|
||||
*
|
||||
* Returns the bit to write to the interrupt acknowledge register.
|
||||
*/
|
||||
static inline u32 ack_bit(unsigned int irq)
|
||||
{
|
||||
return 1 << (irq - IRQ_EINT0);
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
|
||||
* @hw: The hardware state.
|
||||
*
|
||||
* Claim the FIQ handler (only one can be active at any one time) and
|
||||
* then setup the correct transfer code for this transfer.
|
||||
*
|
||||
* This call updates all the necessary state information if sucessful,
|
||||
* so the caller does not need to do anything more than start the transfer
|
||||
* as normal, since the IRQ will have been re-routed to the FIQ handler.
|
||||
*/
|
||||
void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
|
||||
{
|
||||
struct pt_regs regs;
|
||||
enum spi_fiq_mode mode;
|
||||
struct spi_fiq_code *code;
|
||||
int ret;
|
||||
|
||||
if (!hw->fiq_claimed) {
|
||||
/* try and claim fiq if we haven't got it, and if not
|
||||
* then return and simply use another transfer method */
|
||||
|
||||
ret = claim_fiq(&hw->fiq_handler);
|
||||
if (ret)
|
||||
return;
|
||||
}
|
||||
|
||||
if (hw->tx && !hw->rx)
|
||||
mode = FIQ_MODE_TX;
|
||||
else if (hw->rx && !hw->tx)
|
||||
mode = FIQ_MODE_RX;
|
||||
else
|
||||
mode = FIQ_MODE_TXRX;
|
||||
|
||||
regs.uregs[fiq_rspi] = (long)hw->regs;
|
||||
regs.uregs[fiq_rrx] = (long)hw->rx;
|
||||
regs.uregs[fiq_rtx] = (long)hw->tx + 1;
|
||||
regs.uregs[fiq_rcount] = hw->len - 1;
|
||||
regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
|
||||
|
||||
set_fiq_regs(®s);
|
||||
|
||||
if (hw->fiq_mode != mode) {
|
||||
u32 *ack_ptr;
|
||||
|
||||
hw->fiq_mode = mode;
|
||||
|
||||
switch (mode) {
|
||||
case FIQ_MODE_TX:
|
||||
code = &s3c24xx_spi_fiq_tx;
|
||||
break;
|
||||
case FIQ_MODE_RX:
|
||||
code = &s3c24xx_spi_fiq_rx;
|
||||
break;
|
||||
case FIQ_MODE_TXRX:
|
||||
code = &s3c24xx_spi_fiq_txrx;
|
||||
break;
|
||||
default:
|
||||
code = NULL;
|
||||
}
|
||||
|
||||
BUG_ON(!code);
|
||||
|
||||
ack_ptr = (u32 *)&code->data[code->ack_offset];
|
||||
*ack_ptr = ack_bit(hw->irq);
|
||||
|
||||
set_fiq_handler(&code->data, code->length);
|
||||
}
|
||||
|
||||
s3c24xx_set_fiq(hw->irq, true);
|
||||
|
||||
hw->fiq_mode = mode;
|
||||
hw->fiq_inuse = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c24xx_spi_fiqop - FIQ core code callback
|
||||
* @pw: Data registered with the handler
|
||||
* @release: Whether this is a release or a return.
|
||||
*
|
||||
* Called by the FIQ code when another module wants to use the FIQ, so
|
||||
* return whether we are currently using this or not and then update our
|
||||
* internal state.
|
||||
*/
|
||||
static int s3c24xx_spi_fiqop(void *pw, int release)
|
||||
{
|
||||
struct s3c24xx_spi *hw = pw;
|
||||
int ret = 0;
|
||||
|
||||
if (release) {
|
||||
if (hw->fiq_inuse)
|
||||
ret = -EBUSY;
|
||||
|
||||
/* note, we do not need to unroute the FIQ, as the FIQ
|
||||
* vector code de-routes it to signal the end of transfer */
|
||||
|
||||
hw->fiq_mode = FIQ_MODE_NONE;
|
||||
hw->fiq_claimed = 0;
|
||||
} else {
|
||||
hw->fiq_claimed = 1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c24xx_spi_initfiq - setup the information for the FIQ core
|
||||
* @hw: The hardware state.
|
||||
*
|
||||
* Setup the fiq_handler block to pass to the FIQ core.
|
||||
*/
|
||||
static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
|
||||
{
|
||||
hw->fiq_handler.dev_id = hw;
|
||||
hw->fiq_handler.name = dev_name(hw->dev);
|
||||
hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c24xx_spi_usefiq - return if we should be using FIQ.
|
||||
* @hw: The hardware state.
|
||||
*
|
||||
* Return true if the platform data specifies whether this channel is
|
||||
* allowed to use the FIQ.
|
||||
*/
|
||||
static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
|
||||
{
|
||||
return hw->pdata->use_fiq;
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c24xx_spi_usingfiq - return if channel is using FIQ
|
||||
* @spi: The hardware state.
|
||||
*
|
||||
* Return whether the channel is currently using the FIQ (separate from
|
||||
* whether the FIQ is claimed).
|
||||
*/
|
||||
static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
|
||||
{
|
||||
return spi->fiq_inuse;
|
||||
}
|
||||
#else
|
||||
|
||||
static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
|
||||
static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
|
||||
static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
|
||||
static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
|
||||
|
||||
#endif /* CONFIG_SPI_S3C24XX_FIQ */
|
||||
|
||||
static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
|
||||
{
|
||||
struct s3c24xx_spi *hw = to_hw(spi);
|
||||
|
||||
dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
|
||||
t->tx_buf, t->rx_buf, t->len);
|
||||
|
||||
hw->tx = t->tx_buf;
|
||||
hw->rx = t->rx_buf;
|
||||
hw->len = t->len;
|
||||
@@ -228,11 +429,14 @@ static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
|
||||
|
||||
init_completion(&hw->done);
|
||||
|
||||
hw->fiq_inuse = 0;
|
||||
if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
|
||||
s3c24xx_spi_tryfiq(hw);
|
||||
|
||||
/* send the first byte */
|
||||
writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
|
||||
|
||||
wait_for_completion(&hw->done);
|
||||
|
||||
return hw->count;
|
||||
}
|
||||
|
||||
@@ -254,17 +458,27 @@ static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
|
||||
goto irq_done;
|
||||
}
|
||||
|
||||
hw->count++;
|
||||
if (!s3c24xx_spi_usingfiq(hw)) {
|
||||
hw->count++;
|
||||
|
||||
if (hw->rx)
|
||||
hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
|
||||
if (hw->rx)
|
||||
hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
|
||||
|
||||
count++;
|
||||
count++;
|
||||
|
||||
if (count < hw->len)
|
||||
writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
|
||||
else
|
||||
complete(&hw->done);
|
||||
} else {
|
||||
hw->count = hw->len;
|
||||
hw->fiq_inuse = 0;
|
||||
|
||||
if (hw->rx)
|
||||
hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
|
||||
|
||||
if (count < hw->len)
|
||||
writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
|
||||
else
|
||||
complete(&hw->done);
|
||||
}
|
||||
|
||||
irq_done:
|
||||
return IRQ_HANDLED;
|
||||
@@ -322,6 +536,10 @@ static int __init s3c24xx_spi_probe(struct platform_device *pdev)
|
||||
platform_set_drvdata(pdev, hw);
|
||||
init_completion(&hw->done);
|
||||
|
||||
/* initialise fiq handler */
|
||||
|
||||
s3c24xx_spi_initfiq(hw);
|
||||
|
||||
/* setup the master state. */
|
||||
|
||||
/* the spi->mode bits understood by this driver: */
|
||||
|
||||
@@ -0,0 +1,116 @@
|
||||
/* linux/drivers/spi/spi_s3c24xx_fiq.S
|
||||
*
|
||||
* Copyright 2009 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C24XX SPI - FIQ pseudo-DMA transfer code
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-irq.h>
|
||||
#include <plat/regs-spi.h>
|
||||
|
||||
#include "spi_s3c24xx_fiq.h"
|
||||
|
||||
.text
|
||||
|
||||
@ entry to these routines is as follows, with the register names
|
||||
@ defined in fiq.h so that they can be shared with the C files which
|
||||
@ setup the calling registers.
|
||||
@
|
||||
@ fiq_rirq The base of the IRQ registers to find S3C2410_SRCPND
|
||||
@ fiq_rtmp Temporary register to hold tx/rx data
|
||||
@ fiq_rspi The base of the SPI register block
|
||||
@ fiq_rtx The tx buffer pointer
|
||||
@ fiq_rrx The rx buffer pointer
|
||||
@ fiq_rcount The number of bytes to move
|
||||
|
||||
@ each entry starts with a word entry of how long it is
|
||||
@ and an offset to the irq acknowledgment word
|
||||
|
||||
ENTRY(s3c24xx_spi_fiq_rx)
|
||||
s3c24xx_spi_fix_rx:
|
||||
.word fiq_rx_end - fiq_rx_start
|
||||
.word fiq_rx_irq_ack - fiq_rx_start
|
||||
fiq_rx_start:
|
||||
ldr fiq_rtmp, fiq_rx_irq_ack
|
||||
str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
|
||||
|
||||
ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
|
||||
strb fiq_rtmp, [ fiq_rrx ], #1
|
||||
|
||||
mov fiq_rtmp, #0xff
|
||||
strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
|
||||
|
||||
subs fiq_rcount, fiq_rcount, #1
|
||||
subnes pc, lr, #4 @@ return, still have work to do
|
||||
|
||||
@@ set IRQ controller so that next op will trigger IRQ
|
||||
mov fiq_rtmp, #0
|
||||
str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
|
||||
subs pc, lr, #4
|
||||
|
||||
fiq_rx_irq_ack:
|
||||
.word 0
|
||||
fiq_rx_end:
|
||||
|
||||
ENTRY(s3c24xx_spi_fiq_txrx)
|
||||
s3c24xx_spi_fiq_txrx:
|
||||
.word fiq_txrx_end - fiq_txrx_start
|
||||
.word fiq_txrx_irq_ack - fiq_txrx_start
|
||||
fiq_txrx_start:
|
||||
|
||||
ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
|
||||
strb fiq_rtmp, [ fiq_rrx ], #1
|
||||
|
||||
ldr fiq_rtmp, fiq_txrx_irq_ack
|
||||
str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
|
||||
|
||||
ldrb fiq_rtmp, [ fiq_rtx ], #1
|
||||
strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
|
||||
|
||||
subs fiq_rcount, fiq_rcount, #1
|
||||
subnes pc, lr, #4 @@ return, still have work to do
|
||||
|
||||
mov fiq_rtmp, #0
|
||||
str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
|
||||
subs pc, lr, #4
|
||||
|
||||
fiq_txrx_irq_ack:
|
||||
.word 0
|
||||
|
||||
fiq_txrx_end:
|
||||
|
||||
ENTRY(s3c24xx_spi_fiq_tx)
|
||||
s3c24xx_spi_fix_tx:
|
||||
.word fiq_tx_end - fiq_tx_start
|
||||
.word fiq_tx_irq_ack - fiq_tx_start
|
||||
fiq_tx_start:
|
||||
ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
|
||||
|
||||
ldr fiq_rtmp, fiq_tx_irq_ack
|
||||
str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
|
||||
|
||||
ldrb fiq_rtmp, [ fiq_rtx ], #1
|
||||
strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
|
||||
|
||||
subs fiq_rcount, fiq_rcount, #1
|
||||
subnes pc, lr, #4 @@ return, still have work to do
|
||||
|
||||
mov fiq_rtmp, #0
|
||||
str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
|
||||
subs pc, lr, #4
|
||||
|
||||
fiq_tx_irq_ack:
|
||||
.word 0
|
||||
|
||||
fiq_tx_end:
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,26 @@
|
||||
/* linux/drivers/spi/spi_s3c24xx_fiq.h
|
||||
*
|
||||
* Copyright 2009 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C24XX SPI - FIQ pseudo-DMA transfer support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* We have R8 through R13 to play with */
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define __REG_NR(x) r##x
|
||||
#else
|
||||
#define __REG_NR(x) (x)
|
||||
#endif
|
||||
|
||||
#define fiq_rspi __REG_NR(8)
|
||||
#define fiq_rtmp __REG_NR(9)
|
||||
#define fiq_rrx __REG_NR(10)
|
||||
#define fiq_rtx __REG_NR(11)
|
||||
#define fiq_rcount __REG_NR(12)
|
||||
#define fiq_rirq __REG_NR(13)
|
||||
File diff suppressed because it is too large
Load Diff
@@ -148,7 +148,7 @@ static int sh_sci_spi_probe(struct platform_device *dev)
|
||||
ret = -ENOENT;
|
||||
goto err1;
|
||||
}
|
||||
sp->membase = ioremap(r->start, r->end - r->start + 1);
|
||||
sp->membase = ioremap(r->start, resource_size(r));
|
||||
if (!sp->membase) {
|
||||
ret = -ENXIO;
|
||||
goto err1;
|
||||
|
||||
@@ -375,12 +375,10 @@ static int __init txx9spi_probe(struct platform_device *dev)
|
||||
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
goto exit_busy;
|
||||
if (!devm_request_mem_region(&dev->dev,
|
||||
res->start, res->end - res->start + 1,
|
||||
if (!devm_request_mem_region(&dev->dev, res->start, resource_size(res),
|
||||
"spi_txx9"))
|
||||
goto exit_busy;
|
||||
c->membase = devm_ioremap(&dev->dev,
|
||||
res->start, res->end - res->start + 1);
|
||||
c->membase = devm_ioremap(&dev->dev, res->start, resource_size(res));
|
||||
if (!c->membase)
|
||||
goto exit_busy;
|
||||
|
||||
|
||||
@@ -53,7 +53,7 @@
|
||||
#define SPIDEV_MAJOR 153 /* assigned */
|
||||
#define N_SPI_MINORS 32 /* ... up to 256 */
|
||||
|
||||
static unsigned long minors[N_SPI_MINORS / BITS_PER_LONG];
|
||||
static DECLARE_BITMAP(minors, N_SPI_MINORS);
|
||||
|
||||
|
||||
/* Bit masks for spi_device.mode management. Note that incorrect
|
||||
@@ -558,7 +558,7 @@ static struct class *spidev_class;
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
static int spidev_probe(struct spi_device *spi)
|
||||
static int __devinit spidev_probe(struct spi_device *spi)
|
||||
{
|
||||
struct spidev_data *spidev;
|
||||
int status;
|
||||
@@ -607,7 +607,7 @@ static int spidev_probe(struct spi_device *spi)
|
||||
return status;
|
||||
}
|
||||
|
||||
static int spidev_remove(struct spi_device *spi)
|
||||
static int __devexit spidev_remove(struct spi_device *spi)
|
||||
{
|
||||
struct spidev_data *spidev = spi_get_drvdata(spi);
|
||||
|
||||
@@ -629,7 +629,7 @@ static int spidev_remove(struct spi_device *spi)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct spi_driver spidev_spi = {
|
||||
static struct spi_driver spidev_spi_driver = {
|
||||
.driver = {
|
||||
.name = "spidev",
|
||||
.owner = THIS_MODULE,
|
||||
@@ -661,14 +661,14 @@ static int __init spidev_init(void)
|
||||
|
||||
spidev_class = class_create(THIS_MODULE, "spidev");
|
||||
if (IS_ERR(spidev_class)) {
|
||||
unregister_chrdev(SPIDEV_MAJOR, spidev_spi.driver.name);
|
||||
unregister_chrdev(SPIDEV_MAJOR, spidev_spi_driver.driver.name);
|
||||
return PTR_ERR(spidev_class);
|
||||
}
|
||||
|
||||
status = spi_register_driver(&spidev_spi);
|
||||
status = spi_register_driver(&spidev_spi_driver);
|
||||
if (status < 0) {
|
||||
class_destroy(spidev_class);
|
||||
unregister_chrdev(SPIDEV_MAJOR, spidev_spi.driver.name);
|
||||
unregister_chrdev(SPIDEV_MAJOR, spidev_spi_driver.driver.name);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
@@ -676,9 +676,9 @@ module_init(spidev_init);
|
||||
|
||||
static void __exit spidev_exit(void)
|
||||
{
|
||||
spi_unregister_driver(&spidev_spi);
|
||||
spi_unregister_driver(&spidev_spi_driver);
|
||||
class_destroy(spidev_class);
|
||||
unregister_chrdev(SPIDEV_MAJOR, spidev_spi.driver.name);
|
||||
unregister_chrdev(SPIDEV_MAJOR, spidev_spi_driver.driver.name);
|
||||
}
|
||||
module_exit(spidev_exit);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user