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https://github.com/linux-apfs/linux-apfs.git
synced 2026-05-01 15:00:59 -07:00
Merge remote-tracking branch 'kumar/next' into next
From Kumar Gala: << Add support for T4 and B4 SoC families from Freescale, e6500 altivec support, some various board fixes and other minor cleanups. >>
This commit is contained in:
Benjamin Herrenschmidt
@@ -333,6 +333,8 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
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return 0;
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}
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static struct lock_class_key fsl_msi_irq_class;
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static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
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int offset, int irq_index)
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{
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@@ -351,7 +353,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
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dev_err(&dev->dev, "No memory for MSI cascade data\n");
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return -ENOMEM;
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}
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irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
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msi->msi_virqs[irq_index] = virt_msir;
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cascade_data->index = offset;
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cascade_data->msi_data = msi;
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@@ -54,16 +54,63 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
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return;
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}
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static int __init fsl_pcie_check_link(struct pci_controller *hose)
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static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
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int, int, u32 *);
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static int fsl_pcie_check_link(struct pci_controller *hose)
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{
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u32 val;
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u32 val = 0;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
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if (hose->ops->read == fsl_indirect_read_config) {
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struct pci_bus bus;
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bus.number = 0;
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bus.sysdata = hose;
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bus.ops = hose->ops;
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indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
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} else
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early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return 1;
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} else {
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struct ccsr_pci __iomem *pci = hose->private_data;
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/* for PCIe IP rev 3.0 or greater use CSR0 for link state */
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val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
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>> PEX_CSR0_LTSSM_SHIFT;
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if (val != PEX_CSR0_LTSSM_L0)
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return 1;
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}
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early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return 1;
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return 0;
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}
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static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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if (fsl_pcie_check_link(hose))
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hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
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else
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hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
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return indirect_read_config(bus, devfn, offset, len, val);
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}
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static struct pci_ops fsl_indirect_pci_ops =
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{
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.read = fsl_indirect_read_config,
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.write = indirect_write_config,
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};
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static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
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resource_size_t cfg_addr,
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resource_size_t cfg_data, u32 flags)
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{
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setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
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hose->ops = &fsl_indirect_pci_ops;
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}
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#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
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#define MAX_PHYS_ADDR_BITS 40
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@@ -106,7 +153,7 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
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flags |= 0x10000000; /* enable relaxed ordering */
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for (i = 0; size > 0; i++) {
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unsigned int bits = min(__ilog2(size),
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unsigned int bits = min(ilog2(size),
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__ffs(pci_addr | phys_addr));
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if (index + i >= 5)
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@@ -126,10 +173,9 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
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}
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/* atmu setup for fsl pci/pcie controller */
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static void setup_pci_atmu(struct pci_controller *hose,
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struct resource *rsrc)
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static void setup_pci_atmu(struct pci_controller *hose)
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{
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struct ccsr_pci __iomem *pci;
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struct ccsr_pci __iomem *pci = hose->private_data;
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int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
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u64 mem, sz, paddr_hi = 0;
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u64 paddr_lo = ULLONG_MAX;
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@@ -140,15 +186,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
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const u64 *reg;
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int len;
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pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
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(u64)rsrc->start, (u64)resource_size(rsrc));
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pci = ioremap(rsrc->start, resource_size(rsrc));
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if (!pci) {
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dev_err(hose->parent, "Unable to map ATMU registers\n");
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return;
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}
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if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
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if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
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win_idx = 2;
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@@ -196,7 +233,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
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out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
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/* Enable, IO R/W */
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out_be32(&pci->pow[j].powar, 0x80088000
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| (__ilog2(hose->io_resource.end
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| (ilog2(hose->io_resource.end
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- hose->io_resource.start + 1) - 1));
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}
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}
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@@ -207,12 +244,12 @@ static void setup_pci_atmu(struct pci_controller *hose,
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if (paddr_hi == paddr_lo) {
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pr_err("%s: No outbound window space\n", name);
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goto out;
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return;
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}
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if (paddr_lo == 0) {
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pr_err("%s: No space for inbound window\n", name);
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goto out;
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return;
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}
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/* setup PCSRBAR/PEXCSRBAR */
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@@ -261,7 +298,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
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}
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sz = min(mem, paddr_lo);
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mem_log = __ilog2_u64(sz);
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mem_log = ilog2(sz);
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/* PCIe can overmap inbound & outbound since RX & TX are separated */
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if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
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@@ -290,7 +327,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
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* SWIOTLB and access the full range of memory
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*/
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if (sz != mem) {
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mem_log = __ilog2_u64(mem);
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mem_log = ilog2(mem);
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/* Size window up if we dont fit in exact power-of-2 */
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if ((1ull << mem_log) != mem)
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@@ -327,7 +364,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
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sz -= 1ull << mem_log;
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if (sz) {
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mem_log = __ilog2_u64(sz);
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mem_log = ilog2(sz);
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piwar |= (mem_log - 1);
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out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
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@@ -358,9 +395,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
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pr_info("%s: DMA window size is 0x%llx\n", name,
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(u64)hose->dma_window_size);
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}
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out:
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iounmap(pci);
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}
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static void __init setup_pci_cmd(struct pci_controller *hose)
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@@ -429,6 +463,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
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const int *bus_range;
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u8 hdr_type, progif;
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struct device_node *dev;
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struct ccsr_pci __iomem *pci;
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dev = pdev->dev.of_node;
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@@ -461,8 +496,18 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
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PPC_INDIRECT_TYPE_BIG_ENDIAN);
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pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
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(u64)rsrc.start, (u64)resource_size(&rsrc));
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pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
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if (!hose->private_data)
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goto no_bridge;
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fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
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PPC_INDIRECT_TYPE_BIG_ENDIAN);
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if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
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hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
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if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
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/* For PCIE read HEADER_TYPE to identify controler mode */
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@@ -500,11 +545,12 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
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pci_process_bridge_OF_ranges(hose, dev, is_primary);
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/* Setup PEX window registers */
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setup_pci_atmu(hose, &rsrc);
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setup_pci_atmu(hose);
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return 0;
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no_bridge:
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iounmap(hose->private_data);
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/* unmap cfg_data & cfg_addr separately if not on same page */
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if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
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((unsigned long)hose->cfg_addr & PAGE_MASK))
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@@ -681,6 +727,7 @@ static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
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WARN_ON(hose->dn->data);
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hose->dn->data = pcie;
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hose->ops = &mpc83xx_pcie_ops;
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hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
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out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
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out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
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@@ -766,8 +813,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
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if (ret)
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goto err0;
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} else {
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setup_indirect_pci(hose, rsrc_cfg.start,
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rsrc_cfg.start + 4, 0);
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fsl_setup_indirect_pci(hose, rsrc_cfg.start,
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rsrc_cfg.start + 4, 0);
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}
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printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
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@@ -836,6 +883,7 @@ static const struct of_device_id pci_ids[] = {
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{ .compatible = "fsl,qoriq-pcie-v2.2", },
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{ .compatible = "fsl,qoriq-pcie-v2.3", },
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{ .compatible = "fsl,qoriq-pcie-v2.4", },
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{ .compatible = "fsl,qoriq-pcie-v3.0", },
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/*
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* The following entries are for compatibility with older device
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@@ -14,9 +14,12 @@
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#ifndef __POWERPC_FSL_PCI_H
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#define __POWERPC_FSL_PCI_H
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struct platform_device;
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#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
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#define PCIE_LTSSM_L0 0x16 /* L0 state */
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#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
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#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
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#define PIWAR_EN 0x80000000 /* Enable */
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#define PIWAR_PF 0x20000000 /* prefetch */
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#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
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@@ -89,6 +92,16 @@ struct ccsr_pci {
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__be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
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__be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
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__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
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u8 res_e38[200];
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__be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
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u8 res_f04[16];
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__be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
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#define PEX_CSR0_LTSSM_MASK 0xFC
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#define PEX_CSR0_LTSSM_SHIFT 2
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#define PEX_CSR0_LTSSM_L0 0x11
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__be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
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u8 res_f1c[228];
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};
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extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
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@@ -20,9 +20,8 @@
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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static int
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indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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volatile void __iomem *cfg_data;
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@@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 val)
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int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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volatile void __iomem *cfg_data;
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@@ -22,6 +22,6 @@ config UCC
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config QE_USB
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bool
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default y if USB_GADGET_FSL_QE
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default y if USB_FSL_QE
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help
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QE USB Controller support
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