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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull more powerpc updates from Ben Herrenschmidt: "Here are the remaining bits I was mentioning earlier. Mostly bug fixes and new selftests from Michael (yay !). He also removed the WSP platform and A2 core support which were dead before release, so less clutter. One little "feature" I snuck in is the doorbell IPI support for non-virtualized P8 which speeds up IPIs significantly between threads of a core" * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (34 commits) powerpc/book3s: Fix some ABIv2 issues in machine check code powerpc/book3s: Fix guest MC delivery mechanism to avoid soft lockups in guest. powerpc/book3s: Increment the mce counter during machine_check_early call. powerpc/book3s: Add stack overflow check in machine check handler. powerpc/book3s: Fix machine check handling for unhandled errors powerpc/eeh: Dump PE location code powerpc/powernv: Enable POWER8 doorbell IPIs powerpc/cpuidle: Only clear LPCR decrementer wakeup bit on fast sleep entry powerpc/powernv: Fix killed EEH event powerpc: fix typo 'CONFIG_PMAC' powerpc: fix typo 'CONFIG_PPC_CPU' powerpc/powernv: Don't escalate non-existing frozen PE powerpc/eeh: Report frozen parent PE prior to child PE powerpc/eeh: Clear frozen state for child PE powerpc/powernv: Reduce panic timeout from 180s to 10s powerpc/xmon: avoid format string leaking to printk selftests/powerpc: Add tests of PMU EBBs selftests/powerpc: Add support for skipping tests selftests/powerpc: Put the test in a separate process group selftests/powerpc: Fix instruction loop for ABIv2 (LE) ...
This commit is contained in:
Linus Torvalds
@@ -235,11 +235,6 @@ config PPC_EARLY_DEBUG_USBGECKO
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Select this to enable early debugging for Nintendo GameCube/Wii
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consoles via an external USB Gecko adapter.
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config PPC_EARLY_DEBUG_WSP
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bool "Early debugging via WSP's internal UART"
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depends on PPC_WSP
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select PPC_UDBG_16550
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config PPC_EARLY_DEBUG_PS3GELIC
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bool "Early debugging through the PS3 Ethernet port"
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depends on PPC_PS3
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@@ -1,307 +0,0 @@
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CONFIG_PPC64=y
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CONFIG_PPC_BOOK3E_64=y
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# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
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CONFIG_SMP=y
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CONFIG_NR_CPUS=256
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CONFIG_EXPERIMENTAL=y
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CONFIG_SYSVIPC=y
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CONFIG_POSIX_MQUEUE=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_TASKSTATS=y
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CONFIG_TASK_DELAY_ACCT=y
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CONFIG_TASK_XACCT=y
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CONFIG_TASK_IO_ACCOUNTING=y
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CONFIG_AUDIT=y
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CONFIG_AUDITSYSCALL=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_LOG_BUF_SHIFT=19
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CONFIG_CGROUPS=y
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CONFIG_CGROUP_DEVICE=y
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CONFIG_CPUSETS=y
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CONFIG_CGROUP_CPUACCT=y
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CONFIG_RESOURCE_COUNTERS=y
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CONFIG_CGROUP_MEMCG=y
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CONFIG_CGROUP_MEMCG_SWAP=y
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CONFIG_NAMESPACES=y
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CONFIG_RELAY=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_RD_BZIP2=y
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CONFIG_RD_LZMA=y
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CONFIG_INITRAMFS_COMPRESSION_GZIP=y
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CONFIG_KALLSYMS_ALL=y
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CONFIG_EMBEDDED=y
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CONFIG_PERF_EVENTS=y
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CONFIG_PROFILING=y
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CONFIG_OPROFILE=y
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CONFIG_KPROBES=y
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CONFIG_MODULES=y
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CONFIG_MODULE_FORCE_LOAD=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODULE_FORCE_UNLOAD=y
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CONFIG_MODVERSIONS=y
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CONFIG_MODULE_SRCVERSION_ALL=y
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CONFIG_SCOM_DEBUGFS=y
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CONFIG_PPC_A2_DD2=y
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CONFIG_KVM_GUEST=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_HZ_100=y
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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CONFIG_BINFMT_MISC=y
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CONFIG_NUMA=y
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# CONFIG_MIGRATION is not set
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CONFIG_PPC_64K_PAGES=y
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CONFIG_SCHED_SMT=y
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE=""
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# CONFIG_SECCOMP is not set
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CONFIG_PCIEPORTBUS=y
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# CONFIG_PCIEASPM is not set
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CONFIG_PCI_MSI=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_XFRM_USER=m
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CONFIG_XFRM_SUB_POLICY=y
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CONFIG_XFRM_STATISTICS=y
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CONFIG_NET_KEY=m
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CONFIG_NET_KEY_MIGRATE=y
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CONFIG_INET=y
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CONFIG_IP_MULTICAST=y
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CONFIG_IP_ADVANCED_ROUTER=y
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CONFIG_IP_ROUTE_MULTIPATH=y
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CONFIG_IP_ROUTE_VERBOSE=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_PNP_BOOTP=y
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CONFIG_NET_IPIP=y
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CONFIG_IP_MROUTE=y
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CONFIG_IP_PIMSM_V1=y
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CONFIG_IP_PIMSM_V2=y
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CONFIG_SYN_COOKIES=y
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CONFIG_INET_AH=m
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CONFIG_INET_ESP=m
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CONFIG_INET_IPCOMP=m
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CONFIG_IPV6=y
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CONFIG_IPV6_PRIVACY=y
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CONFIG_IPV6_ROUTER_PREF=y
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CONFIG_IPV6_ROUTE_INFO=y
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CONFIG_IPV6_OPTIMISTIC_DAD=y
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CONFIG_INET6_AH=y
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CONFIG_INET6_ESP=y
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CONFIG_INET6_IPCOMP=y
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CONFIG_IPV6_MIP6=y
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CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
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CONFIG_IPV6_TUNNEL=y
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CONFIG_IPV6_MULTIPLE_TABLES=y
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CONFIG_IPV6_SUBTREES=y
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CONFIG_IPV6_MROUTE=y
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CONFIG_IPV6_PIMSM_V2=y
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CONFIG_NETFILTER=y
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CONFIG_NF_CONNTRACK=m
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CONFIG_NF_CONNTRACK_EVENTS=y
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CONFIG_NF_CT_PROTO_UDPLITE=m
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CONFIG_NF_CONNTRACK_FTP=m
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CONFIG_NF_CONNTRACK_IRC=m
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CONFIG_NF_CONNTRACK_TFTP=m
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CONFIG_NF_CT_NETLINK=m
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CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
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CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
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CONFIG_NETFILTER_XT_TARGET_MARK=m
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CONFIG_NETFILTER_XT_TARGET_NFLOG=m
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CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
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CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
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CONFIG_NETFILTER_XT_MATCH_COMMENT=m
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CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
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CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
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CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
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CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
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CONFIG_NETFILTER_XT_MATCH_DCCP=m
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CONFIG_NETFILTER_XT_MATCH_DSCP=m
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CONFIG_NETFILTER_XT_MATCH_ESP=m
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CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
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CONFIG_NETFILTER_XT_MATCH_HELPER=m
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CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
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CONFIG_NETFILTER_XT_MATCH_LENGTH=m
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CONFIG_NETFILTER_XT_MATCH_LIMIT=m
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CONFIG_NETFILTER_XT_MATCH_MAC=m
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CONFIG_NETFILTER_XT_MATCH_MARK=m
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CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
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CONFIG_NETFILTER_XT_MATCH_OWNER=m
|
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CONFIG_NETFILTER_XT_MATCH_POLICY=m
|
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CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
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CONFIG_NETFILTER_XT_MATCH_QUOTA=m
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CONFIG_NETFILTER_XT_MATCH_RATEEST=m
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CONFIG_NETFILTER_XT_MATCH_REALM=m
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CONFIG_NETFILTER_XT_MATCH_RECENT=m
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CONFIG_NETFILTER_XT_MATCH_SCTP=m
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CONFIG_NETFILTER_XT_MATCH_STATE=m
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CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
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CONFIG_NETFILTER_XT_MATCH_STRING=m
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CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
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CONFIG_NETFILTER_XT_MATCH_TIME=m
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CONFIG_NETFILTER_XT_MATCH_U32=m
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CONFIG_NF_CONNTRACK_IPV4=m
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CONFIG_IP_NF_QUEUE=m
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CONFIG_IP_NF_IPTABLES=m
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CONFIG_IP_NF_MATCH_AH=m
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CONFIG_IP_NF_MATCH_ECN=m
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CONFIG_IP_NF_MATCH_TTL=m
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CONFIG_IP_NF_FILTER=m
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CONFIG_IP_NF_TARGET_REJECT=m
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CONFIG_IP_NF_TARGET_LOG=m
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CONFIG_IP_NF_TARGET_ULOG=m
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CONFIG_NF_NAT=m
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CONFIG_IP_NF_TARGET_MASQUERADE=m
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CONFIG_IP_NF_TARGET_NETMAP=m
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CONFIG_IP_NF_TARGET_REDIRECT=m
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CONFIG_NET_TCPPROBE=y
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# CONFIG_WIRELESS is not set
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CONFIG_NET_9P=y
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CONFIG_NET_9P_DEBUG=y
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_DEVTMPFS=y
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CONFIG_MTD=y
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CONFIG_MTD_CHAR=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_ADV_OPTIONS=y
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CONFIG_MTD_CFI_LE_BYTE_SWAP=y
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_CFI_AMDSTD=y
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CONFIG_MTD_CFI_STAA=y
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CONFIG_MTD_PHYSMAP_OF=y
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CONFIG_PROC_DEVICETREE=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_CRYPTOLOOP=y
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CONFIG_BLK_DEV_NBD=m
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_SIZE=65536
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CONFIG_CDROM_PKTCDVD=y
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CONFIG_MISC_DEVICES=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_DEV_SR=y
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CONFIG_BLK_DEV_SR_VENDOR=y
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CONFIG_CHR_DEV_SG=y
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CONFIG_SCSI_MULTI_LUN=y
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CONFIG_SCSI_CONSTANTS=y
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CONFIG_SCSI_SPI_ATTRS=y
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CONFIG_SCSI_FC_ATTRS=y
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CONFIG_SCSI_ISCSI_ATTRS=m
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CONFIG_SCSI_SAS_ATTRS=m
|
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CONFIG_SCSI_SRP_ATTRS=y
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CONFIG_ATA=y
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CONFIG_SATA_AHCI=y
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CONFIG_SATA_SIL24=y
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CONFIG_SATA_MV=y
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CONFIG_SATA_SIL=y
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CONFIG_PATA_CMD64X=y
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CONFIG_PATA_MARVELL=y
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CONFIG_PATA_SIL680=y
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CONFIG_MD=y
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CONFIG_BLK_DEV_MD=y
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CONFIG_MD_LINEAR=y
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CONFIG_BLK_DEV_DM=y
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CONFIG_DM_CRYPT=y
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CONFIG_DM_SNAPSHOT=y
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CONFIG_DM_MIRROR=y
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CONFIG_DM_ZERO=y
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CONFIG_DM_UEVENT=y
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CONFIG_NETDEVICES=y
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CONFIG_TUN=y
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CONFIG_E1000E=y
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CONFIG_TIGON3=y
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# CONFIG_WLAN is not set
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# CONFIG_INPUT is not set
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# CONFIG_SERIO is not set
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# CONFIG_VT is not set
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CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_HW_RANDOM=y
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CONFIG_RAW_DRIVER=y
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CONFIG_MAX_RAW_DEVS=1024
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# CONFIG_HWMON is not set
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# CONFIG_VGA_ARB is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1511=y
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CONFIG_RTC_DRV_DS1553=y
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CONFIG_EXT2_FS=y
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CONFIG_EXT2_FS_XATTR=y
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CONFIG_EXT2_FS_POSIX_ACL=y
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CONFIG_EXT2_FS_SECURITY=y
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CONFIG_EXT2_FS_XIP=y
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CONFIG_EXT3_FS=y
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# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
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CONFIG_EXT3_FS_POSIX_ACL=y
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CONFIG_EXT3_FS_SECURITY=y
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CONFIG_EXT4_FS=y
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# CONFIG_DNOTIFY is not set
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CONFIG_FUSE_FS=y
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CONFIG_ISO9660_FS=y
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CONFIG_JOLIET=y
|
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CONFIG_ZISOFS=y
|
||||
CONFIG_UDF_FS=m
|
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CONFIG_MSDOS_FS=y
|
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CONFIG_VFAT_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_CONFIGFS_FS=m
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_NFS_V4_1=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_CIFS=y
|
||||
CONFIG_CIFS_WEAK_PW_HASH=y
|
||||
CONFIG_CIFS_XATTR=y
|
||||
CONFIG_CIFS_POSIX=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_CRC_CCITT=m
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_LIBCRC32C=m
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_STRIP_ASM_SYMS=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_FTRACE_SYSCALLS=y
|
||||
CONFIG_PPC_EMULATED_STATS=y
|
||||
CONFIG_XMON=y
|
||||
CONFIG_XMON_DEFAULT=y
|
||||
CONFIG_IRQ_DOMAIN_DEBUG=y
|
||||
CONFIG_PPC_EARLY_DEBUG=y
|
||||
CONFIG_KEYS_DEBUG_PROC_KEYS=y
|
||||
CONFIG_CRYPTO_NULL=m
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_CCM=m
|
||||
CONFIG_CRYPTO_GCM=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=m
|
||||
CONFIG_CRYPTO_SHA256=m
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_TGR192=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_AES=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
CONFIG_CRYPTO_SALSA20=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_TEA=m
|
||||
CONFIG_CRYPTO_TWOFISH=m
|
||||
CONFIG_CRYPTO_LZO=m
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
@@ -489,7 +489,6 @@ typedef struct scc_trans {
|
||||
#define FCC_GFMR_TCI ((uint)0x20000000)
|
||||
#define FCC_GFMR_TRX ((uint)0x10000000)
|
||||
#define FCC_GFMR_TTX ((uint)0x08000000)
|
||||
#define FCC_GFMR_TTX ((uint)0x08000000)
|
||||
#define FCC_GFMR_CDP ((uint)0x04000000)
|
||||
#define FCC_GFMR_CTSP ((uint)0x02000000)
|
||||
#define FCC_GFMR_CDS ((uint)0x01000000)
|
||||
|
||||
@@ -254,6 +254,7 @@ void *eeh_pe_traverse(struct eeh_pe *root,
|
||||
void *eeh_pe_dev_traverse(struct eeh_pe *root,
|
||||
eeh_traverse_func fn, void *flag);
|
||||
void eeh_pe_restore_bars(struct eeh_pe *pe);
|
||||
const char *eeh_pe_loc_get(struct eeh_pe *pe);
|
||||
struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
|
||||
|
||||
void *eeh_dev_init(struct device_node *dn, void *data);
|
||||
|
||||
@@ -33,7 +33,7 @@ struct eeh_event {
|
||||
|
||||
int eeh_event_init(void);
|
||||
int eeh_send_failure_event(struct eeh_pe *pe);
|
||||
void eeh_remove_event(struct eeh_pe *pe);
|
||||
void eeh_remove_event(struct eeh_pe *pe, bool force);
|
||||
void eeh_handle_event(struct eeh_pe *pe);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
@@ -223,10 +223,6 @@ typedef struct {
|
||||
unsigned int id;
|
||||
unsigned int active;
|
||||
unsigned long vdso_base;
|
||||
#ifdef CONFIG_PPC_ICSWX
|
||||
struct spinlock *cop_lockp; /* guard cop related stuff */
|
||||
unsigned long acop; /* mask of enabled coprocessor types */
|
||||
#endif /* CONFIG_PPC_ICSWX */
|
||||
#ifdef CONFIG_PPC_MM_SLICES
|
||||
u64 low_slices_psize; /* SLB page size encodings */
|
||||
u64 high_slices_psize; /* 4 bits per slice for now */
|
||||
|
||||
@@ -599,9 +599,9 @@ enum {
|
||||
};
|
||||
|
||||
struct OpalIoPhbErrorCommon {
|
||||
uint32_t version;
|
||||
uint32_t ioType;
|
||||
uint32_t len;
|
||||
__be32 version;
|
||||
__be32 ioType;
|
||||
__be32 len;
|
||||
};
|
||||
|
||||
struct OpalIoP7IOCPhbErrorData {
|
||||
@@ -666,64 +666,64 @@ struct OpalIoP7IOCPhbErrorData {
|
||||
struct OpalIoPhb3ErrorData {
|
||||
struct OpalIoPhbErrorCommon common;
|
||||
|
||||
uint32_t brdgCtl;
|
||||
__be32 brdgCtl;
|
||||
|
||||
/* PHB3 UTL regs */
|
||||
uint32_t portStatusReg;
|
||||
uint32_t rootCmplxStatus;
|
||||
uint32_t busAgentStatus;
|
||||
__be32 portStatusReg;
|
||||
__be32 rootCmplxStatus;
|
||||
__be32 busAgentStatus;
|
||||
|
||||
/* PHB3 cfg regs */
|
||||
uint32_t deviceStatus;
|
||||
uint32_t slotStatus;
|
||||
uint32_t linkStatus;
|
||||
uint32_t devCmdStatus;
|
||||
uint32_t devSecStatus;
|
||||
__be32 deviceStatus;
|
||||
__be32 slotStatus;
|
||||
__be32 linkStatus;
|
||||
__be32 devCmdStatus;
|
||||
__be32 devSecStatus;
|
||||
|
||||
/* cfg AER regs */
|
||||
uint32_t rootErrorStatus;
|
||||
uint32_t uncorrErrorStatus;
|
||||
uint32_t corrErrorStatus;
|
||||
uint32_t tlpHdr1;
|
||||
uint32_t tlpHdr2;
|
||||
uint32_t tlpHdr3;
|
||||
uint32_t tlpHdr4;
|
||||
uint32_t sourceId;
|
||||
__be32 rootErrorStatus;
|
||||
__be32 uncorrErrorStatus;
|
||||
__be32 corrErrorStatus;
|
||||
__be32 tlpHdr1;
|
||||
__be32 tlpHdr2;
|
||||
__be32 tlpHdr3;
|
||||
__be32 tlpHdr4;
|
||||
__be32 sourceId;
|
||||
|
||||
uint32_t rsv3;
|
||||
__be32 rsv3;
|
||||
|
||||
/* Record data about the call to allocate a buffer */
|
||||
uint64_t errorClass;
|
||||
uint64_t correlator;
|
||||
__be64 errorClass;
|
||||
__be64 correlator;
|
||||
|
||||
uint64_t nFir; /* 000 */
|
||||
uint64_t nFirMask; /* 003 */
|
||||
uint64_t nFirWOF; /* 008 */
|
||||
__be64 nFir; /* 000 */
|
||||
__be64 nFirMask; /* 003 */
|
||||
__be64 nFirWOF; /* 008 */
|
||||
|
||||
/* PHB3 MMIO Error Regs */
|
||||
uint64_t phbPlssr; /* 120 */
|
||||
uint64_t phbCsr; /* 110 */
|
||||
uint64_t lemFir; /* C00 */
|
||||
uint64_t lemErrorMask; /* C18 */
|
||||
uint64_t lemWOF; /* C40 */
|
||||
uint64_t phbErrorStatus; /* C80 */
|
||||
uint64_t phbFirstErrorStatus; /* C88 */
|
||||
uint64_t phbErrorLog0; /* CC0 */
|
||||
uint64_t phbErrorLog1; /* CC8 */
|
||||
uint64_t mmioErrorStatus; /* D00 */
|
||||
uint64_t mmioFirstErrorStatus; /* D08 */
|
||||
uint64_t mmioErrorLog0; /* D40 */
|
||||
uint64_t mmioErrorLog1; /* D48 */
|
||||
uint64_t dma0ErrorStatus; /* D80 */
|
||||
uint64_t dma0FirstErrorStatus; /* D88 */
|
||||
uint64_t dma0ErrorLog0; /* DC0 */
|
||||
uint64_t dma0ErrorLog1; /* DC8 */
|
||||
uint64_t dma1ErrorStatus; /* E00 */
|
||||
uint64_t dma1FirstErrorStatus; /* E08 */
|
||||
uint64_t dma1ErrorLog0; /* E40 */
|
||||
uint64_t dma1ErrorLog1; /* E48 */
|
||||
uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
|
||||
uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
|
||||
__be64 phbPlssr; /* 120 */
|
||||
__be64 phbCsr; /* 110 */
|
||||
__be64 lemFir; /* C00 */
|
||||
__be64 lemErrorMask; /* C18 */
|
||||
__be64 lemWOF; /* C40 */
|
||||
__be64 phbErrorStatus; /* C80 */
|
||||
__be64 phbFirstErrorStatus; /* C88 */
|
||||
__be64 phbErrorLog0; /* CC0 */
|
||||
__be64 phbErrorLog1; /* CC8 */
|
||||
__be64 mmioErrorStatus; /* D00 */
|
||||
__be64 mmioFirstErrorStatus; /* D08 */
|
||||
__be64 mmioErrorLog0; /* D40 */
|
||||
__be64 mmioErrorLog1; /* D48 */
|
||||
__be64 dma0ErrorStatus; /* D80 */
|
||||
__be64 dma0FirstErrorStatus; /* D88 */
|
||||
__be64 dma0ErrorLog0; /* DC0 */
|
||||
__be64 dma0ErrorLog1; /* DC8 */
|
||||
__be64 dma1ErrorStatus; /* E00 */
|
||||
__be64 dma1FirstErrorStatus; /* E08 */
|
||||
__be64 dma1ErrorLog0; /* E40 */
|
||||
__be64 dma1ErrorLog1; /* E48 */
|
||||
__be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
|
||||
__be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
|
||||
};
|
||||
|
||||
enum {
|
||||
@@ -851,8 +851,8 @@ int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t erro
|
||||
int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
|
||||
int64_t opal_get_epow_status(__be64 *status);
|
||||
int64_t opal_set_system_attention_led(uint8_t led_action);
|
||||
int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
|
||||
uint16_t *pci_error_type, uint16_t *severity);
|
||||
int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
|
||||
__be16 *pci_error_type, __be16 *severity);
|
||||
int64_t opal_pci_poll(uint64_t phb_id);
|
||||
int64_t opal_return_cpu(void);
|
||||
int64_t opal_reinit_cpus(uint64_t flags);
|
||||
|
||||
@@ -110,15 +110,6 @@
|
||||
#define TLB1_UR ASM_CONST(0x0000000000000002)
|
||||
#define TLB1_SR ASM_CONST(0x0000000000000001)
|
||||
|
||||
#ifdef CONFIG_PPC_EARLY_DEBUG_WSP
|
||||
#define WSP_UART_PHYS 0xffc000c000
|
||||
/* This needs to be careful chosen to hit a !0 congruence class
|
||||
* in the TLB since we bolt it in way 3, which is already occupied
|
||||
* by our linear mapping primary bolted entry in CC 0.
|
||||
*/
|
||||
#define WSP_UART_VIRT 0xf000000000001000
|
||||
#endif
|
||||
|
||||
/* A2 erativax attributes definitions */
|
||||
#define ERATIVAX_RS_IS_ALL 0x000
|
||||
#define ERATIVAX_RS_IS_TID 0x040
|
||||
|
||||
@@ -16,13 +16,15 @@ struct thread_struct;
|
||||
extern struct task_struct *_switch(struct thread_struct *prev,
|
||||
struct thread_struct *next);
|
||||
#ifdef CONFIG_PPC_BOOK3S_64
|
||||
static inline void save_tar(struct thread_struct *prev)
|
||||
static inline void save_early_sprs(struct thread_struct *prev)
|
||||
{
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_207S))
|
||||
prev->tar = mfspr(SPRN_TAR);
|
||||
if (cpu_has_feature(CPU_FTR_DSCR))
|
||||
prev->dscr = mfspr(SPRN_DSCR);
|
||||
}
|
||||
#else
|
||||
static inline void save_tar(struct thread_struct *prev) {}
|
||||
static inline void save_early_sprs(struct thread_struct *prev) {}
|
||||
#endif
|
||||
|
||||
extern void enable_kernel_fp(void);
|
||||
@@ -84,6 +86,8 @@ static inline void clear_task_ebb(struct task_struct *t)
|
||||
{
|
||||
#ifdef CONFIG_PPC_BOOK3S_64
|
||||
/* EBB perf events are not inherited, so clear all EBB state. */
|
||||
t->thread.ebbrr = 0;
|
||||
t->thread.ebbhr = 0;
|
||||
t->thread.bescr = 0;
|
||||
t->thread.mmcr2 = 0;
|
||||
t->thread.mmcr0 = 0;
|
||||
|
||||
@@ -1,14 +0,0 @@
|
||||
/*
|
||||
* Copyright 2011 Michael Ellerman, IBM Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
#ifndef __ASM_POWERPC_WSP_H
|
||||
#define __ASM_POWERPC_WSP_H
|
||||
|
||||
extern int wsp_get_chip_id(struct device_node *dn);
|
||||
|
||||
#endif /* __ASM_POWERPC_WSP_H */
|
||||
@@ -41,5 +41,6 @@
|
||||
#define PPC_FEATURE2_EBB 0x10000000
|
||||
#define PPC_FEATURE2_ISEL 0x08000000
|
||||
#define PPC_FEATURE2_TAR 0x04000000
|
||||
#define PPC_FEATURE2_VEC_CRYPTO 0x02000000
|
||||
|
||||
#endif /* _UAPI__ASM_POWERPC_CPUTABLE_H */
|
||||
|
||||
@@ -43,7 +43,6 @@ obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o
|
||||
obj-$(CONFIG_PPC_BOOK3S_64) += mce.o mce_power.o
|
||||
obj64-$(CONFIG_RELOCATABLE) += reloc_64.o
|
||||
obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o
|
||||
obj-$(CONFIG_PPC_A2) += cpu_setup_a2.o
|
||||
obj-$(CONFIG_PPC64) += vdso64/
|
||||
obj-$(CONFIG_ALTIVEC) += vecemu.o
|
||||
obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
|
||||
|
||||
@@ -1,120 +0,0 @@
|
||||
/*
|
||||
* A2 specific assembly support code
|
||||
*
|
||||
* Copyright 2009 Ben Herrenschmidt, IBM Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/ppc_asm.h>
|
||||
#include <asm/ppc-opcode.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reg_a2.h>
|
||||
#include <asm/reg.h>
|
||||
#include <asm/thread_info.h>
|
||||
|
||||
/*
|
||||
* Disable thdid and class fields in ERATs to bump PID to full 14 bits capacity.
|
||||
* This also prevents external LPID accesses but that isn't a problem when not a
|
||||
* guest. Under PV, this setting will be ignored and MMUCR will return the right
|
||||
* number of PID bits we can use.
|
||||
*/
|
||||
#define MMUCR1_EXTEND_PID \
|
||||
(MMUCR1_ICTID | MMUCR1_ITTID | MMUCR1_DCTID | \
|
||||
MMUCR1_DTTID | MMUCR1_DCCD)
|
||||
|
||||
/*
|
||||
* Use extended PIDs if enabled.
|
||||
* Don't clear the ERATs on context sync events and enable I & D LRU.
|
||||
* Enable ERAT back invalidate when tlbwe overwrites an entry.
|
||||
*/
|
||||
#define INITIAL_MMUCR1 \
|
||||
(MMUCR1_EXTEND_PID | MMUCR1_CSINV_NEVER | MMUCR1_IRRE | \
|
||||
MMUCR1_DRRE | MMUCR1_TLBWE_BINV)
|
||||
|
||||
_GLOBAL(__setup_cpu_a2)
|
||||
/* Some of these are actually thread local and some are
|
||||
* core local but doing it always won't hurt
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PPC_ICSWX
|
||||
/* Make sure ACOP starts out as zero */
|
||||
li r3,0
|
||||
mtspr SPRN_ACOP,r3
|
||||
|
||||
/* Skip the following if we are in Guest mode */
|
||||
mfmsr r3
|
||||
andis. r0,r3,MSR_GS@h
|
||||
bne _icswx_skip_guest
|
||||
|
||||
/* Enable icswx instruction */
|
||||
mfspr r3,SPRN_A2_CCR2
|
||||
ori r3,r3,A2_CCR2_ENABLE_ICSWX
|
||||
mtspr SPRN_A2_CCR2,r3
|
||||
|
||||
/* Unmask all CTs in HACOP */
|
||||
li r3,-1
|
||||
mtspr SPRN_HACOP,r3
|
||||
_icswx_skip_guest:
|
||||
#endif /* CONFIG_PPC_ICSWX */
|
||||
|
||||
/* Enable doorbell */
|
||||
mfspr r3,SPRN_A2_CCR2
|
||||
oris r3,r3,A2_CCR2_ENABLE_PC@h
|
||||
mtspr SPRN_A2_CCR2,r3
|
||||
isync
|
||||
|
||||
/* Setup CCR0 to disable power saving for now as it's busted
|
||||
* in the current implementations. Setup CCR1 to wake on
|
||||
* interrupts normally (we write the default value but who
|
||||
* knows what FW may have clobbered...)
|
||||
*/
|
||||
li r3,0
|
||||
mtspr SPRN_A2_CCR0, r3
|
||||
LOAD_REG_IMMEDIATE(r3,0x0f0f0f0f)
|
||||
mtspr SPRN_A2_CCR1, r3
|
||||
|
||||
/* Initialise MMUCR1 */
|
||||
lis r3,INITIAL_MMUCR1@h
|
||||
ori r3,r3,INITIAL_MMUCR1@l
|
||||
mtspr SPRN_MMUCR1,r3
|
||||
|
||||
/* Set MMUCR2 to enable 4K, 64K, 1M, 16M and 1G pages */
|
||||
LOAD_REG_IMMEDIATE(r3, 0x000a7531)
|
||||
mtspr SPRN_MMUCR2,r3
|
||||
|
||||
/* Set MMUCR3 to write all thids bit to the TLB */
|
||||
LOAD_REG_IMMEDIATE(r3, 0x0000000f)
|
||||
mtspr SPRN_MMUCR3,r3
|
||||
|
||||
/* Don't do ERAT stuff if running guest mode */
|
||||
mfmsr r3
|
||||
andis. r0,r3,MSR_GS@h
|
||||
bne 1f
|
||||
|
||||
/* Now set the I-ERAT watermark to 15 */
|
||||
lis r4,(MMUCR0_TLBSEL_I|MMUCR0_ECL)@h
|
||||
mtspr SPRN_MMUCR0, r4
|
||||
li r4,A2_IERAT_SIZE-1
|
||||
PPC_ERATWE(R4,R4,3)
|
||||
|
||||
/* Now set the D-ERAT watermark to 31 */
|
||||
lis r4,(MMUCR0_TLBSEL_D|MMUCR0_ECL)@h
|
||||
mtspr SPRN_MMUCR0, r4
|
||||
li r4,A2_DERAT_SIZE-1
|
||||
PPC_ERATWE(R4,R4,3)
|
||||
|
||||
/* And invalidate the beast just in case. That won't get rid of
|
||||
* a bolted entry though it will be in LRU and so will go away eventually
|
||||
* but let's not bother for now
|
||||
*/
|
||||
PPC_ERATILX(0,0,R0)
|
||||
1:
|
||||
blr
|
||||
|
||||
_GLOBAL(__restore_cpu_a2)
|
||||
b __setup_cpu_a2
|
||||
@@ -56,6 +56,7 @@ _GLOBAL(__setup_cpu_power8)
|
||||
li r0,0
|
||||
mtspr SPRN_LPID,r0
|
||||
mfspr r3,SPRN_LPCR
|
||||
ori r3, r3, LPCR_PECEDH
|
||||
bl __init_LPCR
|
||||
bl __init_HFSCR
|
||||
bl __init_tlb_power8
|
||||
@@ -74,6 +75,7 @@ _GLOBAL(__restore_cpu_power8)
|
||||
li r0,0
|
||||
mtspr SPRN_LPID,r0
|
||||
mfspr r3,SPRN_LPCR
|
||||
ori r3, r3, LPCR_PECEDH
|
||||
bl __init_LPCR
|
||||
bl __init_HFSCR
|
||||
bl __init_tlb_power8
|
||||
|
||||
@@ -109,7 +109,8 @@ extern void __restore_cpu_e6500(void);
|
||||
PPC_FEATURE_PSERIES_PERFMON_COMPAT)
|
||||
#define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \
|
||||
PPC_FEATURE2_HTM_COMP | PPC_FEATURE2_DSCR | \
|
||||
PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR)
|
||||
PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \
|
||||
PPC_FEATURE2_VEC_CRYPTO)
|
||||
#define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
|
||||
PPC_FEATURE_TRUE_LE | \
|
||||
PPC_FEATURE_HAS_ALTIVEC_COMP)
|
||||
@@ -2148,44 +2149,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
}
|
||||
#endif /* CONFIG_PPC32 */
|
||||
#endif /* CONFIG_E500 */
|
||||
|
||||
#ifdef CONFIG_PPC_A2
|
||||
{ /* Standard A2 (>= DD2) + FPU core */
|
||||
.pvr_mask = 0xffff0000,
|
||||
.pvr_value = 0x00480000,
|
||||
.cpu_name = "A2 (>= DD2)",
|
||||
.cpu_features = CPU_FTRS_A2,
|
||||
.cpu_user_features = COMMON_USER_PPC64,
|
||||
.mmu_features = MMU_FTRS_A2,
|
||||
.icache_bsize = 64,
|
||||
.dcache_bsize = 64,
|
||||
.num_pmcs = 0,
|
||||
.cpu_setup = __setup_cpu_a2,
|
||||
.cpu_restore = __restore_cpu_a2,
|
||||
.machine_check = machine_check_generic,
|
||||
.platform = "ppca2",
|
||||
},
|
||||
{ /* This is a default entry to get going, to be replaced by
|
||||
* a real one at some stage
|
||||
*/
|
||||
#define CPU_FTRS_BASE_BOOK3E (CPU_FTR_USE_TB | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
|
||||
CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
|
||||
.pvr_mask = 0x00000000,
|
||||
.pvr_value = 0x00000000,
|
||||
.cpu_name = "Book3E",
|
||||
.cpu_features = CPU_FTRS_BASE_BOOK3E,
|
||||
.cpu_user_features = COMMON_USER_PPC64,
|
||||
.mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
|
||||
MMU_FTR_USE_TLBIVAX_BCAST |
|
||||
MMU_FTR_LOCK_BCAST_INVAL,
|
||||
.icache_bsize = 64,
|
||||
.dcache_bsize = 64,
|
||||
.num_pmcs = 0,
|
||||
.machine_check = machine_check_generic,
|
||||
.platform = "power6",
|
||||
},
|
||||
#endif /* CONFIG_PPC_A2 */
|
||||
};
|
||||
|
||||
static struct cpu_spec the_cpu_spec;
|
||||
|
||||
@@ -330,8 +330,8 @@ static int eeh_phb_check_failure(struct eeh_pe *pe)
|
||||
eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED);
|
||||
eeh_serialize_unlock(flags);
|
||||
|
||||
pr_err("EEH: PHB#%x failure detected\n",
|
||||
phb_pe->phb->global_number);
|
||||
pr_err("EEH: PHB#%x failure detected, location: %s\n",
|
||||
phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
|
||||
dump_stack();
|
||||
eeh_send_failure_event(phb_pe);
|
||||
|
||||
@@ -358,10 +358,11 @@ out:
|
||||
int eeh_dev_check_failure(struct eeh_dev *edev)
|
||||
{
|
||||
int ret;
|
||||
int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
|
||||
unsigned long flags;
|
||||
struct device_node *dn;
|
||||
struct pci_dev *dev;
|
||||
struct eeh_pe *pe;
|
||||
struct eeh_pe *pe, *parent_pe, *phb_pe;
|
||||
int rc = 0;
|
||||
const char *location;
|
||||
|
||||
@@ -439,14 +440,34 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
|
||||
*/
|
||||
if ((ret < 0) ||
|
||||
(ret == EEH_STATE_NOT_SUPPORT) ||
|
||||
(ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) ==
|
||||
(EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) {
|
||||
((ret & active_flags) == active_flags)) {
|
||||
eeh_stats.false_positives++;
|
||||
pe->false_positives++;
|
||||
rc = 0;
|
||||
goto dn_unlock;
|
||||
}
|
||||
|
||||
/*
|
||||
* It should be corner case that the parent PE has been
|
||||
* put into frozen state as well. We should take care
|
||||
* that at first.
|
||||
*/
|
||||
parent_pe = pe->parent;
|
||||
while (parent_pe) {
|
||||
/* Hit the ceiling ? */
|
||||
if (parent_pe->type & EEH_PE_PHB)
|
||||
break;
|
||||
|
||||
/* Frozen parent PE ? */
|
||||
ret = eeh_ops->get_state(parent_pe, NULL);
|
||||
if (ret > 0 &&
|
||||
(ret & active_flags) != active_flags)
|
||||
pe = parent_pe;
|
||||
|
||||
/* Next parent level */
|
||||
parent_pe = parent_pe->parent;
|
||||
}
|
||||
|
||||
eeh_stats.slot_resets++;
|
||||
|
||||
/* Avoid repeated reports of this failure, including problems
|
||||
@@ -460,8 +481,11 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
|
||||
* a stack trace will help the device-driver authors figure
|
||||
* out what happened. So print that out.
|
||||
*/
|
||||
pr_err("EEH: Frozen PE#%x detected on PHB#%x\n",
|
||||
pe->addr, pe->phb->global_number);
|
||||
phb_pe = eeh_phb_pe_get(pe->phb);
|
||||
pr_err("EEH: Frozen PHB#%x-PE#%x detected\n",
|
||||
pe->phb->global_number, pe->addr);
|
||||
pr_err("EEH: PE location: %s, PHB location: %s\n",
|
||||
eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe));
|
||||
dump_stack();
|
||||
|
||||
eeh_send_failure_event(pe);
|
||||
|
||||
@@ -447,8 +447,9 @@ static void *eeh_pe_detach_dev(void *data, void *userdata)
|
||||
* PE reset (for 3 times), we try to clear the frozen state
|
||||
* for 3 times as well.
|
||||
*/
|
||||
static int eeh_clear_pe_frozen_state(struct eeh_pe *pe)
|
||||
static void *__eeh_clear_pe_frozen_state(void *data, void *flag)
|
||||
{
|
||||
struct eeh_pe *pe = (struct eeh_pe *)data;
|
||||
int i, rc;
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
@@ -461,13 +462,24 @@ static int eeh_clear_pe_frozen_state(struct eeh_pe *pe)
|
||||
}
|
||||
|
||||
/* The PE has been isolated, clear it */
|
||||
if (rc)
|
||||
if (rc) {
|
||||
pr_warn("%s: Can't clear frozen PHB#%x-PE#%x (%d)\n",
|
||||
__func__, pe->phb->global_number, pe->addr, rc);
|
||||
else
|
||||
return (void *)pe;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int eeh_clear_pe_frozen_state(struct eeh_pe *pe)
|
||||
{
|
||||
void *rc;
|
||||
|
||||
rc = eeh_pe_traverse(pe, __eeh_clear_pe_frozen_state, NULL);
|
||||
if (!rc)
|
||||
eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
|
||||
|
||||
return rc;
|
||||
return rc ? -EIO : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -758,7 +770,7 @@ static void eeh_handle_special_event(void)
|
||||
eeh_serialize_lock(&flags);
|
||||
|
||||
/* Purge all events */
|
||||
eeh_remove_event(NULL);
|
||||
eeh_remove_event(NULL, true);
|
||||
|
||||
list_for_each_entry(hose, &hose_list, list_node) {
|
||||
phb_pe = eeh_phb_pe_get(hose);
|
||||
@@ -777,7 +789,7 @@ static void eeh_handle_special_event(void)
|
||||
eeh_serialize_lock(&flags);
|
||||
|
||||
/* Purge all events of the PHB */
|
||||
eeh_remove_event(pe);
|
||||
eeh_remove_event(pe, true);
|
||||
|
||||
if (rc == EEH_NEXT_ERR_DEAD_PHB)
|
||||
eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
|
||||
|
||||
@@ -152,24 +152,33 @@ int eeh_send_failure_event(struct eeh_pe *pe)
|
||||
/**
|
||||
* eeh_remove_event - Remove EEH event from the queue
|
||||
* @pe: Event binding to the PE
|
||||
* @force: Event will be removed unconditionally
|
||||
*
|
||||
* On PowerNV platform, we might have subsequent coming events
|
||||
* is part of the former one. For that case, those subsequent
|
||||
* coming events are totally duplicated and unnecessary, thus
|
||||
* they should be removed.
|
||||
*/
|
||||
void eeh_remove_event(struct eeh_pe *pe)
|
||||
void eeh_remove_event(struct eeh_pe *pe, bool force)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct eeh_event *event, *tmp;
|
||||
|
||||
/*
|
||||
* If we have NULL PE passed in, we have dead IOC
|
||||
* or we're sure we can report all existing errors
|
||||
* by the caller.
|
||||
*
|
||||
* With "force", the event with associated PE that
|
||||
* have been isolated, the event won't be removed
|
||||
* to avoid event lost.
|
||||
*/
|
||||
spin_lock_irqsave(&eeh_eventlist_lock, flags);
|
||||
list_for_each_entry_safe(event, tmp, &eeh_eventlist, list) {
|
||||
/*
|
||||
* If we don't have valid PE passed in, that means
|
||||
* we already have event corresponding to dead IOC
|
||||
* and all events should be purged.
|
||||
*/
|
||||
if (!force && event->pe &&
|
||||
(event->pe->state & EEH_PE_ISOLATED))
|
||||
continue;
|
||||
|
||||
if (!pe) {
|
||||
list_del(&event->list);
|
||||
kfree(event);
|
||||
|
||||
@@ -791,6 +791,66 @@ void eeh_pe_restore_bars(struct eeh_pe *pe)
|
||||
eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
|
||||
}
|
||||
|
||||
/**
|
||||
* eeh_pe_loc_get - Retrieve location code binding to the given PE
|
||||
* @pe: EEH PE
|
||||
*
|
||||
* Retrieve the location code of the given PE. If the primary PE bus
|
||||
* is root bus, we will grab location code from PHB device tree node
|
||||
* or root port. Otherwise, the upstream bridge's device tree node
|
||||
* of the primary PE bus will be checked for the location code.
|
||||
*/
|
||||
const char *eeh_pe_loc_get(struct eeh_pe *pe)
|
||||
{
|
||||
struct pci_controller *hose;
|
||||
struct pci_bus *bus = eeh_pe_bus_get(pe);
|
||||
struct pci_dev *pdev;
|
||||
struct device_node *dn;
|
||||
const char *loc;
|
||||
|
||||
if (!bus)
|
||||
return "N/A";
|
||||
|
||||
/* PHB PE or root PE ? */
|
||||
if (pci_is_root_bus(bus)) {
|
||||
hose = pci_bus_to_host(bus);
|
||||
loc = of_get_property(hose->dn,
|
||||
"ibm,loc-code", NULL);
|
||||
if (loc)
|
||||
return loc;
|
||||
loc = of_get_property(hose->dn,
|
||||
"ibm,io-base-loc-code", NULL);
|
||||
if (loc)
|
||||
return loc;
|
||||
|
||||
pdev = pci_get_slot(bus, 0x0);
|
||||
} else {
|
||||
pdev = bus->self;
|
||||
}
|
||||
|
||||
if (!pdev) {
|
||||
loc = "N/A";
|
||||
goto out;
|
||||
}
|
||||
|
||||
dn = pci_device_to_OF_node(pdev);
|
||||
if (!dn) {
|
||||
loc = "N/A";
|
||||
goto out;
|
||||
}
|
||||
|
||||
loc = of_get_property(dn, "ibm,loc-code", NULL);
|
||||
if (!loc)
|
||||
loc = of_get_property(dn, "ibm,slot-location-code", NULL);
|
||||
if (!loc)
|
||||
loc = "N/A";
|
||||
|
||||
out:
|
||||
if (pci_is_root_bus(bus) && pdev)
|
||||
pci_dev_put(pdev);
|
||||
return loc;
|
||||
}
|
||||
|
||||
/**
|
||||
* eeh_pe_bus_get - Retrieve PCI bus according to the given PE
|
||||
* @pe: EEH PE
|
||||
|
||||
@@ -428,12 +428,6 @@ BEGIN_FTR_SECTION
|
||||
std r24,THREAD_VRSAVE(r3)
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
||||
#endif /* CONFIG_ALTIVEC */
|
||||
#ifdef CONFIG_PPC64
|
||||
BEGIN_FTR_SECTION
|
||||
mfspr r25,SPRN_DSCR
|
||||
std r25,THREAD_DSCR(r3)
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
|
||||
#endif
|
||||
and. r0,r0,r22
|
||||
beq+ 1f
|
||||
andc r22,r22,r0
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user