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s2io, rename BIT macro
s2io, rename BIT macro BIT macro will be global definiton of (1<<x) Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Cc: Ramkrishna Vepa <ram.vepa@neterion.com> Cc: Rastapur Santosh <santosh.rastapur@neterion.com> Cc: Sivakumar Subramani <sivakumar.subramani@neterion.com> Cc: Sreenivasa Honnur <sreenivasa.honnur@neterion.com> Cc: Jeff Garzik <jeff@garzik.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Jiri Slaby
committed by
Linus Torvalds
Linus Torvalds
parent
ed11399da5
commit
b7b5a1282c
+316
-316
File diff suppressed because it is too large
Load Diff
+8
-8
@@ -1716,7 +1716,7 @@ static int init_nic(struct s2io_nic *nic)
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MISC_LINK_STABILITY_PRD(3);
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writeq(val64, &bar0->misc_control);
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val64 = readq(&bar0->pic_control2);
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val64 &= ~(BIT(13)|BIT(14)|BIT(15));
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val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
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writeq(val64, &bar0->pic_control2);
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}
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if (strstr(nic->product_name, "CX4")) {
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@@ -2427,7 +2427,7 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
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}
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if ((rxdp->Control_1 & RXD_OWN_XENA) &&
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((nic->rxd_mode == RXD_MODE_3B) &&
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(rxdp->Control_2 & BIT(0)))) {
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(rxdp->Control_2 & s2BIT(0)))) {
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mac_control->rings[ring_no].rx_curr_put_info.
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offset = off;
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goto end;
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@@ -2540,7 +2540,7 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
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rxdp->Control_2 |= SET_BUFFER2_SIZE_3
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(dev->mtu + 4);
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}
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rxdp->Control_2 |= BIT(0);
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rxdp->Control_2 |= s2BIT(0);
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}
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rxdp->Host_Control = (unsigned long) (skb);
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if (alloc_tab & ((1 << rxsync_frequency) - 1))
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@@ -3377,7 +3377,7 @@ static void s2io_reset(struct s2io_nic * sp)
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pci_write_config_dword(sp->pdev, 0x68, 0x7C);
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/* Clearing PCI_STATUS error reflected here */
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writeq(BIT(62), &bar0->txpic_int_reg);
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writeq(s2BIT(62), &bar0->txpic_int_reg);
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}
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/* Reset device statistics maintained by OS */
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@@ -3575,7 +3575,7 @@ static int wait_for_msix_trans(struct s2io_nic *nic, int i)
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do {
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val64 = readq(&bar0->xmsi_access);
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if (!(val64 & BIT(15)))
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if (!(val64 & s2BIT(15)))
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break;
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mdelay(1);
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cnt++;
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@@ -3597,7 +3597,7 @@ static void restore_xmsi_data(struct s2io_nic *nic)
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for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
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writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
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writeq(nic->msix_info[i].data, &bar0->xmsi_data);
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val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
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val64 = (s2BIT(7) | s2BIT(15) | vBIT(i, 26, 6));
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writeq(val64, &bar0->xmsi_access);
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if (wait_for_msix_trans(nic, i)) {
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DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
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@@ -3614,7 +3614,7 @@ static void store_xmsi_data(struct s2io_nic *nic)
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/* Store and display */
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for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
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val64 = (BIT(15) | vBIT(i, 26, 6));
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val64 = (s2BIT(15) | vBIT(i, 26, 6));
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writeq(val64, &bar0->xmsi_access);
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if (wait_for_msix_trans(nic, i)) {
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DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
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@@ -4634,7 +4634,7 @@ static void s2io_updt_stats(struct s2io_nic *sp)
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do {
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udelay(100);
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val64 = readq(&bar0->stat_cfg);
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if (!(val64 & BIT(0)))
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if (!(val64 & s2BIT(0)))
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break;
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cnt++;
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if (cnt == 5)
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+42
-42
@@ -14,7 +14,7 @@
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#define _S2IO_H
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#define TBD 0
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#define BIT(loc) (0x8000000000000000ULL >> (loc))
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#define s2BIT(loc) (0x8000000000000000ULL >> (loc))
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#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
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#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
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@@ -473,42 +473,42 @@ struct TxFIFO_element {
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u64 List_Control;
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#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
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#define TX_FIFO_FIRST_LIST BIT(14)
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#define TX_FIFO_LAST_LIST BIT(15)
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#define TX_FIFO_FIRST_LIST s2BIT(14)
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#define TX_FIFO_LAST_LIST s2BIT(15)
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#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
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#define TX_FIFO_SPECIAL_FUNC BIT(23)
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#define TX_FIFO_DS_NO_SNOOP BIT(31)
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#define TX_FIFO_BUFF_NO_SNOOP BIT(30)
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#define TX_FIFO_SPECIAL_FUNC s2BIT(23)
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#define TX_FIFO_DS_NO_SNOOP s2BIT(31)
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#define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
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};
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/* Tx descriptor structure */
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struct TxD {
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u64 Control_1;
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/* bit mask */
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#define TXD_LIST_OWN_XENA BIT(7)
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#define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
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#define TXD_LIST_OWN_XENA s2BIT(7)
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#define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
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#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
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#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
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#define TXD_GATHER_CODE (BIT(22) | BIT(23))
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#define TXD_GATHER_CODE_FIRST BIT(22)
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#define TXD_GATHER_CODE_LAST BIT(23)
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#define TXD_TCP_LSO_EN BIT(30)
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#define TXD_UDP_COF_EN BIT(31)
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#define TXD_UFO_EN BIT(31) | BIT(30)
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#define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
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#define TXD_GATHER_CODE_FIRST s2BIT(22)
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#define TXD_GATHER_CODE_LAST s2BIT(23)
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#define TXD_TCP_LSO_EN s2BIT(30)
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#define TXD_UDP_COF_EN s2BIT(31)
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#define TXD_UFO_EN s2BIT(31) | s2BIT(30)
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#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
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#define TXD_UFO_MSS(val) vBIT(val,34,14)
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#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
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u64 Control_2;
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#define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
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#define TXD_TX_CKO_IPV4_EN BIT(5)
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#define TXD_TX_CKO_TCP_EN BIT(6)
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#define TXD_TX_CKO_UDP_EN BIT(7)
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#define TXD_VLAN_ENABLE BIT(15)
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#define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
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#define TXD_TX_CKO_IPV4_EN s2BIT(5)
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#define TXD_TX_CKO_TCP_EN s2BIT(6)
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#define TXD_TX_CKO_UDP_EN s2BIT(7)
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#define TXD_VLAN_ENABLE s2BIT(15)
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#define TXD_VLAN_TAG(val) vBIT(val,16,16)
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#define TXD_INT_NUMBER(val) vBIT(val,34,6)
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#define TXD_INT_TYPE_PER_LIST BIT(47)
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#define TXD_INT_TYPE_UTILZ BIT(46)
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#define TXD_INT_TYPE_PER_LIST s2BIT(47)
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#define TXD_INT_TYPE_UTILZ s2BIT(46)
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#define TXD_SET_MARKER vBIT(0x6,0,4)
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u64 Buffer_Pointer;
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@@ -525,14 +525,14 @@ struct list_info_hold {
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struct RxD_t {
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u64 Host_Control; /* reserved for host */
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u64 Control_1;
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#define RXD_OWN_XENA BIT(7)
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#define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
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#define RXD_OWN_XENA s2BIT(7)
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#define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
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#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
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#define RXD_FRAME_PROTO_IPV4 BIT(27)
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#define RXD_FRAME_PROTO_IPV6 BIT(28)
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#define RXD_FRAME_IP_FRAG BIT(29)
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#define RXD_FRAME_PROTO_TCP BIT(30)
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#define RXD_FRAME_PROTO_UDP BIT(31)
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#define RXD_FRAME_PROTO_IPV4 s2BIT(27)
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#define RXD_FRAME_PROTO_IPV6 s2BIT(28)
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#define RXD_FRAME_IP_FRAG s2BIT(29)
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#define RXD_FRAME_PROTO_TCP s2BIT(30)
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#define RXD_FRAME_PROTO_UDP s2BIT(31)
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#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
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#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
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#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
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@@ -998,26 +998,26 @@ static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
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/* Interrupt masks for the general interrupt mask register */
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#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
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#define TXPIC_INT_M BIT(0)
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#define TXDMA_INT_M BIT(1)
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#define TXMAC_INT_M BIT(2)
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#define TXXGXS_INT_M BIT(3)
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#define TXTRAFFIC_INT_M BIT(8)
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#define PIC_RX_INT_M BIT(32)
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#define RXDMA_INT_M BIT(33)
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#define RXMAC_INT_M BIT(34)
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#define MC_INT_M BIT(35)
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#define RXXGXS_INT_M BIT(36)
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#define RXTRAFFIC_INT_M BIT(40)
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#define TXPIC_INT_M s2BIT(0)
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#define TXDMA_INT_M s2BIT(1)
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#define TXMAC_INT_M s2BIT(2)
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#define TXXGXS_INT_M s2BIT(3)
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#define TXTRAFFIC_INT_M s2BIT(8)
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#define PIC_RX_INT_M s2BIT(32)
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#define RXDMA_INT_M s2BIT(33)
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#define RXMAC_INT_M s2BIT(34)
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#define MC_INT_M s2BIT(35)
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#define RXXGXS_INT_M s2BIT(36)
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#define RXTRAFFIC_INT_M s2BIT(40)
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/* PIC level Interrupts TODO*/
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/* DMA level Inressupts */
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#define TXDMA_PFC_INT_M BIT(0)
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#define TXDMA_PCC_INT_M BIT(2)
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#define TXDMA_PFC_INT_M s2BIT(0)
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#define TXDMA_PCC_INT_M s2BIT(2)
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/* PFC block interrupts */
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#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
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#define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
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/* PCC block interrupts. */
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#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
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