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Merge tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

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power management changes for omap and imx

A significant part of the changes for these two platforms went into
power management, so they are split out into a separate branch.

* tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (65 commits)
  ARM: imx6: remove __CPUINIT annotation from v7_invalidate_l1
  ARM: imx6: fix v7_invalidate_l1 by adding I-Cache invalidation
  ARM: imx6q: resume PL310 only when CACHE_L2X0 defined
  ARM: imx6q: build pm code only when CONFIG_PM selected
  ARM: mx5: use generic irq chip pm interface for pm functions on
  ARM: omap: pass minimal SoC/board data for UART from dt
  arm/dts: Add minimal device tree support for omap2420 and omap2430
  omap-serial: Add minimal device tree support
  omap-serial: Use default clock speed (48Mhz) if not specified
  omap-serial: Get rid of all pdev->id usage
  ARM: OMAP2+: hwmod: Add a new flag to handle hwmods left enabled at init
  ARM: OMAP4: PRM: use PRCM interrupt handler
  ARM: OMAP3: pm: use prcm chain handler
  ARM: OMAP: hwmod: add support for selecting mpu_irq for each wakeup pad
  ARM: OMAP2+: mux: add support for PAD wakeup interrupts
  ARM: OMAP: PRCM: add suspend prepare / finish support
  ARM: OMAP: PRCM: add support for chain interrupt handler
  ARM: OMAP3/4: PRM: add functions to read pending IRQs, PRM barrier
  ARM: OMAP2+: hwmod: Add API to enable IO ring wakeup
  ARM: OMAP2+: mux: add wakeup-capable hwmod mux entries to dynamic list
  ...
This commit is contained in:
Linus Torvalds
2012-01-09 14:39:59 -08:00
parent 2ac9d7aacc 6d0a5636fb
commit b3c3752292
59 changed files with 3876 additions and 1185 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/serial/omap_serial.txt
+10
View File
@@ -0,0 +1,10 @@
OMAP UART controller
Required properties:
- compatible : should be "ti,omap2-uart" for OMAP2 controllers
- compatible : should be "ti,omap3-uart" for OMAP3 controllers
- compatible : should be "ti,omap4-uart" for OMAP4 controllers
- ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
Optional properties:
- clock-frequency : frequency of the clock input to the UART
arch/arm/boot/dts/omap2.dtsi
+67
View File
@@ -0,0 +1,67 @@
/*
* Device Tree Source for OMAP2 SoC
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
};
cpus {
cpu@0 {
compatible = "arm,arm1136jf-s";
};
};
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap2-mpu";
ti,hwmods = "mpu";
};
};
ocp {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main";
intc: interrupt-controller@1 {
compatible = "ti,omap2-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
uart1: serial@4806a000 {
compatible = "ti,omap2-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
};
uart2: serial@4806c000 {
compatible = "ti,omap2-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
};
uart3: serial@4806e000 {
compatible = "ti,omap2-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
};
};
};
arch/arm/boot/dts/omap3.dtsi
+31
View File
@@ -13,6 +13,13 @@
/ {
compatible = "ti,omap3430", "ti,omap3";
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
};
cpus {
cpu@0 {
compatible = "arm,cortex-a8";
@@ -59,5 +66,29 @@
interrupt-controller;
#interrupt-cells = <1>;
};
uart1: serial@0x4806a000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
};
uart2: serial@0x4806c000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
};
uart3: serial@0x49020000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
};
uart4: serial@0x49042000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
};
};
};
arch/arm/boot/dts/omap4.dtsi
+28
View File
@@ -21,6 +21,10 @@
interrupt-parent = <&gic>;
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
};
cpus {
@@ -99,5 +103,29 @@
reg = <0x48241000 0x1000>,
<0x48240100 0x0100>;
};
uart1: serial@0x4806a000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
};
uart2: serial@0x4806c000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
};
uart3: serial@0x48020000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
};
uart4: serial@0x4806e000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
};
};
};
arch/arm/mach-imx/Kconfig
+1
View File
@@ -596,6 +596,7 @@ comment "i.MX6 family:"
config SOC_IMX6Q
bool "i.MX6 Quad support"
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select CPU_V7
select HAVE_ARM_SCU
arch/arm/mach-imx/Makefile
+5 -1
View File
@@ -70,4 +70,8 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
endif
arch/arm/mach-imx/head-v7.S
+12 -5
View File
@@ -16,7 +16,6 @@
#include <asm/hardware/cache-l2x0.h>
.section ".text.head", "ax"
__CPUINIT
/*
* The secondary kernel init calls v7_flush_dcache_all before it enables
@@ -33,6 +32,7 @@
*/
ENTRY(v7_invalidate_l1)
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mcr p15, 2, r0, c0, c0, 0
mrc p15, 1, r0, c0, c0, 0
@@ -71,6 +71,7 @@ ENTRY(v7_secondary_startup)
ENDPROC(v7_secondary_startup)
#endif
#ifdef CONFIG_PM
/*
* The following code is located into the .data section. This is to
* allow phys_l2x0_saved_regs to be accessed with a relative load
@@ -79,6 +80,7 @@ ENDPROC(v7_secondary_startup)
.data
.align
#ifdef CONFIG_CACHE_L2X0
.macro pl310_resume
ldr r2, phys_l2x0_saved_regs
ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0
@@ -88,12 +90,17 @@ ENDPROC(v7_secondary_startup)
str r1, [r0, #L2X0_CTRL] @ re-enable L2
.endm
.globl phys_l2x0_saved_regs
phys_l2x0_saved_regs:
.long 0
#else
.macro pl310_resume
.endm
#endif
ENTRY(v7_cpu_resume)
bl v7_invalidate_l1
pl310_resume
b cpu_resume
ENDPROC(v7_cpu_resume)
.globl phys_l2x0_saved_regs
phys_l2x0_saved_regs:
.long 0
#endif
arch/arm/mach-imx/pm-imx6q.c
+2
View File
@@ -64,7 +64,9 @@ void __init imx6q_pm_init(void)
* address of the data structure used by l2x0 core to save registers,
* and later restore the necessary ones in imx6q resume entry.
*/
#ifdef CONFIG_CACHE_L2X0
phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
#endif
suspend_set_ops(&imx6q_pm_ops);
}
arch/arm/mach-mx5/mm.c
+18 -1
View File
@@ -13,6 +13,7 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <asm/mach/map.h>
@@ -21,10 +22,26 @@
#include <mach/devices-common.h>
#include <mach/iomux-v3.h>
static struct clk *gpc_dvfs_clk;
static void imx5_idle(void)
{
if (!need_resched())
if (!need_resched()) {
/* gpc clock is needed for SRPG */
if (gpc_dvfs_clk == NULL) {
gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
if (IS_ERR(gpc_dvfs_clk))
goto err0;
}
clk_enable(gpc_dvfs_clk);
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
if (tzic_enable_wake())
goto err1;
cpu_do_idle();
err1:
clk_disable(gpc_dvfs_clk);
}
err0:
local_irq_enable();
}
arch/arm/mach-mx5/system.c
-3
View File
@@ -55,9 +55,6 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
stop_mode = 1;
}
arm_srpgcr |= MXC_SRPGCR_PCR;
if (tzic_enable_wake(1) != 0)
return;
break;
case STOP_POWER_ON:
ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
arch/arm/mach-omap2/Kconfig
+21
View File
@@ -365,6 +365,27 @@ config OMAP3_SDRC_AC_TIMING
wish to say no. Selecting yes without understanding what is
going on could result in system crashes;
config OMAP4_ERRATA_I688
bool "OMAP4 errata: Async Bridge Corruption"
depends on ARCH_OMAP4
select ARCH_HAS_BARRIERS
help
If a data is stalled inside asynchronous bridge because of back
pressure, it may be accepted multiple times, creating pointer
misalignment that will corrupt next transfers on that data path
until next reset of the system (No recovery procedure once the
issue is hit, the path remains consistently broken). Async bridge
can be found on path between MPU to EMIF and MPU to L3 interconnect.
This situation can happen only when the idle is initiated by a
Master Request Disconnection (which is trigged by software when
executing WFI on CPU).
The work-around for this errata needs all the initiators connected
through async bridge must ensure that data path is properly drained
before issuing WFI. This condition will be met if one Strongly ordered
access is performed to the target right before executing the WFI.
In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
IO barrier ensure that there is no synchronisation loss on initiators
operating on both interconnect port simultaneously.
endmenu
endif
arch/arm/mach-omap2/Makefile
+12 -7
View File
@@ -11,10 +11,11 @@ hwmod-common = omap_hwmod.o \
omap_hwmod_common_data.o
clock-common = clock.o clock_common_data.o \
clkt_dpll.o clkt_clksel.o
secure-common = omap-smc.o omap-secure.o
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
@@ -24,11 +25,13 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o
obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o
obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o \
sleep44xx.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec)
AFLAGS_omap-smc.o :=-Wa,-march=armv7-a$(plus_sec)
AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec)
# Functions loaded to SRAM
obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
@@ -62,7 +65,8 @@ obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \
cpuidle34xx.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o \
cpuidle44xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
@@ -77,6 +81,7 @@ endif
endif
# PRCM
obj-y += prm_common.o
obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
vc3xxx_data.o vp3xxx_data.o
@@ -86,7 +91,7 @@ obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
cm44xx.o prcm_mpu44xx.o \
prminst44xx.o vc44xx_data.o \
vp44xx_data.o
vp44xx_data.o prm44xx.o
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
arch/arm/mach-omap2/board-3430sdp.c
+1 -99
View File
@@ -475,106 +475,8 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static struct omap_device_pad serial1_pads[] __initdata = {
/*
* Note that off output enable is an active low
* signal. So setting this means pin is a
* input enabled in off mode
*/
OMAP_MUX_STATIC("uart1_cts.uart1_cts",
OMAP_PIN_INPUT |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart1_rts.uart1_rts",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart1_rx.uart1_rx",
OMAP_PIN_INPUT |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart1_tx.uart1_tx",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
};
static struct omap_device_pad serial2_pads[] __initdata = {
OMAP_MUX_STATIC("uart2_cts.uart2_cts",
OMAP_PIN_INPUT_PULLUP |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rts.uart2_rts",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rx.uart2_rx",
OMAP_PIN_INPUT |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_tx.uart2_tx",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
};
static struct omap_device_pad serial3_pads[] __initdata = {
OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
OMAP_PIN_INPUT_PULLDOWN |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
OMAP_PIN_INPUT |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
};
static struct omap_board_data serial1_data __initdata = {
.id = 0,
.pads = serial1_pads,
.pads_cnt = ARRAY_SIZE(serial1_pads),
};
static struct omap_board_data serial2_data __initdata = {
.id = 1,
.pads = serial2_pads,
.pads_cnt = ARRAY_SIZE(serial2_pads),
};
static struct omap_board_data serial3_data __initdata = {
.id = 2,
.pads = serial3_pads,
.pads_cnt = ARRAY_SIZE(serial3_pads),
};
static inline void board_serial_init(void)
{
omap_serial_init_port(&serial1_data);
omap_serial_init_port(&serial2_data);
omap_serial_init_port(&serial3_data);
}
#else
#define board_mux NULL
static inline void board_serial_init(void)
{
omap_serial_init();
}
#endif
/*
@@ -711,7 +613,7 @@ static void __init omap_3430sdp_init(void)
else
gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
omap_ads7846_init(1, gpio_pendown, 310, NULL);
board_serial_init();
omap_serial_init();
omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
usb_musb_init(NULL);
board_smc91x_init();
arch/arm/mach-omap2/board-4430sdp.c
+1 -67
View File
@@ -844,74 +844,8 @@ static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static struct omap_device_pad serial2_pads[] __initdata = {
OMAP_MUX_STATIC("uart2_cts.uart2_cts",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rts.uart2_rts",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rx.uart2_rx",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_tx.uart2_tx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_device_pad serial3_pads[] __initdata = {
OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_device_pad serial4_pads[] __initdata = {
OMAP_MUX_STATIC("uart4_rx.uart4_rx",
OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart4_tx.uart4_tx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_board_data serial2_data __initdata = {
.id = 1,
.pads = serial2_pads,
.pads_cnt = ARRAY_SIZE(serial2_pads),
};
static struct omap_board_data serial3_data __initdata = {
.id = 2,
.pads = serial3_pads,
.pads_cnt = ARRAY_SIZE(serial3_pads),
};
static struct omap_board_data serial4_data __initdata = {
.id = 3,
.pads = serial4_pads,
.pads_cnt = ARRAY_SIZE(serial4_pads),
};
static inline void board_serial_init(void)
{
struct omap_board_data bdata;
bdata.flags = 0;
bdata.pads = NULL;
bdata.pads_cnt = 0;
bdata.id = 0;
/* pass dummy data for UART1 */
omap_serial_init_port(&bdata);
omap_serial_init_port(&serial2_data);
omap_serial_init_port(&serial3_data);
omap_serial_init_port(&serial4_data);
}
#else
#define board_mux NULL
static inline void board_serial_init(void)
{
omap_serial_init();
}
#endif
static void omap4_sdp4430_wifi_mux_init(void)
@@ -961,7 +895,7 @@ static void __init omap_4430sdp_init(void)
omap4_i2c_init();
omap_sfh7741prox_init();
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
board_serial_init();
omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap4_sdp4430_wifi_init();
omap4_twl6030_hsmmc_init(mmc);
arch/arm/mach-omap2/board-generic.c
-1
View File
@@ -69,7 +69,6 @@ static void __init omap_generic_init(void)
if (node)
irq_domain_add_simple(node, 0);
omap_serial_init();
omap_sdrc_init(NULL, NULL);
of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
arch/arm/mach-omap2/board-n8x0.c
+3 -3
View File
@@ -644,15 +644,15 @@ static inline void board_serial_init(void)
bdata.pads_cnt = 0;
bdata.id = 0;
omap_serial_init_port(&bdata);
omap_serial_init_port(&bdata, NULL);
bdata.id = 1;
omap_serial_init_port(&bdata);
omap_serial_init_port(&bdata, NULL);
bdata.id = 2;
bdata.pads = serial2_pads;
bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
omap_serial_init_port(&bdata);
omap_serial_init_port(&bdata, NULL);
}
#else
arch/arm/mach-omap2/board-omap4panda.c
+1 -67
View File
@@ -364,74 +364,8 @@ static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static struct omap_device_pad serial2_pads[] __initdata = {
OMAP_MUX_STATIC("uart2_cts.uart2_cts",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rts.uart2_rts",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rx.uart2_rx",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_tx.uart2_tx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_device_pad serial3_pads[] __initdata = {
OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_device_pad serial4_pads[] __initdata = {
OMAP_MUX_STATIC("uart4_rx.uart4_rx",
OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart4_tx.uart4_tx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_board_data serial2_data __initdata = {
.id = 1,
.pads = serial2_pads,
.pads_cnt = ARRAY_SIZE(serial2_pads),
};
static struct omap_board_data serial3_data __initdata = {
.id = 2,
.pads = serial3_pads,
.pads_cnt = ARRAY_SIZE(serial3_pads),
};
static struct omap_board_data serial4_data __initdata = {
.id = 3,
.pads = serial4_pads,
.pads_cnt = ARRAY_SIZE(serial4_pads),
};
static inline void board_serial_init(void)
{
struct omap_board_data bdata;
bdata.flags = 0;
bdata.pads = NULL;
bdata.pads_cnt = 0;
bdata.id = 0;
/* pass dummy data for UART1 */
omap_serial_init_port(&bdata);
omap_serial_init_port(&serial2_data);
omap_serial_init_port(&serial3_data);
omap_serial_init_port(&serial4_data);
}
#else
#define board_mux NULL
static inline void board_serial_init(void)
{
omap_serial_init();
}
#endif
/* Display DVI */
@@ -562,7 +496,7 @@ static void __init omap4_panda_init(void)
omap4_panda_i2c_init();
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
platform_device_register(&omap_vwlan_device);
board_serial_init();
omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap4_twl6030_hsmmc_init(mmc);
omap4_ehci_init();
arch/arm/mach-omap2/common.h
+53 -11
View File
@@ -24,9 +24,11 @@
#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
#ifndef __ASSEMBLER__
#include <linux/delay.h>
#include <plat/common.h>
#include <asm/proc-fns.h>
#ifdef CONFIG_SOC_OMAP2420
extern void omap242x_map_common_io(void);
@@ -168,23 +170,23 @@ void omap3_intc_resume_idle(void);
void omap2_intc_handle_irq(struct pt_regs *regs);
void omap3_intc_handle_irq(struct pt_regs *regs);
/*
* wfi used in low power code. Directly opcode is used instead
* of instruction to avoid mulit-omap build break
*/
#ifdef CONFIG_THUMB2_KERNEL
#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
#else
#define do_wfi() \
__asm__ __volatile__ (".word 0xe320f003" : : : "memory")
#ifdef CONFIG_CACHE_L2X0
extern void __iomem *omap4_get_l2cache_base(void);
#endif
#ifdef CONFIG_CACHE_L2X0
extern void __iomem *l2cache_base;
#ifdef CONFIG_SMP
extern void __iomem *omap4_get_scu_base(void);
#else
static inline void __iomem *omap4_get_scu_base(void)
{
return NULL;
}
#endif
extern void __init gic_init_irq(void);
extern void omap_smc1(u32 fn, u32 arg);
extern void __iomem *omap4_get_sar_ram_base(void);
extern void omap_do_wfi(void);
#ifdef CONFIG_SMP
/* Needed for secondary core boot */
@@ -194,4 +196,44 @@ extern void omap_auxcoreboot_addr(u32 cpu_addr);
extern u32 omap_read_auxcoreboot0(void);
#endif
#if defined(CONFIG_SMP) && defined(CONFIG_PM)
extern int omap4_mpuss_init(void);
extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
extern int omap4_finish_suspend(unsigned long cpu_state);
extern void omap4_cpu_resume(void);
extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
extern u32 omap4_mpuss_read_prev_context_state(void);
#else
static inline int omap4_enter_lowpower(unsigned int cpu,
unsigned int power_state)
{
cpu_do_idle();
return 0;
}
static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
cpu_do_idle();
return 0;
}
static inline int omap4_mpuss_init(void)
{
return 0;
}
static inline int omap4_finish_suspend(unsigned long cpu_state)
{
return 0;
}
static inline void omap4_cpu_resume(void)
{}
static inline u32 omap4_mpuss_read_prev_context_state(void)
{
return 0;
}
#endif
#endif /* __ASSEMBLER__ */
#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
arch/arm/mach-omap2/cpuidle34xx.c
+15 -6
View File
@@ -25,12 +25,12 @@
#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
#include <linux/cpu_pm.h>
#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/serial.h>
#include "pm.h"
#include "control.h"
@@ -124,9 +124,23 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
}
/*
* Call idle CPU PM enter notifier chain so that
* VFP context is saved.
*/
if (mpu_state == PWRDM_POWER_OFF)
cpu_pm_enter();
/* Execute ARM wfi */
omap_sram_idle();
/*
* Call idle CPU PM enter notifier chain to restore
* VFP context.
*/
if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
cpu_pm_exit();
/* Re-allow idle for C1 */
if (index == 0) {
pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
@@ -245,11 +259,6 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
struct omap3_idle_statedata *cx;
int ret;
if (!omap3_can_sleep()) {
new_state_idx = drv->safe_state_index;
goto select_state;
}
/*
* Prevent idle completely if CAM is active.
* CAM does not have wakeup capability in OMAP3.
arch/arm/mach-omap2/cpuidle44xx.c
+245
View File
@@ -0,0 +1,245 @@
/*
* OMAP4 CPU idle Routines
*
* Copyright (C) 2011 Texas Instruments, Inc.
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Rajendra Nayak <rnayak@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/export.h>
#include <linux/clockchips.h>
#include <asm/proc-fns.h>
#include "common.h"
#include "pm.h"
#include "prm.h"
#ifdef CONFIG_CPU_IDLE
/* Machine specific information to be recorded in the C-state driver_data */
struct omap4_idle_statedata {
u32 cpu_state;
u32 mpu_logic_state;
u32 mpu_state;
u8 valid;
};
static struct cpuidle_params cpuidle_params_table[] = {
/* C1 - CPU0 ON + CPU1 ON + MPU ON */
{.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
/* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
{.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
{.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
};
#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
/**
* omap4_enter_idle - Programs OMAP4 to enter the specified state
* @dev: cpuidle device
* @drv: cpuidle driver
* @index: the index of state to be entered
*
* Called from the CPUidle framework to program the device to the
* specified low power state selected by the governor.
* Returns the amount of time spent in the low power state.
*/
static int omap4_enter_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
struct omap4_idle_statedata *cx =
cpuidle_get_statedata(&dev->states_usage[index]);
struct timespec ts_preidle, ts_postidle, ts_idle;
u32 cpu1_state;
int idle_time;
int new_state_idx;
int cpu_id = smp_processor_id();
/* Used to keep track of the total time in idle */
getnstimeofday(&ts_preidle);
local_irq_disable();
local_fiq_disable();
/*
* CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
* This is necessary to honour hardware recommondation
* of triggeing all the possible low power modes once CPU1 is
* out of coherency and in OFF mode.
* Update dev->last_state so that governor stats reflects right
* data.
*/
cpu1_state = pwrdm_read_pwrst(cpu1_pd);
if (cpu1_state != PWRDM_POWER_OFF) {
new_state_idx = drv->safe_state_index;
cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
}
if (index > 0)
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
/*
* Call idle CPU PM enter notifier chain so that
* VFP and per CPU interrupt context is saved.
*/
if (cx->cpu_state == PWRDM_POWER_OFF)
cpu_pm_enter();
pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
/*
* Call idle CPU cluster PM enter notifier chain
* to save GIC and wakeupgen context.
*/
if ((cx->mpu_state == PWRDM_POWER_RET) &&
(cx->mpu_logic_state == PWRDM_POWER_OFF))
cpu_cluster_pm_enter();
omap4_enter_lowpower(dev->cpu, cx->cpu_state);
/*
* Call idle CPU PM exit notifier chain to restore
* VFP and per CPU IRQ context. Only CPU0 state is
* considered since CPU1 is managed by CPU hotplug.
*/
if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
cpu_pm_exit();
/*
* Call idle CPU cluster PM exit notifier chain
* to restore GIC and wakeupgen context.
*/
if (omap4_mpuss_read_prev_context_state())
cpu_cluster_pm_exit();
if (index > 0)
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
getnstimeofday(&ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
local_irq_enable();
local_fiq_enable();
idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
USEC_PER_SEC;
/* Update cpuidle counters */
dev->last_residency = idle_time;
return index;
}
DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
struct cpuidle_driver omap4_idle_driver = {
.name = "omap4_idle",
.owner = THIS_MODULE,
};
static inline void _fill_cstate(struct cpuidle_driver *drv,
int idx, const char *descr)
{
struct cpuidle_state *state = &drv->states[idx];
state->exit_latency = cpuidle_params_table[idx].exit_latency;
state->target_residency = cpuidle_params_table[idx].target_residency;
state->flags = CPUIDLE_FLAG_TIME_VALID;
state->enter = omap4_enter_idle;
sprintf(state->name, "C%d", idx + 1);
strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
}
static inline struct omap4_idle_statedata *_fill_cstate_usage(
struct cpuidle_device *dev,
int idx)
{
struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
cx->valid = cpuidle_params_table[idx].valid;
cpuidle_set_statedata(state_usage, cx);
return cx;
}
/**
* omap4_idle_init - Init routine for OMAP4 idle
*
* Registers the OMAP4 specific cpuidle driver to the cpuidle
* framework with the valid set of states.
*/
int __init omap4_idle_init(void)
{
struct omap4_idle_statedata *cx;
struct cpuidle_device *dev;
struct cpuidle_driver *drv = &omap4_idle_driver;
unsigned int cpu_id = 0;
mpu_pd = pwrdm_lookup("mpu_pwrdm");
cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
return -ENODEV;
drv->safe_state_index = -1;
dev = &per_cpu(omap4_idle_dev, cpu_id);
dev->cpu = cpu_id;
/* C1 - CPU0 ON + CPU1 ON + MPU ON */
_fill_cstate(drv, 0, "MPUSS ON");
drv->safe_state_index = 0;
cx = _fill_cstate_usage(dev, 0);
cx->valid = 1; /* C1 is always valid */
cx->cpu_state = PWRDM_POWER_ON;
cx->mpu_state = PWRDM_POWER_ON;
cx->mpu_logic_state = PWRDM_POWER_RET;
/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
_fill_cstate(drv, 1, "MPUSS CSWR");
cx = _fill_cstate_usage(dev, 1);
cx->cpu_state = PWRDM_POWER_OFF;
cx->mpu_state = PWRDM_POWER_RET;
cx->mpu_logic_state = PWRDM_POWER_RET;
/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
_fill_cstate(drv, 2, "MPUSS OSWR");
cx = _fill_cstate_usage(dev, 2);
cx->cpu_state = PWRDM_POWER_OFF;
cx->mpu_state = PWRDM_POWER_RET;
cx->mpu_logic_state = PWRDM_POWER_OFF;
drv->state_count = OMAP4_NUM_STATES;
cpuidle_register_driver(&omap4_idle_driver);
dev->state_count = OMAP4_NUM_STATES;
if (cpuidle_register_device(dev)) {
pr_err("%s: CPUidle register device failed\n", __func__);
return -EIO;
}
return 0;
}
#else
int __init omap4_idle_init(void)
{
return 0;
}
#endif /* CONFIG_CPU_IDLE */

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