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Merge branch 'mti-next' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
This commit is contained in:
Ralf Baechle
@@ -11,6 +11,7 @@
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/tlbdebug.h>
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#include <asm/mmu_context.h>
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static inline const char *msk2str(unsigned int mask)
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{
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@@ -55,7 +56,7 @@ static void dump_tlb(int first, int last)
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s_pagemask = read_c0_pagemask();
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s_entryhi = read_c0_entryhi();
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s_index = read_c0_index();
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asid = s_entryhi & 0xff;
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asid = ASID_MASK(s_entryhi);
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for (i = first; i <= last; i++) {
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write_c0_index(i);
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@@ -85,7 +86,7 @@ static void dump_tlb(int first, int last)
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printk("va=%0*lx asid=%02lx\n",
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width, (entryhi & ~0x1fffUL),
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entryhi & 0xff);
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ASID_MASK(entryhi));
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printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
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width,
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(entrylo0 << 6) & PAGE_MASK, c0,
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+54
-30
@@ -5,7 +5,8 @@
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*
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* Copyright (C) 1998, 1999, 2000 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2007 Maciej W. Rozycki
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* Copyright (C) 2007 by Maciej W. Rozycki
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* Copyright (C) 2011, 2012 MIPS Technologies, Inc.
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*/
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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@@ -19,6 +20,20 @@
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#define LONG_S_R sdr
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#endif
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#ifdef CONFIG_CPU_MICROMIPS
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#define STORSIZE (LONGSIZE * 2)
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#define STORMASK (STORSIZE - 1)
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#define FILL64RG t8
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#define FILLPTRG t7
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#undef LONG_S
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#define LONG_S LONG_SP
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#else
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#define STORSIZE LONGSIZE
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#define STORMASK LONGMASK
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#define FILL64RG a1
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#define FILLPTRG t0
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#endif
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#define EX(insn,reg,addr,handler) \
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9: insn reg, addr; \
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.section __ex_table,"a"; \
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@@ -26,23 +41,25 @@
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.previous
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.macro f_fill64 dst, offset, val, fixup
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EX(LONG_S, \val, (\offset + 0 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 1 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 2 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 3 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 4 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 5 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 6 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 7 * LONGSIZE)(\dst), \fixup)
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#if LONGSIZE == 4
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EX(LONG_S, \val, (\offset + 8 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 9 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 10 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 11 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 12 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 13 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 14 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 15 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup)
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#if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) || !defined(CONFIG_CPU_MICROMIPS))
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EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup)
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#endif
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#if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4))
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EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup)
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#endif
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.endm
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@@ -71,16 +88,20 @@ LEAF(memset)
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1:
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FEXPORT(__bzero)
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sltiu t0, a2, LONGSIZE /* very small region? */
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sltiu t0, a2, STORSIZE /* very small region? */
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bnez t0, .Lsmall_memset
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andi t0, a0, LONGMASK /* aligned? */
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andi t0, a0, STORMASK /* aligned? */
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#ifdef CONFIG_CPU_MICROMIPS
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move t8, a1 /* used by 'swp' instruction */
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move t9, a1
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#endif
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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beqz t0, 1f
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PTR_SUBU t0, LONGSIZE /* alignment in bytes */
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PTR_SUBU t0, STORSIZE /* alignment in bytes */
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#else
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.set noat
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li AT, LONGSIZE
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li AT, STORSIZE
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beqz t0, 1f
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PTR_SUBU t0, AT /* alignment in bytes */
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.set at
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@@ -99,24 +120,27 @@ FEXPORT(__bzero)
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1: ori t1, a2, 0x3f /* # of full blocks */
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xori t1, 0x3f
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beqz t1, .Lmemset_partial /* no block to fill */
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andi t0, a2, 0x40-LONGSIZE
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andi t0, a2, 0x40-STORSIZE
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PTR_ADDU t1, a0 /* end address */
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.set reorder
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1: PTR_ADDIU a0, 64
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R10KCBARRIER(0(ra))
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f_fill64 a0, -64, a1, .Lfwd_fixup
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f_fill64 a0, -64, FILL64RG, .Lfwd_fixup
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bne t1, a0, 1b
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.set noreorder
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.Lmemset_partial:
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R10KCBARRIER(0(ra))
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PTR_LA t1, 2f /* where to start */
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#ifdef CONFIG_CPU_MICROMIPS
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LONG_SRL t7, t0, 1
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#endif
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#if LONGSIZE == 4
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PTR_SUBU t1, t0
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PTR_SUBU t1, FILLPTRG
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#else
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.set noat
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LONG_SRL AT, t0, 1
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LONG_SRL AT, FILLPTRG, 1
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PTR_SUBU t1, AT
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.set at
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#endif
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@@ -126,9 +150,9 @@ FEXPORT(__bzero)
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.set push
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.set noreorder
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.set nomacro
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f_fill64 a0, -64, a1, .Lpartial_fixup /* ... but first do longs ... */
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f_fill64 a0, -64, FILL64RG, .Lpartial_fixup /* ... but first do longs ... */
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2: .set pop
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andi a2, LONGMASK /* At most one long to go */
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andi a2, STORMASK /* At most one long to go */
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beqz a2, 1f
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PTR_ADDU a0, a2 /* What's left */
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@@ -169,7 +193,7 @@ FEXPORT(__bzero)
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.Lpartial_fixup:
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PTR_L t0, TI_TASK($28)
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andi a2, LONGMASK
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andi a2, STORMASK
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, t1
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jr ra
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@@ -177,4 +201,4 @@ FEXPORT(__bzero)
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.Llast_fixup:
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jr ra
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andi v1, a2, LONGMASK
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andi v1, a2, STORMASK
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@@ -9,6 +9,7 @@
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#include <linux/mm.h>
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#include <asm/mipsregs.h>
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#include <asm/mmu_context.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/tlbdebug.h>
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@@ -21,7 +22,7 @@ static void dump_tlb(int first, int last)
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unsigned int asid;
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unsigned long entryhi, entrylo0;
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asid = read_c0_entryhi() & 0xfc0;
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asid = ASID_MASK(read_c0_entryhi());
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for (i = first; i <= last; i++) {
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write_c0_index(i<<8);
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@@ -35,7 +36,7 @@ static void dump_tlb(int first, int last)
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/* Unused entries have a virtual address of KSEG0. */
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if ((entryhi & 0xffffe000) != 0x80000000
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&& (entryhi & 0xfc0) == asid) {
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&& (ASID_MASK(entryhi) == asid)) {
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/*
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* Only print entries in use
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*/
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@@ -44,7 +45,7 @@ static void dump_tlb(int first, int last)
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printk("va=%08lx asid=%08lx"
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" [pa=%06lx n=%d d=%d v=%d g=%d]",
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(entryhi & 0xffffe000),
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entryhi & 0xfc0,
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ASID_MASK(entryhi),
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entrylo0 & PAGE_MASK,
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(entrylo0 & (1 << 11)) ? 1 : 0,
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(entrylo0 & (1 << 10)) ? 1 : 0,
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@@ -3,8 +3,9 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 1996, 1998, 1999, 2004 by Ralf Baechle
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* Copyright (c) 1999 Silicon Graphics, Inc.
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* Copyright (C) 1996, 1998, 1999, 2004 by Ralf Baechle
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) 2011 MIPS Technologies, Inc.
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*/
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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@@ -28,9 +29,9 @@ LEAF(__strlen_user_asm)
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FEXPORT(__strlen_user_nocheck_asm)
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move v0, a0
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1: EX(lb, t0, (v0), .Lfault)
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1: EX(lbu, v1, (v0), .Lfault)
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PTR_ADDIU v0, 1
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bnez t0, 1b
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bnez v1, 1b
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PTR_SUBU v0, a0
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jr ra
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END(__strlen_user_asm)
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@@ -3,7 +3,8 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 1996, 1999 by Ralf Baechle
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* Copyright (C) 1996, 1999 by Ralf Baechle
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* Copyright (C) 2011 MIPS Technologies, Inc.
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*/
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#include <linux/errno.h>
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#include <asm/asm.h>
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@@ -33,26 +34,27 @@ LEAF(__strncpy_from_user_asm)
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bnez v0, .Lfault
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FEXPORT(__strncpy_from_user_nocheck_asm)
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move v0, zero
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move v1, a1
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.set noreorder
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1: EX(lbu, t0, (v1), .Lfault)
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move t0, zero
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move v1, a1
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1: EX(lbu, v0, (v1), .Lfault)
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PTR_ADDIU v1, 1
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R10KCBARRIER(0(ra))
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beqz t0, 2f
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sb t0, (a0)
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PTR_ADDIU v0, 1
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.set reorder
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PTR_ADDIU a0, 1
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bne v0, a2, 1b
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2: PTR_ADDU t0, a1, v0
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xor t0, a1
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bltz t0, .Lfault
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beqz v0, 2f
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sb v0, (a0)
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PTR_ADDIU t0, 1
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bne t0, a2, 1b
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PTR_ADDIU a0, 1
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2: PTR_ADDU v0, a1, t0
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xor v0, a1
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bltz v0, .Lfault
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nop
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jr ra # return n
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move v0, t0
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END(__strncpy_from_user_asm)
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.Lfault: li v0, -EFAULT
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jr ra
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.Lfault: jr ra
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li v0, -EFAULT
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.section __ex_table,"a"
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PTR 1b, .Lfault
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@@ -35,7 +35,7 @@ FEXPORT(__strnlen_user_nocheck_asm)
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PTR_ADDU a1, a0 # stop pointer
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1: beq v0, a1, 1f # limit reached?
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EX(lb, t0, (v0), .Lfault)
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PTR_ADDU v0, 1
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PTR_ADDIU v0, 1
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bnez t0, 1b
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1: PTR_SUBU v0, a0
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jr ra
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