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[MIPS] Remove IT8172-based platforms, ITE 8172G and Globespan IVR support.
As per feature-removal-schedule.txt. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Acked-by: Alan Cox <alan@redhat.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Yoichi Yuasa
committed by
Ralf Baechle
Ralf Baechle
parent
08dfcee84c
commit
af8b128719
@@ -211,16 +211,6 @@ Who: Nick Piggin <npiggin@suse.de>
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---------------------------
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What: Support for the IT8172-based platforms, ITE 8172G and Globespan IVR
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When: September 2006
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Why: Code does no longer build since at least 2.6.0, apparently there is
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no user base left for these platforms. Hardware out of production
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since several years and hardly a trace of the manufacturer left on
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the net.
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Who: Ralf Baechle <ralf@linux-mips.org>
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---------------------------
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What: Interrupt only SA_* flags
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When: Januar 2007
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Why: The interrupt related SA_* flags are replaced by IRQF_* to move them
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@@ -203,39 +203,6 @@ config MIPS_EV64120
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<http://www.marvell.com/>. Say Y here if you wish to build a
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kernel for this platform.
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config MIPS_IVR
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bool "Globespan IVR board"
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select ITE_BOARD_GEN
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select SYS_HAS_CPU_NEVADA
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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help
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This is an evaluation board built by Globespan to showcase thir
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iVR (Internet Video Recorder) design. It utilizes a QED RM5231
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R5000 MIPS core. More information can be found out their website
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located at <http://www.globespan.net/>. Say Y here if you wish to
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build a kernel for this platform.
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config MIPS_ITE8172
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bool "ITE 8172G board"
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select ITE_BOARD_GEN
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select SYS_HAS_CPU_R5432
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select SYS_HAS_CPU_NEVADA
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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help
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Ths is an evaluation board made by ITE <http://www.ite.com.tw/>
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with ATX form factor that utilizes a MIPS R5000 to work with its
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ITE8172G companion internet appliance chip. The MIPS core can be
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either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
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a kernel for this platform.
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config MACH_JAZZ
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bool "Jazz family of machines"
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select ARC
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@@ -804,7 +771,6 @@ endchoice
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source "arch/mips/ddb5xxx/Kconfig"
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source "arch/mips/gt64120/ev64120/Kconfig"
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source "arch/mips/jazz/Kconfig"
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source "arch/mips/ite-boards/Kconfig"
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source "arch/mips/lasat/Kconfig"
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source "arch/mips/momentum/Kconfig"
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source "arch/mips/pmc-sierra/Kconfig"
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@@ -964,9 +930,6 @@ config MIPS_RM9122
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config PCI_MARVELL
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bool
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config ITE_BOARD_GEN
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bool
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config SOC_AU1000
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bool
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select SOC_AU1X00
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@@ -1050,16 +1013,6 @@ config AU1X00_USB_DEVICE
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depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
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default n
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config IT8172_CIR
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bool
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depends on MIPS_ITE8172 || MIPS_IVR
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default y
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config IT8712
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bool
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depends on MIPS_ITE8172
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default y
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config BOOT_ELF32
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bool
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@@ -286,19 +286,6 @@ core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/
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cflags-$(CONFIG_WR_PPMC) += -Iinclude/asm-mips/mach-wrppmc
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load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
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#
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# Globespan IVR eval board with QED 5231 CPU
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#
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core-$(CONFIG_ITE_BOARD_GEN) += arch/mips/ite-boards/generic/
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core-$(CONFIG_MIPS_IVR) += arch/mips/ite-boards/ivr/
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load-$(CONFIG_MIPS_IVR) += 0xffffffff80100000
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#
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# ITE 8172 eval board with QED 5231 CPU
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#
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core-$(CONFIG_MIPS_ITE8172) += arch/mips/ite-boards/qed-4n-s01b/
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load-$(CONFIG_MIPS_ITE8172) += 0xffffffff80100000
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#
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# For all MIPS, Inc. eval boards
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#
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,8 +0,0 @@
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config IT8172_REVC
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bool "Support for older IT8172 (Rev C)"
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depends on MIPS_ITE8172
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help
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Say Y here to support the older, Revision C version of the Integrated
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Technology Express, Inc. ITE8172 SBC. Vendor page at
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<http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
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board at <http://www.mvista.com/partners/semiconductor/ite.html>.
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@@ -1,15 +0,0 @@
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#
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# Copyright 2000 MontaVista Software Inc.
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# Author: MontaVista Software, Inc.
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# ppopov@mvista.com or source@mvista.com
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#
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# Makefile for the ITE 8172 (qed-4n-s01b) board, generic files.
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#
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obj-y += it8172_setup.o irq.o pmon_prom.o \
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time.o lpc.o puts.o reset.o
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obj-$(CONFIG_IT8172_CIR)+= it8172_cir.o
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obj-$(CONFIG_KGDB) += dbg_io.o
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EXTRA_AFLAGS := $(CFLAGS)
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@@ -1,124 +0,0 @@
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#ifdef CONFIG_KGDB
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/* --- CONFIG --- */
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/* we need uint32 uint8 */
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/* #include "types.h" */
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typedef unsigned char uint8;
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typedef unsigned int uint32;
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/* --- END OF CONFIG --- */
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#define UART16550_BAUD_2400 2400
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#define UART16550_BAUD_4800 4800
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#define UART16550_BAUD_9600 9600
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#define UART16550_BAUD_19200 19200
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#define UART16550_BAUD_38400 38400
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#define UART16550_BAUD_57600 57600
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#define UART16550_BAUD_115200 115200
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#define UART16550_PARITY_NONE 0
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#define UART16550_PARITY_ODD 0x08
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#define UART16550_PARITY_EVEN 0x18
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#define UART16550_PARITY_MARK 0x28
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#define UART16550_PARITY_SPACE 0x38
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#define UART16550_DATA_5BIT 0x0
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#define UART16550_DATA_6BIT 0x1
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#define UART16550_DATA_7BIT 0x2
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#define UART16550_DATA_8BIT 0x3
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#define UART16550_STOP_1BIT 0x0
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#define UART16550_STOP_2BIT 0x4
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/* ----------------------------------------------------- */
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/* === CONFIG === */
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/* [stevel] we use the IT8712 serial port for kgdb */
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#define DEBUG_BASE 0xB40003F8 /* 8712 serial port 1 base address */
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#define MAX_BAUD 115200
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/* === END OF CONFIG === */
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/* register offset */
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#define OFS_RCV_BUFFER 0
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#define OFS_TRANS_HOLD 0
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#define OFS_SEND_BUFFER 0
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#define OFS_INTR_ENABLE 1
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#define OFS_INTR_ID 2
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#define OFS_DATA_FORMAT 3
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#define OFS_LINE_CONTROL 3
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#define OFS_MODEM_CONTROL 4
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#define OFS_RS232_OUTPUT 4
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#define OFS_LINE_STATUS 5
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#define OFS_MODEM_STATUS 6
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#define OFS_RS232_INPUT 6
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#define OFS_SCRATCH_PAD 7
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#define OFS_DIVISOR_LSB 0
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#define OFS_DIVISOR_MSB 1
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/* memory-mapped read/write of the port */
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#define UART16550_READ(y) (*((volatile uint8*)(DEBUG_BASE + y)))
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#define UART16550_WRITE(y,z) ((*((volatile uint8*)(DEBUG_BASE + y))) = z)
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void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
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{
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/* disable interrupts */
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UART16550_WRITE(OFS_INTR_ENABLE, 0);
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/* set up baud rate */
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{
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uint32 divisor;
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/* set DIAB bit */
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UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
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/* set divisor */
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divisor = MAX_BAUD / baud;
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UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
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UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
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/* clear DIAB bit */
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UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
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}
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/* set data format */
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UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
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}
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static int remoteDebugInitialized = 0;
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uint8 getDebugChar(void)
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{
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if (!remoteDebugInitialized) {
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remoteDebugInitialized = 1;
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debugInit(UART16550_BAUD_115200,
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UART16550_DATA_8BIT,
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UART16550_PARITY_NONE, UART16550_STOP_1BIT);
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}
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while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
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return UART16550_READ(OFS_RCV_BUFFER);
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}
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int putDebugChar(uint8 byte)
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{
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if (!remoteDebugInitialized) {
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remoteDebugInitialized = 1;
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debugInit(UART16550_BAUD_115200,
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UART16550_DATA_8BIT,
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UART16550_PARITY_NONE, UART16550_STOP_1BIT);
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}
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while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
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UART16550_WRITE(OFS_SEND_BUFFER, byte);
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return 1;
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}
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#endif
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@@ -1,308 +0,0 @@
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/*
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* BRIEF MODULE DESCRIPTION
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* ITE 8172G interrupt/setup routines.
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*
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* Copyright 2000,2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* Part of this file was derived from Carsten Langgaard's
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* arch/mips/mips-boards/atlas/atlas_int.c.
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/serial_reg.h>
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#include <linux/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/it8172/it8172.h>
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#include <asm/it8172/it8172_int.h>
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#include <asm/it8172/it8172_dbg.h>
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/* revisit */
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#define EXT_IRQ0_TO_IP 2 /* IP 2 */
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#define EXT_IRQ5_TO_IP 7 /* IP 7 */
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#define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
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extern void set_debug_traps(void);
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extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
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struct it8172_intc_regs volatile *it8172_hw0_icregs =
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(struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
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static void disable_it8172_irq(unsigned int irq_nr)
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{
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if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
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/* LPC interrupt */
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it8172_hw0_icregs->lpc_mask |=
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(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
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} else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
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/* Local Bus interrupt */
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it8172_hw0_icregs->lb_mask |=
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(1 << (irq_nr - IT8172_LB_IRQ_BASE));
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} else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
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/* PCI and other interrupts */
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it8172_hw0_icregs->pci_mask |=
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(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
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} else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
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/* NMI interrupts */
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it8172_hw0_icregs->nmi_mask |=
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(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
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} else {
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panic("disable_it8172_irq: bad irq %d", irq_nr);
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}
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}
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static void enable_it8172_irq(unsigned int irq_nr)
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{
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if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
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/* LPC interrupt */
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it8172_hw0_icregs->lpc_mask &=
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~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
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}
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else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
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/* Local Bus interrupt */
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it8172_hw0_icregs->lb_mask &=
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~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
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}
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else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
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/* PCI and other interrupts */
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it8172_hw0_icregs->pci_mask &=
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~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
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}
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else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
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/* NMI interrupts */
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it8172_hw0_icregs->nmi_mask &=
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~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
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}
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else {
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panic("enable_it8172_irq: bad irq %d", irq_nr);
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}
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}
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static unsigned int startup_ite_irq(unsigned int irq)
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{
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enable_it8172_irq(irq);
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return 0;
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}
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#define shutdown_ite_irq disable_it8172_irq
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#define mask_and_ack_ite_irq disable_it8172_irq
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static void end_ite_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_it8172_irq(irq);
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}
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static struct irq_chip it8172_irq_type = {
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.typename = "ITE8172",
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.startup = startup_ite_irq,
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.shutdown = shutdown_ite_irq,
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.enable = enable_it8172_irq,
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.disable = disable_it8172_irq,
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.ack = mask_and_ack_ite_irq,
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.end = end_ite_irq,
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};
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static void enable_none(unsigned int irq) { }
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static unsigned int startup_none(unsigned int irq) { return 0; }
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static void disable_none(unsigned int irq) { }
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static void ack_none(unsigned int irq) { }
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/* startup is the same as "enable", shutdown is same as "disable" */
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#define shutdown_none disable_none
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#define end_none enable_none
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static struct irq_chip cp0_irq_type = {
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.typename = "CP0 Count",
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.startup = startup_none,
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.shutdown = shutdown_none,
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.enable = enable_none,
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.disable = disable_none,
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.ack = ack_none,
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.end = end_none
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};
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void enable_cpu_timer(void)
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{
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unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
set_c0_status(0x100 << EXT_IRQ5_TO_IP);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long flags;
|
||||
|
||||
/* mask all interrupts */
|
||||
it8172_hw0_icregs->lb_mask = 0xffff;
|
||||
it8172_hw0_icregs->lpc_mask = 0xffff;
|
||||
it8172_hw0_icregs->pci_mask = 0xffff;
|
||||
it8172_hw0_icregs->nmi_mask = 0xffff;
|
||||
|
||||
/* make all interrupts level triggered */
|
||||
it8172_hw0_icregs->lb_trigger = 0;
|
||||
it8172_hw0_icregs->lpc_trigger = 0;
|
||||
it8172_hw0_icregs->pci_trigger = 0;
|
||||
it8172_hw0_icregs->nmi_trigger = 0;
|
||||
|
||||
/* active level setting */
|
||||
/* uart, keyboard, and mouse are active high */
|
||||
it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
|
||||
it8172_hw0_icregs->lb_level |= 0x20;
|
||||
|
||||
/* keyboard and mouse are edge triggered */
|
||||
it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
|
||||
|
||||
|
||||
#if 0
|
||||
// Enable this piece of code to make internal USB interrupt
|
||||
// edge triggered.
|
||||
it8172_hw0_icregs->pci_trigger |=
|
||||
(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
|
||||
it8172_hw0_icregs->pci_level &=
|
||||
~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
|
||||
#endif
|
||||
|
||||
for (i = 0; i <= IT8172_LAST_IRQ; i++) {
|
||||
irq_desc[i].chip = &it8172_irq_type;
|
||||
spin_lock_init(&irq_desc[i].lock);
|
||||
}
|
||||
irq_desc[MIPS_CPU_TIMER_IRQ].chip = &cp0_irq_type;
|
||||
set_c0_status(ALLINTS_NOTIMER);
|
||||
}
|
||||
|
||||
void mips_spurious_interrupt(struct pt_regs *regs)
|
||||
{
|
||||
#if 1
|
||||
return;
|
||||
#else
|
||||
unsigned long status, cause;
|
||||
|
||||
printk("got spurious interrupt\n");
|
||||
status = read_c0_status();
|
||||
cause = read_c0_cause();
|
||||
printk("status %x cause %x\n", status, cause);
|
||||
printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr);
|
||||
#endif
|
||||
}
|
||||
|
||||
void it8172_hw0_irqdispatch(struct pt_regs *regs)
|
||||
{
|
||||
int irq;
|
||||
unsigned short intstatus = 0, status = 0;
|
||||
|
||||
intstatus = it8172_hw0_icregs->intstatus;
|
||||
if (intstatus & 0x8) {
|
||||
panic("Got NMI interrupt");
|
||||
} else if (intstatus & 0x4) {
|
||||
/* PCI interrupt */
|
||||
irq = 0;
|
||||
status |= it8172_hw0_icregs->pci_req;
|
||||
while (!(status & 0x1)) {
|
||||
irq++;
|
||||
status >>= 1;
|
||||
}
|
||||
irq += IT8172_PCI_DEV_IRQ_BASE;
|
||||
} else if (intstatus & 0x1) {
|
||||
/* Local Bus interrupt */
|
||||
irq = 0;
|
||||
status |= it8172_hw0_icregs->lb_req;
|
||||
while (!(status & 0x1)) {
|
||||
irq++;
|
||||
status >>= 1;
|
||||
}
|
||||
irq += IT8172_LB_IRQ_BASE;
|
||||
} else if (intstatus & 0x2) {
|
||||
/* LPC interrupt */
|
||||
/* Since some lpc interrupts are edge triggered,
|
||||
* we could lose an interrupt this way because
|
||||
* we acknowledge all ints at onces. Revisit.
|
||||
*/
|
||||
status |= it8172_hw0_icregs->lpc_req;
|
||||
it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */
|
||||
irq = 0;
|
||||
while (!(status & 0x1)) {
|
||||
irq++;
|
||||
status >>= 1;
|
||||
}
|
||||
irq += IT8172_LPC_IRQ_BASE;
|
||||
} else
|
||||
return;
|
||||
|
||||
do_IRQ(irq, regs);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
|
||||
if (!pending)
|
||||
mips_spurious_interrupt(regs);
|
||||
else if (pending & CAUSEF_IP7)
|
||||
ll_timer_interrupt(127, regs);
|
||||
else if (pending & CAUSEF_IP2)
|
||||
it8172_hw0_irqdispatch(regs);
|
||||
}
|
||||
|
||||
void show_pending_irqs(void)
|
||||
{
|
||||
fputs("intstatus: ");
|
||||
put32(it8172_hw0_icregs->intstatus);
|
||||
puts("");
|
||||
|
||||
fputs("pci_req: ");
|
||||
put32(it8172_hw0_icregs->pci_req);
|
||||
puts("");
|
||||
|
||||
fputs("lb_req: ");
|
||||
put32(it8172_hw0_icregs->lb_req);
|
||||
puts("");
|
||||
|
||||
fputs("lpc_req: ");
|
||||
put32(it8172_hw0_icregs->lpc_req);
|
||||
puts("");
|
||||
}
|
||||
@@ -1,170 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* IT8172 Consumer IR port generic routines.
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
|
||||
#ifdef CONFIG_IT8172_CIR
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/it8172/it8172.h>
|
||||
#include <asm/it8172/it8172_cir.h>
|
||||
|
||||
|
||||
volatile struct it8172_cir_regs *cir_regs[NUM_CIR_PORTS] = {
|
||||
(volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR0_BASE)),
|
||||
(volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR1_BASE))};
|
||||
|
||||
|
||||
/*
|
||||
* Initialize Consumer IR Port.
|
||||
*/
|
||||
int cir_port_init(struct cir_port *cir)
|
||||
{
|
||||
int port = cir->port;
|
||||
unsigned char data;
|
||||
|
||||
/* set baud rate */
|
||||
cir_regs[port]->bdlr = cir->baud_rate & 0xff;
|
||||
cir_regs[port]->bdhr = (cir->baud_rate >> 8) & 0xff;
|
||||
|
||||
/* set receiver control register */
|
||||
cir_regs[port]->rcr = (CIR_SET_RDWOS(cir->rdwos) | CIR_SET_RXDCR(cir->rxdcr));
|
||||
|
||||
/* set carrier frequency register */
|
||||
cir_regs[port]->cfr = (CIR_SET_CF(cir->cfq) | CIR_SET_HS(cir->hcfs));
|
||||
|
||||
/* set fifo threshold */
|
||||
data = cir_regs[port]->mstcr & 0xf3;
|
||||
data |= CIR_SET_FIFO_TL(cir->fifo_tl);
|
||||
cir_regs[port]->mstcr = data;
|
||||
|
||||
clear_fifo(cir);
|
||||
enable_receiver(cir);
|
||||
disable_rx_demodulation(cir);
|
||||
|
||||
set_rx_active(cir);
|
||||
int_enable(cir);
|
||||
rx_int_enable(cir);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void clear_fifo(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->mstcr |= CIR_FIFO_CLEAR;
|
||||
}
|
||||
|
||||
void enable_receiver(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->rcr |= CIR_RXEN;
|
||||
}
|
||||
|
||||
void disable_receiver(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->rcr &= ~CIR_RXEN;
|
||||
}
|
||||
|
||||
void enable_rx_demodulation(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->rcr |= CIR_RXEND;
|
||||
}
|
||||
|
||||
void disable_rx_demodulation(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->rcr &= ~CIR_RXEND;
|
||||
}
|
||||
|
||||
void set_rx_active(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->rcr |= CIR_RXACT;
|
||||
}
|
||||
|
||||
void int_enable(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->ier |= CIR_IEC;
|
||||
}
|
||||
|
||||
void rx_int_enable(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->ier |= CIR_RDAIE;
|
||||
}
|
||||
|
||||
void dump_regs(struct cir_port *cir)
|
||||
{
|
||||
printk("mstcr %x ier %x iir %x cfr %x rcr %x tcr %x tfsr %x rfsr %x\n",
|
||||
cir_regs[cir->port]->mstcr,
|
||||
cir_regs[cir->port]->ier,
|
||||
cir_regs[cir->port]->iir,
|
||||
cir_regs[cir->port]->cfr,
|
||||
cir_regs[cir->port]->rcr,
|
||||
cir_regs[cir->port]->tcr,
|
||||
cir_regs[cir->port]->tfsr,
|
||||
cir_regs[cir->port]->rfsr);
|
||||
|
||||
while (cir_regs[cir->port]->iir & CIR_RDAI) {
|
||||
printk("data %x\n", cir_regs[cir->port]->dr);
|
||||
}
|
||||
}
|
||||
|
||||
void dump_reg_addr(struct cir_port *cir)
|
||||
{
|
||||
printk("dr %x mstcr %x ier %x iir %x cfr %x rcr %x tcr %x bdlr %x bdhr %x tfsr %x rfsr %x\n",
|
||||
(unsigned)&cir_regs[cir->port]->dr,
|
||||
(unsigned)&cir_regs[cir->port]->mstcr,
|
||||
(unsigned)&cir_regs[cir->port]->ier,
|
||||
(unsigned)&cir_regs[cir->port]->iir,
|
||||
(unsigned)&cir_regs[cir->port]->cfr,
|
||||
(unsigned)&cir_regs[cir->port]->rcr,
|
||||
(unsigned)&cir_regs[cir->port]->tcr,
|
||||
(unsigned)&cir_regs[cir->port]->bdlr,
|
||||
(unsigned)&cir_regs[cir->port]->bdhr,
|
||||
(unsigned)&cir_regs[cir->port]->tfsr,
|
||||
(unsigned)&cir_regs[cir->port]->rfsr);
|
||||
}
|
||||
|
||||
int cir_get_rx_count(struct cir_port *cir)
|
||||
{
|
||||
return cir_regs[cir->port]->rfsr & CIR_RXFBC_MASK;
|
||||
}
|
||||
|
||||
char cir_read_data(struct cir_port *cir)
|
||||
{
|
||||
return cir_regs[cir->port]->dr;
|
||||
}
|
||||
|
||||
char get_int_status(struct cir_port *cir)
|
||||
{
|
||||
return cir_regs[cir->port]->iir;
|
||||
}
|
||||
#endif
|
||||
@@ -1,352 +0,0 @@
|
||||
/*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* IT8172/QED5231 board setup.
|
||||
*
|
||||
* Copyright 2000 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <linux/major.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/pm.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/it8172/it8172.h>
|
||||
#include <asm/it8712.h>
|
||||
|
||||
extern struct resource ioport_resource;
|
||||
#ifdef CONFIG_SERIO_I8042
|
||||
int init_8712_keyboard(void);
|
||||
#endif
|
||||
|
||||
extern int SearchIT8712(void);
|
||||
extern void InitLPCInterface(void);
|
||||
extern char * __init prom_getcmdline(void);
|
||||
extern void it8172_restart(char *command);
|
||||
extern void it8172_halt(void);
|
||||
extern void it8172_power_off(void);
|
||||
|
||||
extern void it8172_time_init(void);
|
||||
|
||||
#ifdef CONFIG_IT8172_REVC
|
||||
struct {
|
||||
struct resource ram;
|
||||
struct resource pci_mem;
|
||||
struct resource pci_io;
|
||||
struct resource flash;
|
||||
struct resource boot;
|
||||
} it8172_resources = {
|
||||
{
|
||||
.start = 0, /* to be initted */
|
||||
.end = 0,
|
||||
.name = "RAM",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x10000000,
|
||||
.end = 0x13FFFFFF,
|
||||
.name = "PCI Mem",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x14000000,
|
||||
.end = 0x17FFFFFF
|
||||
.name = "PCI I/O",
|
||||
}, {
|
||||
.start = 0x08000000,
|
||||
.end = 0x0CFFFFFF
|
||||
.name = "Flash",
|
||||
}, {
|
||||
.start = 0x1FC00000,
|
||||
.end = 0x1FFFFFFF
|
||||
.name = "Boot ROM",
|
||||
}
|
||||
};
|
||||
#else
|
||||
struct {
|
||||
struct resource ram;
|
||||
struct resource pci_mem0;
|
||||
struct resource pci_mem1;
|
||||
struct resource pci_io;
|
||||
struct resource pci_mem2;
|
||||
struct resource pci_mem3;
|
||||
struct resource flash;
|
||||
struct resource boot;
|
||||
} it8172_resources = {
|
||||
{
|
||||
.start = 0, /* to be initted */
|
||||
.end = 0,
|
||||
.name = "RAM",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x0C000000,
|
||||
.end = 0x0FFFFFFF,
|
||||
.name = "PCI Mem0",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x10000000,
|
||||
.end = 0x13FFFFFF,
|
||||
.name = "PCI Mem1",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x14000000,
|
||||
.end = 0x17FFFFFF
|
||||
.name = "PCI I/O",
|
||||
}, {
|
||||
.start = 0x1A000000,
|
||||
.end = 0x1BFFFFFF,
|
||||
.name = "PCI Mem2",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x1C000000,
|
||||
.end = 0x1FBFFFFF,
|
||||
.name = "PCI Mem3",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x08000000,
|
||||
.end = 0x0CFFFFFF
|
||||
.name = "Flash",
|
||||
}, {
|
||||
.start = 0x1FC00000,
|
||||
.end = 0x1FFFFFFF
|
||||
.name = "Boot ROM",
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
void __init it8172_init_ram_resource(unsigned long memsize)
|
||||
{
|
||||
it8172_resources.ram.end = memsize;
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
unsigned short dsr;
|
||||
char *argptr;
|
||||
|
||||
argptr = prom_getcmdline();
|
||||
#ifdef CONFIG_SERIAL_CONSOLE
|
||||
if ((argptr = strstr(argptr, "console=")) == NULL) {
|
||||
argptr = prom_getcmdline();
|
||||
strcat(argptr, " console=ttyS0,115200");
|
||||
}
|
||||
#endif
|
||||
|
||||
clear_c0_status(ST0_FR);
|
||||
|
||||
board_time_init = it8172_time_init;
|
||||
|
||||
_machine_restart = it8172_restart;
|
||||
_machine_halt = it8172_halt;
|
||||
pm_power_off = it8172_power_off;
|
||||
|
||||
/*
|
||||
* IO/MEM resources.
|
||||
*
|
||||
* revisit this area.
|
||||
*/
|
||||
set_io_port_base(KSEG1);
|
||||
ioport_resource.start = it8172_resources.pci_io.start;
|
||||
ioport_resource.end = it8172_resources.pci_io.end;
|
||||
#ifdef CONFIG_IT8172_REVC
|
||||
iomem_resource.start = it8172_resources.pci_mem.start;
|
||||
iomem_resource.end = it8172_resources.pci_mem.end;
|
||||
#else
|
||||
iomem_resource.start = it8172_resources.pci_mem0.start;
|
||||
iomem_resource.end = it8172_resources.pci_mem3.end;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
ROOT_DEV = Root_RAM0;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Pull enabled devices out of standby
|
||||
*/
|
||||
IT_IO_READ16(IT_PM_DSR, dsr);
|
||||
|
||||
/*
|
||||
* Fixme: This breaks when these drivers are modules!!!
|
||||
*/
|
||||
#ifdef CONFIG_SOUND_IT8172
|
||||
dsr &= ~IT_PM_DSR_ACSB;
|
||||
#else
|
||||
dsr |= IT_PM_DSR_ACSB;
|
||||
#endif
|
||||
#ifdef CONFIG_BLK_DEV_IT8172
|
||||
dsr &= ~IT_PM_DSR_IDESB;
|
||||
#else
|
||||
dsr |= IT_PM_DSR_IDESB;
|
||||
#endif
|
||||
IT_IO_WRITE16(IT_PM_DSR, dsr);
|
||||
|
||||
InitLPCInterface();
|
||||
|
||||
#ifdef CONFIG_MIPS_ITE8172
|
||||
if (SearchIT8712()) {
|
||||
printk("Found IT8712 Super IO\n");
|
||||
/* enable IT8712 serial port */
|
||||
LPCSetConfig(LDN_SERIAL1, 0x30, 0x01); /* enable */
|
||||
LPCSetConfig(LDN_SERIAL1, 0x23, 0x01); /* clock selection */
|
||||
#ifdef CONFIG_SERIO_I8042
|
||||
if (init_8712_keyboard()) {
|
||||
printk("Unable to initialize keyboard\n");
|
||||
LPCSetConfig(LDN_KEYBOARD, 0x30, 0x0); /* disable keyboard */
|
||||
} else {
|
||||
LPCSetConfig(LDN_KEYBOARD, 0x30, 0x1); /* enable keyboard */
|
||||
LPCSetConfig(LDN_KEYBOARD, 0xf0, 0x2);
|
||||
LPCSetConfig(LDN_KEYBOARD, 0x71, 0x3);
|
||||
|
||||
LPCSetConfig(LDN_MOUSE, 0x30, 0x1); /* enable mouse */
|
||||
|
||||
LPCSetConfig(0x4, 0x30, 0x1);
|
||||
LPCSetConfig(0x4, 0xf4, LPCGetConfig(0x4, 0xf4) | 0x80);
|
||||
|
||||
if ((LPCGetConfig(LDN_KEYBOARD, 0x30) == 0) ||
|
||||
(LPCGetConfig(LDN_MOUSE, 0x30) == 0))
|
||||
printk("Error: keyboard or mouse not enabled\n");
|
||||
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk("IT8712 Super IO not found\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IT8172_CIR
|
||||
{
|
||||
unsigned long data;
|
||||
//printk("Enabling CIR0\n");
|
||||
IT_IO_READ16(IT_PM_DSR, data);
|
||||
data &= ~IT_PM_DSR_CIR0SB;
|
||||
IT_IO_WRITE16(IT_PM_DSR, data);
|
||||
//printk("DSR register: %x\n", (unsigned)IT_IO_READ16(IT_PM_DSR, data));
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_IT8172_SCR0
|
||||
{
|
||||
unsigned i;
|
||||
/* Enable Smart Card Reader 0 */
|
||||
/* First power it up */
|
||||
IT_IO_READ16(IT_PM_DSR, i);
|
||||
i &= ~IT_PM_DSR_SCR0SB;
|
||||
IT_IO_WRITE16(IT_PM_DSR, i);
|
||||
/* Then initialize its registers */
|
||||
outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
|
||||
|IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
|
||||
|IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
|
||||
|IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
|
||||
|IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
|
||||
IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SFR);
|
||||
outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
|
||||
IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SCDR);
|
||||
}
|
||||
#endif /* CONFIG_IT8172_SCR0 */
|
||||
#ifdef CONFIG_IT8172_SCR1
|
||||
{
|
||||
unsigned i;
|
||||
/* Enable Smart Card Reader 1 */
|
||||
/* First power it up */
|
||||
IT_IO_READ16(IT_PM_DSR, i);
|
||||
i &= ~IT_PM_DSR_SCR1SB;
|
||||
IT_IO_WRITE16(IT_PM_DSR, i);
|
||||
/* Then initialize its registers */
|
||||
outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
|
||||
|IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
|
||||
|IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
|
||||
|IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
|
||||
|IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
|
||||
IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SFR);
|
||||
outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
|
||||
IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SCDR);
|
||||
}
|
||||
#endif /* CONFIG_IT8172_SCR1 */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SERIO_I8042
|
||||
/*
|
||||
* According to the ITE Special BIOS Note for waking up the
|
||||
* keyboard controller...
|
||||
*/
|
||||
static int init_8712_keyboard(void)
|
||||
{
|
||||
unsigned int cmd_port = 0x14000064;
|
||||
unsigned int data_port = 0x14000060;
|
||||
^^^^^^^^^^^
|
||||
Somebody here doesn't grok the concept of io ports.
|
||||
|
||||
unsigned char data;
|
||||
int i;
|
||||
|
||||
outb(0xaa, cmd_port); /* send self-test cmd */
|
||||
i = 0;
|
||||
while (!(inb(cmd_port) & 0x1)) { /* wait output buffer full */
|
||||
i++;
|
||||
if (i > 0xffffff)
|
||||
return 1;
|
||||
}
|
||||
|
||||
data = inb(data_port);
|
||||
outb(0xcb, cmd_port); /* set ps2 mode */
|
||||
while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
|
||||
i++;
|
||||
if (i > 0xffffff)
|
||||
return 1;
|
||||
}
|
||||
outb(0x01, data_port);
|
||||
while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
|
||||
i++;
|
||||
if (i > 0xffffff)
|
||||
return 1;
|
||||
}
|
||||
|
||||
outb(0x60, cmd_port); /* write 8042 command byte */
|
||||
while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
|
||||
i++;
|
||||
if (i > 0xffffff)
|
||||
return 1;
|
||||
}
|
||||
outb(0x45, data_port); /* at interface, keyboard enabled, system flag */
|
||||
while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
|
||||
i++;
|
||||
if (i > 0xffffff)
|
||||
return 1;
|
||||
}
|
||||
|
||||
outb(0xae, cmd_port); /* enable interface */
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -1,144 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* ITE Semi IT8712 Super I/O functions.
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/types.h>
|
||||
#include <asm/it8712.h>
|
||||
#include <asm/it8172/it8172.h>
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
void LPCEnterMBPnP(void)
|
||||
{
|
||||
int i;
|
||||
unsigned char key[4] = {0x87, 0x01, 0x55, 0x55};
|
||||
|
||||
for (i = 0; i<4; i++)
|
||||
outb(key[i], LPC_KEY_ADDR);
|
||||
|
||||
}
|
||||
|
||||
void LPCExitMBPnP(void)
|
||||
{
|
||||
outb(0x02, LPC_KEY_ADDR);
|
||||
outb(0x02, LPC_DATA_ADDR);
|
||||
}
|
||||
|
||||
void LPCSetConfig(char LdnNumber, char Index, char data)
|
||||
{
|
||||
LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
|
||||
outb(0x07, LPC_KEY_ADDR);
|
||||
outb(LdnNumber, LPC_DATA_ADDR);
|
||||
outb(Index, LPC_KEY_ADDR);
|
||||
outb(data, LPC_DATA_ADDR);
|
||||
LPCExitMBPnP();
|
||||
}
|
||||
|
||||
char LPCGetConfig(char LdnNumber, char Index)
|
||||
{
|
||||
char rtn;
|
||||
|
||||
LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
|
||||
outb(0x07, LPC_KEY_ADDR);
|
||||
outb(LdnNumber, LPC_DATA_ADDR);
|
||||
outb(Index, LPC_KEY_ADDR);
|
||||
rtn = inb(LPC_DATA_ADDR);
|
||||
LPCExitMBPnP();
|
||||
return rtn;
|
||||
}
|
||||
|
||||
int SearchIT8712(void)
|
||||
{
|
||||
unsigned char Id1, Id2;
|
||||
unsigned short Id;
|
||||
|
||||
LPCEnterMBPnP();
|
||||
outb(0x20, LPC_KEY_ADDR); /* chip id byte 1 */
|
||||
Id1 = inb(LPC_DATA_ADDR);
|
||||
outb(0x21, LPC_KEY_ADDR); /* chip id byte 2 */
|
||||
Id2 = inb(LPC_DATA_ADDR);
|
||||
Id = (Id1 << 8) | Id2;
|
||||
LPCExitMBPnP();
|
||||
if (Id == 0x8712)
|
||||
return TRUE;
|
||||
else
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
void InitLPCInterface(void)
|
||||
{
|
||||
unsigned char bus, dev_fn;
|
||||
unsigned long data;
|
||||
|
||||
bus = 0;
|
||||
dev_fn = 1<<3 | 4;
|
||||
|
||||
|
||||
/* pci cmd, SERR# Enable */
|
||||
IT_WRITE(IT_CONFADDR,
|
||||
(bus << IT_BUSNUM_SHF) |
|
||||
(dev_fn << IT_FUNCNUM_SHF) |
|
||||
((0x4 / 4) << IT_REGNUM_SHF));
|
||||
IT_READ(IT_CONFDATA, data);
|
||||
data |= 0x0100;
|
||||
IT_WRITE(IT_CONFADDR,
|
||||
(bus << IT_BUSNUM_SHF) |
|
||||
(dev_fn << IT_FUNCNUM_SHF) |
|
||||
((0x4 / 4) << IT_REGNUM_SHF));
|
||||
IT_WRITE(IT_CONFDATA, data);
|
||||
|
||||
/* setup serial irq control register */
|
||||
IT_WRITE(IT_CONFADDR,
|
||||
(bus << IT_BUSNUM_SHF) |
|
||||
(dev_fn << IT_FUNCNUM_SHF) |
|
||||
((0x48 / 4) << IT_REGNUM_SHF));
|
||||
IT_READ(IT_CONFDATA, data);
|
||||
data = (data & 0xffff00ff) | 0xc400;
|
||||
IT_WRITE(IT_CONFADDR,
|
||||
(bus << IT_BUSNUM_SHF) |
|
||||
(dev_fn << IT_FUNCNUM_SHF) |
|
||||
((0x48 / 4) << IT_REGNUM_SHF));
|
||||
IT_WRITE(IT_CONFDATA, data);
|
||||
|
||||
|
||||
/* Enable I/O Space Subtractive Decode */
|
||||
/* default 0x4C is 0x3f220000 */
|
||||
IT_WRITE(IT_CONFADDR,
|
||||
(bus << IT_BUSNUM_SHF) |
|
||||
(dev_fn << IT_FUNCNUM_SHF) |
|
||||
((0x4C / 4) << IT_REGNUM_SHF));
|
||||
IT_WRITE(IT_CONFDATA, 0x3f2200f3);
|
||||
}
|
||||
@@ -1,135 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* PROM library initialisation code, assuming a version of
|
||||
* pmon is the boot code.
|
||||
*
|
||||
* Copyright 2000 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This file was derived from Carsten Langgaard's
|
||||
* arch/mips/mips-boards/xx files.
|
||||
*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
extern int prom_argc;
|
||||
extern char **prom_argv, **prom_envp;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char *name;
|
||||
/* char *val; */
|
||||
}t_env_var;
|
||||
|
||||
|
||||
char * __init prom_getcmdline(void)
|
||||
{
|
||||
return &(arcs_cmdline[0]);
|
||||
}
|
||||
|
||||
void __init prom_init_cmdline(void)
|
||||
{
|
||||
char *cp;
|
||||
int actr;
|
||||
|
||||
actr = 1; /* Always ignore argv[0] */
|
||||
|
||||
cp = &(arcs_cmdline[0]);
|
||||
while(actr < prom_argc) {
|
||||
strcpy(cp, prom_argv[actr]);
|
||||
cp += strlen(prom_argv[actr]);
|
||||
*cp++ = ' ';
|
||||
actr++;
|
||||
}
|
||||
if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
|
||||
--cp;
|
||||
*cp = '\0';
|
||||
|
||||
}
|
||||
|
||||
|
||||
char *prom_getenv(char *envname)
|
||||
{
|
||||
/*
|
||||
* Return a pointer to the given environment variable.
|
||||
* Environment variables are stored in the form of "memsize=64".
|
||||
*/
|
||||
|
||||
t_env_var *env = (t_env_var *)prom_envp;
|
||||
int i;
|
||||
|
||||
i = strlen(envname);
|
||||
|
||||
while(env->name) {
|
||||
if(strncmp(envname, env->name, i) == 0) {
|
||||
return(env->name + strlen(envname) + 1);
|
||||
}
|
||||
env++;
|
||||
}
|
||||
return(NULL);
|
||||
}
|
||||
|
||||
static inline unsigned char str2hexnum(unsigned char c)
|
||||
{
|
||||
if(c >= '0' && c <= '9')
|
||||
return c - '0';
|
||||
if(c >= 'a' && c <= 'f')
|
||||
return c - 'a' + 10;
|
||||
return 0; /* foo */
|
||||
}
|
||||
|
||||
unsigned long __init prom_free_prom_memory(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long __init prom_get_memsize(void)
|
||||
{
|
||||
char *memsize_str;
|
||||
unsigned int memsize;
|
||||
|
||||
memsize_str = prom_getenv("memsize");
|
||||
if (!memsize_str) {
|
||||
#ifdef CONFIG_MIPS_ITE8172
|
||||
memsize = 32;
|
||||
#elif defined(CONFIG_MIPS_IVR)
|
||||
memsize = 64;
|
||||
#else
|
||||
memsize = 8;
|
||||
#endif
|
||||
printk("memsize unknown: setting to %dMB\n", memsize);
|
||||
} else {
|
||||
printk("memsize: %s\n", memsize_str);
|
||||
memsize = simple_strtol(memsize_str, NULL, 0);
|
||||
}
|
||||
return memsize;
|
||||
}
|
||||
@@ -1,139 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Low level uart routines to directly access a 16550 uart.
|
||||
*
|
||||
* Copyright 2000,2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define SERIAL_BASE 0xB4011800 /* it8172 */
|
||||
#define SER_CMD 5
|
||||
#define SER_DATA 0x00
|
||||
#define TX_BUSY 0x20
|
||||
|
||||
#define TIMEOUT 0xffff
|
||||
#undef SLOW_DOWN
|
||||
|
||||
static const char digits[16] = "0123456789abcdef";
|
||||
static volatile unsigned char *const com1 = (unsigned char *) SERIAL_BASE;
|
||||
|
||||
|
||||
#ifdef SLOW_DOWN
|
||||
static inline void slow_down()
|
||||
{
|
||||
int k;
|
||||
for (k = 0; k < 10000; k++);
|
||||
}
|
||||
#else
|
||||
#define slow_down()
|
||||
#endif
|
||||
|
||||
void putch(const unsigned char c)
|
||||
{
|
||||
unsigned char ch;
|
||||
int i = 0;
|
||||
|
||||
do {
|
||||
ch = com1[SER_CMD];
|
||||
slow_down();
|
||||
i++;
|
||||
if (i > TIMEOUT) {
|
||||
break;
|
||||
}
|
||||
} while (0 == (ch & TX_BUSY));
|
||||
com1[SER_DATA] = c;
|
||||
}
|
||||
|
||||
void puts(unsigned char *cp)
|
||||
{
|
||||
unsigned char ch;
|
||||
int i = 0;
|
||||
|
||||
while (*cp) {
|
||||
do {
|
||||
ch = com1[SER_CMD];
|
||||
slow_down();
|
||||
i++;
|
||||
if (i > TIMEOUT) {
|
||||
break;
|
||||
}
|
||||
} while (0 == (ch & TX_BUSY));
|
||||
com1[SER_DATA] = *cp++;
|
||||
}
|
||||
putch('\r');
|
||||
putch('\n');
|
||||
}
|
||||
|
||||
void fputs(unsigned char *cp)
|
||||
{
|
||||
unsigned char ch;
|
||||
int i = 0;
|
||||
|
||||
while (*cp) {
|
||||
|
||||
do {
|
||||
ch = com1[SER_CMD];
|
||||
slow_down();
|
||||
i++;
|
||||
if (i > TIMEOUT) {
|
||||
break;
|
||||
}
|
||||
} while (0 == (ch & TX_BUSY));
|
||||
com1[SER_DATA] = *cp++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void put64(uint64_t ul)
|
||||
{
|
||||
int cnt;
|
||||
unsigned ch;
|
||||
|
||||
cnt = 16; /* 16 nibbles in a 64 bit long */
|
||||
putch('0');
|
||||
putch('x');
|
||||
do {
|
||||
cnt--;
|
||||
ch = (unsigned char) (ul >> cnt * 4) & 0x0F;
|
||||
putch(digits[ch]);
|
||||
} while (cnt > 0);
|
||||
}
|
||||
|
||||
void put32(unsigned u)
|
||||
{
|
||||
int cnt;
|
||||
unsigned ch;
|
||||
|
||||
cnt = 8; /* 8 nibbles in a 32 bit long */
|
||||
putch('0');
|
||||
putch('x');
|
||||
do {
|
||||
cnt--;
|
||||
ch = (unsigned char) (u >> cnt * 4) & 0x0F;
|
||||
putch(digits[ch]);
|
||||
} while (cnt > 0);
|
||||
}
|
||||
@@ -1,60 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* ITE 8172 reset routines.
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
void it8172_restart()
|
||||
{
|
||||
set_c0_status(ST0_BEV | ST0_ERL);
|
||||
change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
|
||||
flush_cache_all();
|
||||
write_c0_wired(0);
|
||||
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
|
||||
}
|
||||
|
||||
void it8172_halt(void)
|
||||
{
|
||||
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
|
||||
while (1)
|
||||
__asm__(".set\tmips3\n\t"
|
||||
"wait\n\t"
|
||||
".set\tmips0");
|
||||
}
|
||||
|
||||
void it8172_power_off(void)
|
||||
{
|
||||
it8172_halt();
|
||||
}
|
||||
@@ -1,249 +0,0 @@
|
||||
/*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* Copyright (C) 2003 MontaVista Software Inc.
|
||||
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* ########################################################################
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
* ########################################################################
|
||||
*
|
||||
* Setting up the clock on the MIPS boards.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mc146818rtc.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/it8172/it8172.h>
|
||||
#include <asm/it8172/it8172_int.h>
|
||||
#include <asm/debug.h>
|
||||
|
||||
#define IT8172_RTC_ADR_REG (IT8172_PCI_IO_BASE + IT_RTC_BASE)
|
||||
#define IT8172_RTC_DAT_REG (IT8172_RTC_ADR_REG + 1)
|
||||
#define IT8172_RTC_CENTURY_REG (IT8172_PCI_IO_BASE + IT_RTC_CENTURY)
|
||||
|
||||
static volatile char *rtc_adr_reg = (char*)KSEG1ADDR(IT8172_RTC_ADR_REG);
|
||||
static volatile char *rtc_dat_reg = (char*)KSEG1ADDR(IT8172_RTC_DAT_REG);
|
||||
static volatile char *rtc_century_reg = (char*)KSEG1ADDR(IT8172_RTC_CENTURY_REG);
|
||||
|
||||
unsigned char it8172_rtc_read_data(unsigned long addr)
|
||||
{
|
||||
unsigned char retval;
|
||||
|
||||
*rtc_adr_reg = addr;
|
||||
retval = *rtc_dat_reg;
|
||||
return retval;
|
||||
}
|
||||
|
||||
void it8172_rtc_write_data(unsigned char data, unsigned long addr)
|
||||
{
|
||||
*rtc_adr_reg = addr;
|
||||
*rtc_dat_reg = data;
|
||||
}
|
||||
|
||||
#undef CMOS_READ
|
||||
#undef CMOS_WRITE
|
||||
#define CMOS_READ(addr) it8172_rtc_read_data(addr)
|
||||
#define CMOS_WRITE(data, addr) it8172_rtc_write_data(data, addr)
|
||||
|
||||
static unsigned char saved_control; /* remember rtc control reg */
|
||||
static inline int rtc_24h(void) { return saved_control & RTC_24H; }
|
||||
static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; }
|
||||
|
||||
static inline unsigned char
|
||||
bin_to_hw(unsigned char c)
|
||||
{
|
||||
if (rtc_dm_binary())
|
||||
return c;
|
||||
else
|
||||
return ((c/10) << 4) + (c%10);
|
||||
}
|
||||
|
||||
static inline unsigned char
|
||||
hw_to_bin(unsigned char c)
|
||||
{
|
||||
if (rtc_dm_binary())
|
||||
return c;
|
||||
else
|
||||
return (c>>4)*10 + (c &0xf);
|
||||
}
|
||||
|
||||
/* 0x80 bit indicates pm in 12-hour format */
|
||||
static inline unsigned char
|
||||
hour_bin_to_hw(unsigned char c)
|
||||
{
|
||||
if (rtc_24h())
|
||||
return bin_to_hw(c);
|
||||
if (c >= 12)
|
||||
return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */
|
||||
else
|
||||
return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */
|
||||
}
|
||||
|
||||
static inline unsigned char
|
||||
hour_hw_to_bin(unsigned char c)
|
||||
{
|
||||
unsigned char tmp = hw_to_bin(c&0x3f);
|
||||
if (rtc_24h())
|
||||
return tmp;
|
||||
if (c & 0x80)
|
||||
return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */
|
||||
else
|
||||
return (tmp==12)?0:tmp; /* 12am is 0 */
|
||||
}
|
||||
|
||||
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
|
||||
static unsigned long r4k_cur; /* What counter should be at next timer irq */
|
||||
extern unsigned int mips_hpt_frequency;
|
||||
|
||||
/*
|
||||
* Figure out the r4k offset, the amount to increment the compare
|
||||
* register for each time tick.
|
||||
* Use the RTC to calculate offset.
|
||||
*/
|
||||
static unsigned long __init cal_r4koff(void)
|
||||
{
|
||||
unsigned int flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
/* Start counter exactly on falling edge of update flag */
|
||||
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
|
||||
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
|
||||
|
||||
/* Start r4k counter. */
|
||||
write_c0_count(0);
|
||||
|
||||
/* Read counter exactly on falling edge of update flag */
|
||||
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
|
||||
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
|
||||
|
||||
mips_hpt_frequency = read_c0_count();
|
||||
|
||||
/* restore interrupts */
|
||||
local_irq_restore(flags);
|
||||
|
||||
return (mips_hpt_frequency / HZ);
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
it8172_rtc_get_time(void)
|
||||
{
|
||||
unsigned int year, mon, day, hour, min, sec;
|
||||
unsigned int flags;
|
||||
|
||||
/* avoid update-in-progress. */
|
||||
for (;;) {
|
||||
local_irq_save(flags);
|
||||
if (! (CMOS_READ(RTC_REG_A) & RTC_UIP))
|
||||
break;
|
||||
/* don't hold intr closed all the time */
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
/* Read regs. */
|
||||
sec = hw_to_bin(CMOS_READ(RTC_SECONDS));
|
||||
min = hw_to_bin(CMOS_READ(RTC_MINUTES));
|
||||
hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS));
|
||||
day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH));
|
||||
mon = hw_to_bin(CMOS_READ(RTC_MONTH));
|
||||
year = hw_to_bin(CMOS_READ(RTC_YEAR)) +
|
||||
hw_to_bin(*rtc_century_reg) * 100;
|
||||
|
||||
/* restore interrupts */
|
||||
local_irq_restore(flags);
|
||||
|
||||
return mktime(year, mon, day, hour, min, sec);
|
||||
}
|
||||
|
||||
static int
|
||||
it8172_rtc_set_time(unsigned long t)
|
||||
{
|
||||
struct rtc_time tm;
|
||||
unsigned int flags;
|
||||
|
||||
/* convert */
|
||||
to_tm(t, &tm);
|
||||
|
||||
/* avoid update-in-progress. */
|
||||
for (;;) {
|
||||
local_irq_save(flags);
|
||||
if (! (CMOS_READ(RTC_REG_A) & RTC_UIP))
|
||||
break;
|
||||
/* don't hold intr closed all the time */
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
*rtc_century_reg = bin_to_hw(tm.tm_year/100);
|
||||
CMOS_WRITE(bin_to_hw(tm.tm_sec), RTC_SECONDS);
|
||||
CMOS_WRITE(bin_to_hw(tm.tm_min), RTC_MINUTES);
|
||||
CMOS_WRITE(hour_bin_to_hw(tm.tm_hour), RTC_HOURS);
|
||||
CMOS_WRITE(bin_to_hw(tm.tm_mday), RTC_DAY_OF_MONTH);
|
||||
CMOS_WRITE(bin_to_hw(tm.tm_mon+1), RTC_MONTH); /* tm_mon starts from 0 */
|
||||
CMOS_WRITE(bin_to_hw(tm.tm_year%100), RTC_YEAR);
|
||||
|
||||
/* restore interrupts */
|
||||
local_irq_restore(flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init it8172_time_init(void)
|
||||
{
|
||||
unsigned int est_freq, flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
saved_control = CMOS_READ(RTC_CONTROL);
|
||||
|
||||
printk("calculating r4koff... ");
|
||||
r4k_offset = cal_r4koff();
|
||||
printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
|
||||
|
||||
est_freq = 2*r4k_offset*HZ;
|
||||
est_freq += 5000; /* round */
|
||||
est_freq -= est_freq%10000;
|
||||
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
|
||||
(est_freq%1000000)*100/1000000);
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
rtc_mips_get_time = it8172_rtc_get_time;
|
||||
rtc_mips_set_time = it8172_rtc_set_time;
|
||||
}
|
||||
|
||||
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
|
||||
|
||||
void __init plat_timer_setup(struct irqaction *irq)
|
||||
{
|
||||
puts("timer_setup\n");
|
||||
put32(NR_IRQS);
|
||||
puts("");
|
||||
/* we are using the cpu counter for timer interrupts */
|
||||
setup_irq(MIPS_CPU_TIMER_IRQ, irq);
|
||||
|
||||
/* to generate the first timer interrupt */
|
||||
r4k_cur = (read_c0_count() + r4k_offset);
|
||||
write_c0_compare(r4k_cur);
|
||||
set_c0_status(ALLINTS);
|
||||
}
|
||||
@@ -1,10 +0,0 @@
|
||||
#
|
||||
# Copyright 2000 MontaVista Software Inc.
|
||||
# Author: MontaVista Software, Inc.
|
||||
# ppopov@mvista.com or source@mvista.com
|
||||
#
|
||||
# Makefile for the Globespan IVR board,
|
||||
# board-specific files.
|
||||
#
|
||||
|
||||
obj-y += init.o
|
||||
@@ -1,3 +0,0 @@
|
||||
This is not really a board made by ITE Semi, but it's very
|
||||
similar to the ITE QED-4N-S01B board. The IVR board is made
|
||||
by Globespan and it's a reference board for the PVR chip.
|
||||
@@ -1,81 +0,0 @@
|
||||
/*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* IVR board setup.
|
||||
*
|
||||
* Copyright 2000 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/it8172/it8172.h>
|
||||
#include <asm/it8172/it8172_dbg.h>
|
||||
|
||||
int prom_argc;
|
||||
char **prom_argv, **prom_envp;
|
||||
|
||||
extern void __init prom_init_cmdline(void);
|
||||
extern unsigned long __init prom_get_memsize(void);
|
||||
extern void __init it8172_init_ram_resource(unsigned long memsize);
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "Globespan IVR";
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
unsigned long mem_size;
|
||||
unsigned long pcicr;
|
||||
|
||||
prom_argc = fw_arg0;
|
||||
prom_argv = (char **) fw_arg1;
|
||||
prom_envp = (int *) fw_arg3;
|
||||
|
||||
mips_machgroup = MACH_GROUP_GLOBESPAN;
|
||||
mips_machtype = MACH_IVR; /* Globespan's iTVC15 reference board */
|
||||
|
||||
prom_init_cmdline();
|
||||
|
||||
/* pmon does not set memsize */
|
||||
mem_size = prom_get_memsize();
|
||||
mem_size = mem_size << 20;
|
||||
|
||||
/*
|
||||
* make the entire physical memory visible to pci bus masters
|
||||
*/
|
||||
IT_READ(IT_MC_PCICR, pcicr);
|
||||
pcicr &= ~0x1f;
|
||||
pcicr |= (mem_size - 1) >> 22;
|
||||
IT_WRITE(IT_MC_PCICR, pcicr);
|
||||
|
||||
it8172_init_ram_resource(mem_size);
|
||||
add_memory_region(0, mem_size, BOOT_MEM_RAM);
|
||||
}
|
||||
@@ -1,10 +0,0 @@
|
||||
#
|
||||
# Copyright 2000 MontaVista Software Inc.
|
||||
# Author: MontaVista Software, Inc.
|
||||
# ppopov@mvista.com or source@mvista.com
|
||||
#
|
||||
# Makefile for the ITE 8172 (qed-4n-s01b) board, board
|
||||
# specific files.
|
||||
#
|
||||
|
||||
obj-y := init.o
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user