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MIPS: microMIPS: uasm: Split 'uasm.c' into two files.
Split 'uasm.c' into two files. The new file 'uasm-mips.c' has the functions specific to the classic MIPS ISA. The 'uasm.c' file contains common code that can be used by classic or other ISAs that could be supported by the kernel. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: kevink@paralogos.com Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/4922/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 0961103562ab958fa74f35043bf4f72e51ed6155)
This commit is contained in:
Steven J. Hill
committed by
Steven J. Hill
Steven J. Hill
parent
2aa9fd06e2
commit
abc597fe62
@@ -6,7 +6,7 @@
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* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
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* Copyright (C) 2005 Maciej W. Rozycki
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* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2012 MIPS Technologies, Inc.
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* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/types.h>
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@@ -22,44 +22,57 @@
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#define UASM_EXPORT_SYMBOL(sym)
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#endif
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#define _UASM_ISA_CLASSIC 0
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#ifndef UASM_ISA
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#define UASM_ISA _UASM_ISA_CLASSIC
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#endif
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#if (UASM_ISA == _UASM_ISA_CLASSIC)
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#define ISAOPC(op) uasm_i##op
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#define ISAFUNC(x) x
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#else
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#error Unsupported micro-assembler ISA!!!
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#endif
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#define Ip_u1u2u3(op) \
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void __uasminit \
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uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
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ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
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#define Ip_u2u1u3(op) \
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void __uasminit \
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uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
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ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
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#define Ip_u3u1u2(op) \
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void __uasminit \
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uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
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ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
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#define Ip_u1u2s3(op) \
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void __uasminit \
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uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
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ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
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#define Ip_u2s3u1(op) \
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void __uasminit \
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uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
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ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
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#define Ip_u2u1s3(op) \
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void __uasminit \
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uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
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ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
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#define Ip_u2u1msbu3(op) \
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void __uasminit \
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uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
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ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
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unsigned int d)
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#define Ip_u1u2(op) \
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void __uasminit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
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void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b)
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#define Ip_u1s2(op) \
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void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b)
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void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, signed int b)
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#define Ip_u1(op) void __uasminit uasm_i##op(u32 **buf, unsigned int a)
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#define Ip_u1(op) void __uasminit ISAOPC(op)(u32 **buf, unsigned int a)
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#define Ip_0(op) void __uasminit uasm_i##op(u32 **buf)
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#define Ip_0(op) void __uasminit ISAOPC(op)(u32 **buf)
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Ip_u2u1s3(_addiu);
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Ip_u3u1u2(_addu);
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@@ -132,14 +145,15 @@ struct uasm_label {
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int lab;
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};
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void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
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void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr,
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int lid);
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#ifdef CONFIG_64BIT
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int uasm_in_compat_space_p(long addr);
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int ISAFUNC(uasm_in_compat_space_p)(long addr);
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#endif
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int uasm_rel_hi(long val);
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int uasm_rel_lo(long val);
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void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
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void UASM_i_LA(u32 **buf, unsigned int rs, long addr);
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int ISAFUNC(uasm_rel_hi)(long val);
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int ISAFUNC(uasm_rel_lo)(long val);
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void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr);
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void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr);
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#define UASM_L_LA(lb) \
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static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
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@@ -196,27 +210,27 @@ static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
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unsigned int a2, unsigned int a3)
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{
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if (a3 < 32)
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uasm_i_drotr(p, a1, a2, a3);
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ISAOPC(_drotr)(p, a1, a2, a3);
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else
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uasm_i_drotr32(p, a1, a2, a3 - 32);
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ISAOPC(_drotr32)(p, a1, a2, a3 - 32);
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}
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static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
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unsigned int a2, unsigned int a3)
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{
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if (a3 < 32)
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uasm_i_dsll(p, a1, a2, a3);
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ISAOPC(_dsll)(p, a1, a2, a3);
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else
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uasm_i_dsll32(p, a1, a2, a3 - 32);
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ISAOPC(_dsll32)(p, a1, a2, a3 - 32);
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}
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static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
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unsigned int a2, unsigned int a3)
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{
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if (a3 < 32)
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uasm_i_dsrl(p, a1, a2, a3);
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ISAOPC(_dsrl)(p, a1, a2, a3);
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else
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uasm_i_dsrl32(p, a1, a2, a3 - 32);
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ISAOPC(_dsrl32)(p, a1, a2, a3 - 32);
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}
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/* Handle relocations. */
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@@ -4,7 +4,7 @@
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obj-y += cache.o dma-default.o extable.o fault.o \
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gup.o init.o mmap.o page.o page-funcs.o \
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tlbex.o tlbex-fault.o uasm.o
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tlbex.o tlbex-fault.o uasm-mips.o
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obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
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obj-$(CONFIG_64BIT) += pgtable-64.o
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@@ -0,0 +1,196 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* A small micro-assembler. It is intentionally kept simple, does only
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* support a subset of instructions, and does not try to hide pipeline
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* effects like branch delay slots.
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*
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* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
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* Copyright (C) 2005, 2007 Maciej W. Rozycki
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* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <asm/inst.h>
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#include <asm/elf.h>
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#include <asm/bugs.h>
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#include <asm/uasm.h>
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#define RS_MASK 0x1f
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#define RS_SH 21
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#define RT_MASK 0x1f
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#define RT_SH 16
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#define SCIMM_MASK 0xfffff
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#define SCIMM_SH 6
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/* This macro sets the non-variable bits of an instruction. */
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#define M(a, b, c, d, e, f) \
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((a) << OP_SH \
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| (b) << RS_SH \
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| (c) << RT_SH \
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| (d) << RD_SH \
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| (e) << RE_SH \
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| (f) << FUNC_SH)
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#include "uasm.c"
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static struct insn insn_table[] __uasminitdata = {
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{ insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
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{ insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
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{ insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
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{ insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
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{ insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
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{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
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{ insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
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{ insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
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{ insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
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{ insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
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{ insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
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{ insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
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{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
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{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
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{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
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{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
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{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
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{ insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
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{ insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
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{ insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
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{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
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{ insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
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{ insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
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{ insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
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{ insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
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{ insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
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{ insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
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{ insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
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{ insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
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{ insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
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{ insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
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{ insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
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{ insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
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{ insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
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{ insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
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{ insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
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{ insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
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{ insn_invalid, 0, 0 }
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};
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#undef M
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static inline __uasminit u32 build_bimm(s32 arg)
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{
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WARN(arg > 0x1ffff || arg < -0x20000,
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KERN_WARNING "Micro-assembler field overflow\n");
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WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
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return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
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}
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static inline __uasminit u32 build_jimm(u32 arg)
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{
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WARN(arg & ~(JIMM_MASK << 2),
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KERN_WARNING "Micro-assembler field overflow\n");
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return (arg >> 2) & JIMM_MASK;
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}
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/*
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* The order of opcode arguments is implicitly left to right,
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* starting with RS and ending with FUNC or IMM.
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*/
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static void __uasminit build_insn(u32 **buf, enum opcode opc, ...)
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{
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struct insn *ip = NULL;
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unsigned int i;
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va_list ap;
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u32 op;
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for (i = 0; insn_table[i].opcode != insn_invalid; i++)
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if (insn_table[i].opcode == opc) {
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ip = &insn_table[i];
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break;
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}
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if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
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panic("Unsupported Micro-assembler instruction %d", opc);
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op = ip->match;
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va_start(ap, opc);
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if (ip->fields & RS)
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op |= build_rs(va_arg(ap, u32));
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if (ip->fields & RT)
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op |= build_rt(va_arg(ap, u32));
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if (ip->fields & RD)
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op |= build_rd(va_arg(ap, u32));
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if (ip->fields & RE)
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op |= build_re(va_arg(ap, u32));
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if (ip->fields & SIMM)
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op |= build_simm(va_arg(ap, s32));
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if (ip->fields & UIMM)
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op |= build_uimm(va_arg(ap, u32));
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if (ip->fields & BIMM)
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op |= build_bimm(va_arg(ap, s32));
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if (ip->fields & JIMM)
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op |= build_jimm(va_arg(ap, u32));
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if (ip->fields & FUNC)
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op |= build_func(va_arg(ap, u32));
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if (ip->fields & SET)
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op |= build_set(va_arg(ap, u32));
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if (ip->fields & SCIMM)
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op |= build_scimm(va_arg(ap, u32));
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va_end(ap);
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**buf = op;
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(*buf)++;
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}
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static inline void __uasminit
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__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
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{
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long laddr = (long)lab->addr;
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long raddr = (long)rel->addr;
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switch (rel->type) {
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case R_MIPS_PC16:
|
||||
*rel->addr |= build_bimm(laddr - (raddr + 4));
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("Unsupported Micro-assembler relocation %d",
|
||||
rel->type);
|
||||
}
|
||||
}
|
||||
+78
-248
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user