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ARM: Remove mach-bcmring
Remove mach-bcmring as this is no longer maintained or used. Signed-off-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
-16
@@ -658,22 +658,6 @@ W: http://www.linux4sam.org
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S: Supported
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F: arch/arm/mach-at91/
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ARM/BCMRING ARM ARCHITECTURE
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M: Jiandong Zheng <jdzheng@broadcom.com>
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M: Scott Branden <sbranden@broadcom.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm/mach-bcmring
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ARM/BCMRING MTD NAND DRIVER
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M: Jiandong Zheng <jdzheng@broadcom.com>
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M: Scott Branden <sbranden@broadcom.com>
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L: linux-mtd@lists.infradead.org
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S: Maintained
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F: drivers/mtd/nand/bcm_umi_nand.c
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F: drivers/mtd/nand/bcm_umi_bch.c
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F: drivers/mtd/nand/nand_bcm_umi.h
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ARM/CALXEDA HIGHBANK ARCHITECTURE
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M: Rob Herring <rob.herring@calxeda.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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@@ -356,18 +356,6 @@ config ARCH_AT91
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This enables support for systems based on Atmel
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AT91RM9200 and AT91SAM9* processors.
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config ARCH_BCMRING
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bool "Broadcom BCMRING"
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depends on MMU
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select CPU_V6
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select ARM_AMBA
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select ARM_TIMER_SP804
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select CLKDEV_LOOKUP
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select GENERIC_CLOCKEVENTS
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select ARCH_WANT_OPTIONAL_GPIOLIB
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help
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Support for Broadcom's BCMRing platform.
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config ARCH_HIGHBANK
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bool "Calxeda Highbank-based"
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select ARCH_WANT_OPTIONAL_GPIOLIB
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@@ -1037,8 +1025,6 @@ source "arch/arm/mach-mvebu/Kconfig"
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source "arch/arm/mach-at91/Kconfig"
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source "arch/arm/mach-bcmring/Kconfig"
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source "arch/arm/mach-clps711x/Kconfig"
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source "arch/arm/mach-cns3xxx/Kconfig"
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@@ -136,7 +136,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
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# Machine directory name. This list is sorted alphanumerically
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# by CONFIG_* macro name.
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machine-$(CONFIG_ARCH_AT91) := at91
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machine-$(CONFIG_ARCH_BCMRING) := bcmring
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machine-$(CONFIG_ARCH_CLPS711X) := clps711x
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machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
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machine-$(CONFIG_ARCH_DAVINCI) := davinci
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@@ -1,79 +0,0 @@
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CONFIG_EXPERIMENTAL=y
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# CONFIG_LOCALVERSION_AUTO is not set
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# CONFIG_SWAP is not set
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CONFIG_SYSVIPC=y
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CONFIG_EXPERT=y
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CONFIG_KALLSYMS_EXTRA_PASS=y
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# CONFIG_HOTPLUG is not set
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# CONFIG_ELF_CORE is not set
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# CONFIG_EPOLL is not set
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# CONFIG_SIGNALFD is not set
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# CONFIG_TIMERFD is not set
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# CONFIG_EVENTFD is not set
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# CONFIG_AIO is not set
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CONFIG_PERF_EVENTS=y
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# CONFIG_VM_EVENT_COUNTERS is not set
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# CONFIG_SLUB_DEBUG is not set
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# CONFIG_COMPAT_BRK is not set
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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# CONFIG_IOSCHED_CFQ is not set
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CONFIG_ARCH_BCMRING=y
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CONFIG_BCM_ZRELADDR=0x8000
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CONFIG_CPU_32v6K=y
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CONFIG_NO_HZ=y
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CONFIG_PREEMPT=y
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CONFIG_AEABI=y
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# CONFIG_OABI_COMPAT is not set
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CONFIG_UACCESS_WITH_MEMCPY=y
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CONFIG_ZBOOT_ROM_TEXT=0x0e000000
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CONFIG_ZBOOT_ROM_BSS=0x0ea00000
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CONFIG_ZBOOT_ROM=y
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CONFIG_NET=y
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# CONFIG_WIRELESS is not set
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CONFIG_MTD=y
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CONFIG_MTD_CONCAT=y
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CONFIG_MTD_PARTITIONS=y
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_CHAR=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_ADV_OPTIONS=y
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CONFIG_MTD_CFI_GEOMETRY=y
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# CONFIG_MTD_CFI_I2 is not set
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_VERIFY_WRITE=y
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CONFIG_MTD_NAND_BCM_UMI=y
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CONFIG_MTD_NAND_BCM_UMI_HWCS=y
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# CONFIG_MISC_DEVICES is not set
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# CONFIG_INPUT_MOUSEDEV is not set
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_SERIO is not set
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# CONFIG_CONSOLE_TRANSLATIONS is not set
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# CONFIG_DEVKMEM is not set
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CONFIG_SERIAL_AMBA_PL011=y
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CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
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CONFIG_LEGACY_PTY_COUNT=64
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# CONFIG_HW_RANDOM is not set
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# CONFIG_HWMON is not set
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# CONFIG_VGA_CONSOLE is not set
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# CONFIG_HID_SUPPORT is not set
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# CONFIG_USB_SUPPORT is not set
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# CONFIG_FILE_LOCKING is not set
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# CONFIG_DNOTIFY is not set
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# CONFIG_INOTIFY_USER is not set
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# CONFIG_PROC_PAGE_MONITOR is not set
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CONFIG_TMPFS=y
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CONFIG_JFFS2_FS=y
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CONFIG_JFFS2_SUMMARY=y
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CONFIG_JFFS2_FS_XATTR=y
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# CONFIG_JFFS2_FS_SECURITY is not set
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# CONFIG_NETWORK_FILESYSTEMS is not set
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# CONFIG_ENABLE_WARN_DEPRECATED is not set
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CONFIG_MAGIC_SYSRQ=y
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CONFIG_HEADERS_CHECK=y
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# CONFIG_RCU_CPU_STALL_DETECTOR is not set
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# CONFIG_ARM_UNWIND is not set
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@@ -1,19 +0,0 @@
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choice
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prompt "Processor selection in BCMRING family of devices"
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depends on ARCH_BCMRING
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default ARCH_BCM11107
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config ARCH_FPGA11107
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bool "FPGA11107"
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config ARCH_BCM11107
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bool "BCM11107"
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endchoice
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menu "BCMRING Options"
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depends on ARCH_BCMRING
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config BCM_ZRELADDR
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hex "Compressed ZREL ADDR"
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endmenu
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@@ -1,8 +0,0 @@
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#
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# Makefile for the linux kernel.
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#
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# Object file lists.
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obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
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obj-y += csp/
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@@ -1,6 +0,0 @@
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# Address where decompressor will be written and eventually executed.
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#
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# default to SDRAM
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zreladdr-y += $(CONFIG_BCM_ZRELADDR)
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params_phys-y := 0x00000800
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@@ -1,199 +0,0 @@
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/*****************************************************************************
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* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <linux/proc_fs.h>
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#include <linux/sysctl.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/time.h>
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#include <asm/pmu.h>
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#include <asm/mach/arch.h>
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#include <mach/dma.h>
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#include <mach/hardware.h>
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#include <mach/csp/mm_io.h>
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#include <mach/csp/chipcHw_def.h>
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#include <mach/csp/chipcHw_inline.h>
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#include <cfg_global.h>
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#include "core.h"
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HW_DECLARE_SPINLOCK(arch)
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HW_DECLARE_SPINLOCK(gpio)
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#if defined(CONFIG_DEBUG_SPINLOCK)
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EXPORT_SYMBOL(bcmring_gpio_reg_lock);
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#endif
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/* sysctl */
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static int bcmring_arch_warm_reboot; /* do a warm reboot on hard reset */
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static void bcmring_restart(char mode, const char *cmd)
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{
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printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
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if (mode == 'h') {
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/* Reboot configured in proc entry */
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if (bcmring_arch_warm_reboot) {
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printk("warm reset\n");
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/* Issue Warm reset (do not reset ethernet switch, keep alive) */
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chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
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} else {
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/* Force reset of everything */
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printk("force reset\n");
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chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
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}
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} else {
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/* Force reset of everything */
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printk("force reset\n");
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chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
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}
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}
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static struct ctl_table_header *bcmring_sysctl_header;
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static struct ctl_table bcmring_sysctl_warm_reboot[] = {
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{
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.procname = "warm",
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.data = &bcmring_arch_warm_reboot,
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.maxlen = sizeof(int),
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.mode = 0644,
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.proc_handler = proc_dointvec},
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{}
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};
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static struct ctl_table bcmring_sysctl_reboot[] = {
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{
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.procname = "reboot",
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.mode = 0555,
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.child = bcmring_sysctl_warm_reboot},
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{}
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};
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static struct resource nand_resource[] = {
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[0] = {
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.start = MM_ADDR_IO_NAND,
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.end = MM_ADDR_IO_NAND + 0x1000 - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device nand_device = {
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.name = "bcm-nand",
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.id = -1,
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.resource = nand_resource,
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.num_resources = ARRAY_SIZE(nand_resource),
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};
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static struct resource pmu_resource = {
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.start = IRQ_PMUIRQ,
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.end = IRQ_PMUIRQ,
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.flags = IORESOURCE_IRQ,
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};
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static struct platform_device pmu_device = {
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.name = "arm-pmu",
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.id = ARM_PMU_DEVICE_CPU,
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.resource = &pmu_resource,
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.num_resources = 1,
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};
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static struct platform_device *devices[] __initdata = {
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&nand_device,
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&pmu_device,
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};
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/****************************************************************************
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*
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* Called from the customize_machine function in arch/arm/kernel/setup.c
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*
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* The customize_machine function is tagged as an arch_initcall
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* (see include/linux/init.h for the order that the various init sections
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* are called in.
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*
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*****************************************************************************/
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static void __init bcmring_init_machine(void)
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{
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bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
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/* Enable spread spectrum */
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chipcHw_enableSpreadSpectrum();
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platform_add_devices(devices, ARRAY_SIZE(devices));
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bcmring_amba_init();
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dma_init();
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}
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/****************************************************************************
|
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*
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* Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
|
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* passed in by the boot loader.
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*
|
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*****************************************************************************/
|
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static void __init bcmring_fixup(struct tag *t, char **cmdline,
|
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struct meminfo *mi) {
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#ifdef CONFIG_BLK_DEV_INITRD
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printk(KERN_NOTICE "bcmring_fixup\n");
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t->hdr.tag = ATAG_CORE;
|
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t->hdr.size = tag_size(tag_core);
|
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t->u.core.flags = 0;
|
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t->u.core.pagesize = PAGE_SIZE;
|
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t->u.core.rootdev = 31 << 8 | 0;
|
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t = tag_next(t);
|
||||
|
||||
t->hdr.tag = ATAG_MEM;
|
||||
t->hdr.size = tag_size(tag_mem32);
|
||||
t->u.mem.start = CFG_GLOBAL_RAM_BASE;
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t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
|
||||
|
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t = tag_next(t);
|
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|
||||
t->hdr.tag = ATAG_NONE;
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t->hdr.size = 0;
|
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#endif
|
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}
|
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|
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/****************************************************************************
|
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*
|
||||
* Machine Description
|
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*
|
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*****************************************************************************/
|
||||
|
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MACHINE_START(BCMRING, "BCMRING")
|
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/* Maintainer: Broadcom Corporation */
|
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.fixup = bcmring_fixup,
|
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.map_io = bcmring_map_io,
|
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.init_early = bcmring_init_early,
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.init_irq = bcmring_init_irq,
|
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.timer = &bcmring_timer,
|
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.init_machine = bcmring_init_machine,
|
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.restart = bcmring_restart,
|
||||
MACHINE_END
|
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@@ -1,223 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available at
|
||||
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* consent.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/csp/hw_cfg.h>
|
||||
#include <mach/csp/chipcHw_def.h>
|
||||
#include <mach/csp/chipcHw_reg.h>
|
||||
#include <mach/csp/chipcHw_inline.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
|
||||
#define clk_is_pll1(x) ((x)->type & CLK_TYPE_PLL1)
|
||||
#define clk_is_pll2(x) ((x)->type & CLK_TYPE_PLL2)
|
||||
#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
|
||||
#define clk_is_bypassable(x) ((x)->type & CLK_TYPE_BYPASSABLE)
|
||||
|
||||
#define clk_is_using_xtal(x) ((x)->mode & CLK_MODE_XTAL)
|
||||
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
||||
static void __clk_enable(struct clk *clk)
|
||||
{
|
||||
if (!clk)
|
||||
return;
|
||||
|
||||
/* enable parent clock first */
|
||||
if (clk->parent)
|
||||
__clk_enable(clk->parent);
|
||||
|
||||
if (clk->use_cnt++ == 0) {
|
||||
if (clk_is_pll1(clk)) { /* PLL1 */
|
||||
chipcHw_pll1Enable(clk->rate_hz, 0);
|
||||
} else if (clk_is_pll2(clk)) { /* PLL2 */
|
||||
chipcHw_pll2Enable(clk->rate_hz);
|
||||
} else if (clk_is_using_xtal(clk)) { /* source is crystal */
|
||||
if (!clk_is_primary(clk))
|
||||
chipcHw_bypassClockEnable(clk->csp_id);
|
||||
} else { /* source is PLL */
|
||||
chipcHw_setClockEnable(clk->csp_id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int clk_enable(struct clk *clk)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (!clk)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&clk_lock, flags);
|
||||
__clk_enable(clk);
|
||||
spin_unlock_irqrestore(&clk_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_enable);
|
||||
|
||||
static void __clk_disable(struct clk *clk)
|
||||
{
|
||||
if (!clk)
|
||||
return;
|
||||
|
||||
BUG_ON(clk->use_cnt == 0);
|
||||
|
||||
if (--clk->use_cnt == 0) {
|
||||
if (clk_is_pll1(clk)) { /* PLL1 */
|
||||
chipcHw_pll1Disable();
|
||||
} else if (clk_is_pll2(clk)) { /* PLL2 */
|
||||
chipcHw_pll2Disable();
|
||||
} else if (clk_is_using_xtal(clk)) { /* source is crystal */
|
||||
if (!clk_is_primary(clk))
|
||||
chipcHw_bypassClockDisable(clk->csp_id);
|
||||
} else { /* source is PLL */
|
||||
chipcHw_setClockDisable(clk->csp_id);
|
||||
}
|
||||
}
|
||||
|
||||
if (clk->parent)
|
||||
__clk_disable(clk->parent);
|
||||
}
|
||||
|
||||
void clk_disable(struct clk *clk)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (!clk)
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&clk_lock, flags);
|
||||
__clk_disable(clk);
|
||||
spin_unlock_irqrestore(&clk_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_disable);
|
||||
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
if (!clk)
|
||||
return 0;
|
||||
|
||||
return clk->rate_hz;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_rate);
|
||||
|
||||
long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long actual;
|
||||
unsigned long rate_hz;
|
||||
|
||||
if (!clk)
|
||||
return -EINVAL;
|
||||
|
||||
if (!clk_is_programmable(clk))
|
||||
return -EINVAL;
|
||||
|
||||
if (clk->use_cnt)
|
||||
return -EBUSY;
|
||||
|
||||
spin_lock_irqsave(&clk_lock, flags);
|
||||
actual = clk->parent->rate_hz;
|
||||
rate_hz = min(actual, rate);
|
||||
spin_unlock_irqrestore(&clk_lock, flags);
|
||||
|
||||
return rate_hz;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_round_rate);
|
||||
|
||||
int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long actual;
|
||||
unsigned long rate_hz;
|
||||
|
||||
if (!clk)
|
||||
return -EINVAL;
|
||||
|
||||
if (!clk_is_programmable(clk))
|
||||
return -EINVAL;
|
||||
|
||||
if (clk->use_cnt)
|
||||
return -EBUSY;
|
||||
|
||||
spin_lock_irqsave(&clk_lock, flags);
|
||||
actual = clk->parent->rate_hz;
|
||||
rate_hz = min(actual, rate);
|
||||
rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
|
||||
clk->rate_hz = rate_hz;
|
||||
spin_unlock_irqrestore(&clk_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_rate);
|
||||
|
||||
struct clk *clk_get_parent(struct clk *clk)
|
||||
{
|
||||
if (!clk)
|
||||
return NULL;
|
||||
|
||||
return clk->parent;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_parent);
|
||||
|
||||
int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct clk *old_parent;
|
||||
|
||||
if (!clk || !parent)
|
||||
return -EINVAL;
|
||||
|
||||
if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
|
||||
return -EINVAL;
|
||||
|
||||
/* if more than one user, parent is not allowed */
|
||||
if (clk->use_cnt > 1)
|
||||
return -EBUSY;
|
||||
|
||||
if (clk->parent == parent)
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(&clk_lock, flags);
|
||||
old_parent = clk->parent;
|
||||
clk->parent = parent;
|
||||
if (clk_is_using_xtal(parent))
|
||||
clk->mode |= CLK_MODE_XTAL;
|
||||
else
|
||||
clk->mode &= (~CLK_MODE_XTAL);
|
||||
|
||||
/* if clock is active */
|
||||
if (clk->use_cnt != 0) {
|
||||
clk->use_cnt--;
|
||||
/* enable clock with the new parent */
|
||||
__clk_enable(clk);
|
||||
/* disable the old parent */
|
||||
__clk_disable(old_parent);
|
||||
}
|
||||
spin_unlock_irqrestore(&clk_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_parent);
|
||||
@@ -1,33 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available at
|
||||
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* consent.
|
||||
*****************************************************************************/
|
||||
#include <mach/csp/chipcHw_def.h>
|
||||
|
||||
#define CLK_TYPE_PRIMARY 1 /* primary clock must NOT have a parent */
|
||||
#define CLK_TYPE_PLL1 2 /* PPL1 */
|
||||
#define CLK_TYPE_PLL2 4 /* PPL2 */
|
||||
#define CLK_TYPE_PROGRAMMABLE 8 /* programmable clock rate */
|
||||
#define CLK_TYPE_BYPASSABLE 16 /* parent can be changed */
|
||||
|
||||
#define CLK_MODE_XTAL 1 /* clock source is from crystal */
|
||||
|
||||
struct clk {
|
||||
const char *name; /* clock name */
|
||||
unsigned int type; /* clock type */
|
||||
unsigned int mode; /* current mode */
|
||||
volatile int use_bypass; /* indicate if it's in bypass mode */
|
||||
chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */
|
||||
unsigned long rate_hz; /* clock rate in Hz */
|
||||
unsigned int use_cnt; /* usage count */
|
||||
struct clk *parent; /* parent clock */
|
||||
};
|
||||
@@ -1,228 +0,0 @@
|
||||
/*
|
||||
* derived from linux/arch/arm/mach-versatile/core.c
|
||||
* linux/arch/arm/mach-bcmring/core.c
|
||||
*
|
||||
* Copyright (C) 1999 - 2003 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
/* Portions copyright Broadcom 2008 */
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
#include <mach/csp/mm_addr.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/hardware/arm_timer.h>
|
||||
#include <asm/hardware/timer-sp.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/flash.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <cfg_global.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
#include <csp/secHw.h>
|
||||
#include <mach/csp/secHw_def.h>
|
||||
#include <mach/csp/chipcHw_inline.h>
|
||||
#include <mach/csp/tmrHw_reg.h>
|
||||
|
||||
static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
|
||||
static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
|
||||
|
||||
static struct clk pll1_clk = {
|
||||
.name = "PLL1",
|
||||
.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
|
||||
.rate_hz = 2000000000,
|
||||
.use_cnt = 7,
|
||||
};
|
||||
|
||||
static struct clk uart_clk = {
|
||||
.name = "UART",
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.csp_id = chipcHw_CLOCK_UART,
|
||||
.rate_hz = HW_CFG_UART_CLK_HZ,
|
||||
.parent = &pll1_clk,
|
||||
};
|
||||
|
||||
static struct clk dummy_apb_pclk = {
|
||||
.name = "BUSCLK",
|
||||
.type = CLK_TYPE_PRIMARY,
|
||||
.mode = CLK_MODE_XTAL,
|
||||
};
|
||||
|
||||
/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
|
||||
#if defined(CONFIG_ARCH_FPGA11107)
|
||||
/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
|
||||
/* slow down Linux's sense of time */
|
||||
#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
|
||||
#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
|
||||
#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
|
||||
#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
|
||||
#else
|
||||
#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
|
||||
#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
|
||||
#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
|
||||
#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
|
||||
#endif
|
||||
|
||||
static struct clk sp804_timer012_clk = {
|
||||
.name = "sp804-timer-0,1,2",
|
||||
.type = CLK_TYPE_PRIMARY,
|
||||
.mode = CLK_MODE_XTAL,
|
||||
.rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
|
||||
};
|
||||
|
||||
static struct clk sp804_timer3_clk = {
|
||||
.name = "sp804-timer-3",
|
||||
.type = CLK_TYPE_PRIMARY,
|
||||
.mode = CLK_MODE_XTAL,
|
||||
.rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
{ /* Bus clock */
|
||||
.con_id = "apb_pclk",
|
||||
.clk = &dummy_apb_pclk,
|
||||
}, { /* UART0 */
|
||||
.dev_id = "uarta",
|
||||
.clk = &uart_clk,
|
||||
}, { /* UART1 */
|
||||
.dev_id = "uartb",
|
||||
.clk = &uart_clk,
|
||||
}, { /* SP804 timer 0 */
|
||||
.dev_id = "sp804",
|
||||
.con_id = "timer0",
|
||||
.clk = &sp804_timer012_clk,
|
||||
}, { /* SP804 timer 1 */
|
||||
.dev_id = "sp804",
|
||||
.con_id = "timer1",
|
||||
.clk = &sp804_timer012_clk,
|
||||
}, { /* SP804 timer 3 */
|
||||
.dev_id = "sp804",
|
||||
.con_id = "timer3",
|
||||
.clk = &sp804_timer3_clk,
|
||||
}
|
||||
};
|
||||
|
||||
static struct amba_device *amba_devs[] __initdata = {
|
||||
&uartA_device,
|
||||
&uartB_device,
|
||||
};
|
||||
|
||||
void __init bcmring_amba_init(void)
|
||||
{
|
||||
int i;
|
||||
u32 bus_clock;
|
||||
|
||||
/* Linux is run initially in non-secure mode. Secure peripherals */
|
||||
/* generate FIQ, and must be handled in secure mode. Until we have */
|
||||
/* a linux security monitor implementation, keep everything in */
|
||||
/* non-secure mode. */
|
||||
chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
|
||||
secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
|
||||
secHw_BLK_MASK_KEY_SCAN |
|
||||
secHw_BLK_MASK_TOUCH_SCREEN |
|
||||
secHw_BLK_MASK_UART0 |
|
||||
secHw_BLK_MASK_UART1 |
|
||||
secHw_BLK_MASK_WATCHDOG |
|
||||
secHw_BLK_MASK_SPUM |
|
||||
secHw_BLK_MASK_DDR2 |
|
||||
secHw_BLK_MASK_SPU |
|
||||
secHw_BLK_MASK_PKA |
|
||||
secHw_BLK_MASK_RNG |
|
||||
secHw_BLK_MASK_RTC |
|
||||
secHw_BLK_MASK_OTP |
|
||||
secHw_BLK_MASK_BOOT |
|
||||
secHw_BLK_MASK_MPU |
|
||||
secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
|
||||
|
||||
/* Only the devices attached to the AMBA bus are enabled just before the bus is */
|
||||
/* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
|
||||
/* driver to access these blocks. The bus is probed, and the drivers are loaded. */
|
||||
/* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
|
||||
bus_clock = chipcHw_REG_BUS_CLOCK_GE
|
||||
| chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
|
||||
|
||||
chipcHw_busInterfaceClockEnable(bus_clock);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
|
||||
struct amba_device *d = amba_devs[i];
|
||||
amba_device_register(d, &iomem_resource);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Where is the timer (VA)?
|
||||
*/
|
||||
#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR)
|
||||
#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
|
||||
#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
|
||||
#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
|
||||
|
||||
static int __init bcmring_clocksource_init(void)
|
||||
{
|
||||
/* setup timer1 as free-running clocksource */
|
||||
sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
|
||||
|
||||
/* setup timer3 as free-running clocksource */
|
||||
sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up timer interrupt, and return the current time in seconds.
|
||||
*/
|
||||
void __init bcmring_init_timer(void)
|
||||
{
|
||||
printk(KERN_INFO "bcmring_init_timer\n");
|
||||
/*
|
||||
* Initialise to a known state (all timers off)
|
||||
*/
|
||||
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
|
||||
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
|
||||
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
|
||||
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
|
||||
|
||||
/*
|
||||
* Make irqs happen for the system timer
|
||||
*/
|
||||
bcmring_clocksource_init();
|
||||
|
||||
sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
|
||||
}
|
||||
|
||||
struct sys_timer bcmring_timer = {
|
||||
.init = bcmring_init_timer,
|
||||
};
|
||||
|
||||
void __init bcmring_init_early(void)
|
||||
{
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
}
|
||||
@@ -1,31 +0,0 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-versatile/core.h
|
||||
*
|
||||
* Copyright (C) 2004 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
/* Portions copyright Broadcom 2008 */
|
||||
#ifndef __ASM_ARCH_BCMRING_H
|
||||
#define __ASM_ARCH_BCMRING_H
|
||||
|
||||
void __init bcmring_amba_init(void);
|
||||
void __init bcmring_map_io(void);
|
||||
void __init bcmring_init_irq(void);
|
||||
void __init bcmring_init_early(void);
|
||||
|
||||
extern struct sys_timer bcmring_timer;
|
||||
#endif
|
||||
@@ -1,3 +0,0 @@
|
||||
obj-y += dmac/
|
||||
obj-y += tmr/
|
||||
obj-y += chipc/
|
||||
@@ -1 +0,0 @@
|
||||
obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,293 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available at
|
||||
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* consent.
|
||||
*****************************************************************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* @file chipcHw_init.c
|
||||
*
|
||||
* @brief Low level CHIPC PLL configuration functions
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* These routines provide basic PLL controlling functionality only.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
/* ---- Include Files ---------------------------------------------------- */
|
||||
|
||||
#include <csp/errno.h>
|
||||
#include <csp/stdint.h>
|
||||
#include <csp/module.h>
|
||||
|
||||
#include <mach/csp/chipcHw_def.h>
|
||||
#include <mach/csp/chipcHw_inline.h>
|
||||
|
||||
#include <csp/reg.h>
|
||||
#include <csp/delay.h>
|
||||
/* ---- Private Constants and Types --------------------------------------- */
|
||||
|
||||
/*
|
||||
Calculation for NDIV_i to obtain VCO frequency
|
||||
-----------------------------------------------
|
||||
|
||||
Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
|
||||
for Freq_vco = VCO_FREQ_MHz
|
||||
Freq_ref = chipcHw_XTAL_FREQ_Hz
|
||||
PLL_P1 = PLL_P2 = 1
|
||||
and
|
||||
PLL_NDIV_f = 0
|
||||
|
||||
We get:
|
||||
PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
|
||||
|
||||
Calculation for PLL MDIV to obtain frequency Freq_x for channel x
|
||||
-----------------------------------------------------------------
|
||||
Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
|
||||
|
||||
PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
|
||||
*/
|
||||
|
||||
/* ---- Private Variables ------------------------------------------------- */
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* @brief Initializes the PLL2
|
||||
*
|
||||
* This function initializes the PLL2
|
||||
*
|
||||
*/
|
||||
/****************************************************************************/
|
||||
void chipcHw_pll2Enable(uint32_t vcoFreqHz)
|
||||
{
|
||||
uint32_t pllPreDivider2 = 0;
|
||||
|
||||
{
|
||||
REG_LOCAL_IRQ_SAVE;
|
||||
pChipcHw->PLLConfig2 =
|
||||
chipcHw_REG_PLL_CONFIG_D_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_A_RESET;
|
||||
|
||||
pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
|
||||
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
|
||||
(chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
|
||||
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
|
||||
(chipcHw_REG_PLL_PREDIVIDER_P1 <<
|
||||
chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
|
||||
(chipcHw_REG_PLL_PREDIVIDER_P2 <<
|
||||
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
|
||||
|
||||
/* Enable CHIPC registers to control the PLL */
|
||||
pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
|
||||
|
||||
/* Set pre divider to get desired VCO frequency */
|
||||
pChipcHw->PLLPreDivider2 = pllPreDivider2;
|
||||
/* Set NDIV Frac */
|
||||
pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
|
||||
|
||||
/* This has to be removed once the default values are fixed for PLL2. */
|
||||
pChipcHw->PLLControl12 = 0x38000700;
|
||||
pChipcHw->PLLControl22 = 0x00000015;
|
||||
|
||||
/* Reset PLL2 */
|
||||
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
|
||||
pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_A_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
|
||||
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
|
||||
} else {
|
||||
pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_A_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
|
||||
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
|
||||
}
|
||||
REG_LOCAL_IRQ_RESTORE;
|
||||
}
|
||||
|
||||
/* Insert certain amount of delay before deasserting ARESET. */
|
||||
udelay(1);
|
||||
|
||||
{
|
||||
REG_LOCAL_IRQ_SAVE;
|
||||
/* Remove analog reset and Power on the PLL */
|
||||
pChipcHw->PLLConfig2 &=
|
||||
~(chipcHw_REG_PLL_CONFIG_A_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_POWER_DOWN);
|
||||
|
||||
REG_LOCAL_IRQ_RESTORE;
|
||||
|
||||
}
|
||||
|
||||
/* Wait until PLL is locked */
|
||||
while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
|
||||
;
|
||||
|
||||
{
|
||||
REG_LOCAL_IRQ_SAVE;
|
||||
/* Remove digital reset */
|
||||
pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
|
||||
|
||||
REG_LOCAL_IRQ_RESTORE;
|
||||
}
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(chipcHw_pll2Enable);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* @brief Initializes the PLL1
|
||||
*
|
||||
* This function initializes the PLL1
|
||||
*
|
||||
*/
|
||||
/****************************************************************************/
|
||||
void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
|
||||
{
|
||||
uint32_t pllPreDivider = 0;
|
||||
|
||||
{
|
||||
REG_LOCAL_IRQ_SAVE;
|
||||
|
||||
pChipcHw->PLLConfig =
|
||||
chipcHw_REG_PLL_CONFIG_D_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_A_RESET;
|
||||
/* Setting VCO frequency */
|
||||
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
|
||||
pllPreDivider =
|
||||
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
|
||||
((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
|
||||
1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
|
||||
(chipcHw_REG_PLL_PREDIVIDER_P1 <<
|
||||
chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
|
||||
(chipcHw_REG_PLL_PREDIVIDER_P2 <<
|
||||
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
|
||||
} else {
|
||||
pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
|
||||
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
|
||||
(chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
|
||||
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
|
||||
(chipcHw_REG_PLL_PREDIVIDER_P1 <<
|
||||
chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
|
||||
(chipcHw_REG_PLL_PREDIVIDER_P2 <<
|
||||
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
|
||||
}
|
||||
|
||||
/* Enable CHIPC registers to control the PLL */
|
||||
pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
|
||||
|
||||
/* Set pre divider to get desired VCO frequency */
|
||||
pChipcHw->PLLPreDivider = pllPreDivider;
|
||||
/* Set NDIV Frac */
|
||||
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
|
||||
pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
|
||||
chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
|
||||
} else {
|
||||
pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
|
||||
chipcHw_REG_PLL_DIVIDER_NDIV_f;
|
||||
}
|
||||
|
||||
/* Reset PLL1 */
|
||||
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
|
||||
pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_A_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
|
||||
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
|
||||
} else {
|
||||
pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_A_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
|
||||
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
|
||||
}
|
||||
|
||||
REG_LOCAL_IRQ_RESTORE;
|
||||
|
||||
/* Insert certain amount of delay before deasserting ARESET. */
|
||||
udelay(1);
|
||||
|
||||
{
|
||||
REG_LOCAL_IRQ_SAVE;
|
||||
/* Remove analog reset and Power on the PLL */
|
||||
pChipcHw->PLLConfig &=
|
||||
~(chipcHw_REG_PLL_CONFIG_A_RESET |
|
||||
chipcHw_REG_PLL_CONFIG_POWER_DOWN);
|
||||
REG_LOCAL_IRQ_RESTORE;
|
||||
}
|
||||
|
||||
/* Wait until PLL is locked */
|
||||
while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
|
||||
|| !(pChipcHw->
|
||||
PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
|
||||
;
|
||||
|
||||
/* Remove digital reset */
|
||||
{
|
||||
REG_LOCAL_IRQ_SAVE;
|
||||
pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
|
||||
REG_LOCAL_IRQ_RESTORE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(chipcHw_pll1Enable);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* @brief Initializes the chipc module
|
||||
*
|
||||
* This function initializes the PLLs and core system clocks
|
||||
*
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */
|
||||
) {
|
||||
#if !(defined(__KERNEL__) && !defined(STANDALONE))
|
||||
delay_init();
|
||||
#endif
|
||||
|
||||
/* Do not program PLL, when warm reset */
|
||||
if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
|
||||
chipcHw_pll1Enable(initParam->pllVcoFreqHz,
|
||||
initParam->ssSupport);
|
||||
chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
|
||||
} else {
|
||||
/* Clear sticky bits */
|
||||
chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
|
||||
}
|
||||
/* Clear sticky bits */
|
||||
chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
|
||||
|
||||
/* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
|
||||
pChipcHw->ACLKClock =
|
||||
(pChipcHw->
|
||||
ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
|
||||
armBusRatio &
|
||||
chipcHw_REG_ACLKClock_CLK_DIV_MASK);
|
||||
|
||||
/* Set various core component frequencies. The order in which this is done is important for some. */
|
||||
/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
|
||||
/* frequency to find its ratio with the BUS. Hence we must set the ARM first, followed by the BUS, */
|
||||
/* then VPM and RTBUS. */
|
||||
|
||||
chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
|
||||
initParam->busClockFreqHz *
|
||||
initParam->armBusRatio);
|
||||
chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
|
||||
chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
|
||||
initParam->busClockFreqHz *
|
||||
initParam->vpmBusRatio);
|
||||
chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
|
||||
initParam->busClockFreqHz *
|
||||
initParam->ddrBusRatio);
|
||||
chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
|
||||
initParam->busClockFreqHz / 2);
|
||||
}
|
||||
@@ -1,124 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available at
|
||||
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* consent.
|
||||
*****************************************************************************/
|
||||
|
||||
/* ---- Include Files ---------------------------------------------------- */
|
||||
#include <csp/stdint.h>
|
||||
#include <mach/csp/chipcHw_def.h>
|
||||
#include <mach/csp/chipcHw_inline.h>
|
||||
#include <csp/intcHw.h>
|
||||
#include <csp/cache.h>
|
||||
|
||||
/* ---- Private Constants and Types --------------------------------------- */
|
||||
/* ---- Private Variables ------------------------------------------------- */
|
||||
void chipcHw_reset_run_from_aram(void);
|
||||
|
||||
typedef void (*RUNFUNC) (void);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* @brief warmReset
|
||||
*
|
||||
* @note warmReset configures the clocks which are not reset back to the state
|
||||
* required to execute on reset. To do so we need to copy the code into internal
|
||||
* memory to change the ARM clock while we are not executing from DDR.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
void chipcHw_reset(uint32_t mask)
|
||||
{
|
||||
int i = 0;
|
||||
RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
|
||||
|
||||
/* Disable all interrupts */
|
||||
intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
|
||||
intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
|
||||
intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
|
||||
|
||||
{
|
||||
REG_LOCAL_IRQ_SAVE;
|
||||
if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
|
||||
chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
|
||||
}
|
||||
/* Bypass the PLL clocks before reboot */
|
||||
pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
|
||||
pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
|
||||
|
||||
/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
|
||||
do {
|
||||
((uint32_t *) MM_IO_BASE_ARAM)[i] =
|
||||
((uint32_t *) &chipcHw_reset_run_from_aram)[i];
|
||||
i++;
|
||||
} while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
|
||||
|
||||
CSP_CACHE_FLUSH_ALL;
|
||||
|
||||
/* run the function from ARAM */
|
||||
runFunc();
|
||||
|
||||
/* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
|
||||
REG_LOCAL_IRQ_RESTORE;
|
||||
}
|
||||
}
|
||||
|
||||
/* This function must run from internal memory */
|
||||
void chipcHw_reset_run_from_aram(void)
|
||||
{
|
||||
/* Make sure, pipeline is filled with instructions coming from ARAM */
|
||||
__asm (" nop \n\t"
|
||||
" nop \n\t"
|
||||
#if defined(__KERNEL__) && !defined(STANDALONE)
|
||||
" MRC p15,#0x0,r0,c1,c0,#0 \n\t"
|
||||
" BIC r0,r0,#0xd \n\t"
|
||||
" MCR p15,#0x0,r0,c1,c0,#0 \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
#endif
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
/* Bypass the ARM clock and switch to XTAL clock */
|
||||
" MOV r2,#0x80000000 \n\t"
|
||||
" LDR r3,[r2,#8] \n\t"
|
||||
" ORR r3,r3,#0x20000 \n\t"
|
||||
" STR r3,[r2,#8] \n\t"
|
||||
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
" nop \n\t"
|
||||
/* Issue reset */
|
||||
" MOV r3,#0x2 \n\t"
|
||||
" STR r3,[r2,#0x80] \n\t"
|
||||
/* End here */
|
||||
" MOV pc,pc \n\t");
|
||||
/* 0xe1a0f00f == asm ("mov r15, r15"); */
|
||||
}
|
||||
@@ -1,64 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* Copyright 2008 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available at
|
||||
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* consent.
|
||||
*****************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* @file chipcHw_str.c
|
||||
*
|
||||
* @brief Contains strings which are useful to linux and csp
|
||||
*
|
||||
* @note
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
/* ---- Include Files ---------------------------------------------------- */
|
||||
|
||||
#include <mach/csp/chipcHw_inline.h>
|
||||
|
||||
/* ---- Private Constants and Types --------------------------------------- */
|
||||
|
||||
static const char *gMuxStr[] = {
|
||||
"GPIO", /* 0 */
|
||||
"KeyPad", /* 1 */
|
||||
"I2C-Host", /* 2 */
|
||||
"SPI", /* 3 */
|
||||
"Uart", /* 4 */
|
||||
"LED-Mtx-P", /* 5 */
|
||||
"LED-Mtx-S", /* 6 */
|
||||
"SDIO-0", /* 7 */
|
||||
"SDIO-1", /* 8 */
|
||||
"PCM", /* 9 */
|
||||
"I2S", /* 10 */
|
||||
"ETM", /* 11 */
|
||||
"Debug", /* 12 */
|
||||
"Misc", /* 13 */
|
||||
"0xE", /* 14 */
|
||||
"0xF", /* 15 */
|
||||
};
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* @brief Retrieves a string representation of the mux setting for a pin.
|
||||
*
|
||||
* @return Pointer to a character string.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
const char *chipcHw_getGpioPinFunctionStr(int pin)
|
||||
{
|
||||
if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
|
||||
return "";
|
||||
}
|
||||
|
||||
return gMuxStr[chipcHw_getGpioPinFunction(pin)];
|
||||
}
|
||||
@@ -1 +0,0 @@
|
||||
obj-y += dmacHw.o dmacHw_extra.o
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user