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Enable a suitable ISA for the assembler around ll/sc so that code
builds even for processors that don't support the instructions. Plus minor formatting fixes. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki
committed by
Ralf Baechle
Ralf Baechle
parent
fded2e508a
commit
aac8aa7717
+50
-24
@@ -18,14 +18,16 @@
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#if (_MIPS_SZLONG == 32)
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#define SZLONG_LOG 5
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#define SZLONG_MASK 31UL
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#define __LL "ll "
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#define __SC "sc "
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#define __LL "ll "
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#define __SC "sc "
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#define __SET_MIPS ".set mips2 "
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#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
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#elif (_MIPS_SZLONG == 64)
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#define SZLONG_LOG 6
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#define SZLONG_MASK 63UL
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#define __LL "lld "
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#define __SC "scd "
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#define __LL "lld "
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#define __SC "scd "
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#define __SET_MIPS ".set mips3 "
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#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
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#endif
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@@ -72,18 +74,22 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # set_bit \n"
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" or %0, %2 \n"
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" "__SC "%0, %1 \n"
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" " __SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # set_bit \n"
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" or %0, %2 \n"
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" "__SC "%0, %1 \n"
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" " __SC "%0, %1 \n"
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" beqz %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else {
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@@ -132,18 +138,22 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # clear_bit \n"
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" and %0, %2 \n"
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" " __SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # clear_bit \n"
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" and %0, %2 \n"
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" " __SC "%0, %1 \n"
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" beqz %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
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} else {
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@@ -191,10 +201,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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unsigned long temp;
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__asm__ __volatile__(
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # change_bit \n"
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" xor %0, %2 \n"
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" "__SC "%0, %1 \n"
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" " __SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else if (cpu_has_llsc) {
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@@ -202,10 +214,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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unsigned long temp;
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__asm__ __volatile__(
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # change_bit \n"
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" xor %0, %2 \n"
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" "__SC "%0, %1 \n"
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" " __SC "%0, %1 \n"
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" beqz %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else {
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@@ -253,14 +267,16 @@ static inline int test_and_set_bit(unsigned long nr,
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unsigned long temp, res;
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__asm__ __volatile__(
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # test_and_set_bit \n"
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" or %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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"sync \n"
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" sync \n"
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#endif
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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@@ -271,16 +287,18 @@ static inline int test_and_set_bit(unsigned long nr,
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set noreorder # test_and_set_bit \n"
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"1: " __LL "%0, %1 \n"
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" .set push \n"
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" .set noreorder \n"
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # test_and_set_bit \n"
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" or %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" beqz %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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"sync \n"
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" sync \n"
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#endif
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".set\treorder"
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" .set pop \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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@@ -343,15 +361,17 @@ static inline int test_and_clear_bit(unsigned long nr,
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unsigned long temp, res;
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__asm__ __volatile__(
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # test_and_clear_bit \n"
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" or %2, %0, %3 \n"
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" xor %2, %3 \n"
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__SC "%2, %1 \n"
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" " __SC "%2, %1 \n"
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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@@ -362,17 +382,19 @@ static inline int test_and_clear_bit(unsigned long nr,
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set noreorder # test_and_clear_bit \n"
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"1: " __LL "%0, %1 \n"
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" .set push \n"
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" .set noreorder \n"
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # test_and_clear_bit \n"
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" or %2, %0, %3 \n"
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" xor %2, %3 \n"
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__SC "%2, %1 \n"
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" " __SC "%2, %1 \n"
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" beqz %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set reorder \n"
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" .set pop \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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@@ -435,14 +457,16 @@ static inline int test_and_change_bit(unsigned long nr,
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unsigned long temp, res;
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__asm__ __volatile__(
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"1: " __LL " %0, %1 # test_and_change_bit \n"
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # test_and_change_bit \n"
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" xor %2, %0, %3 \n"
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" "__SC "%2, %1 \n"
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" " __SC "%2, %1 \n"
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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@@ -453,16 +477,18 @@ static inline int test_and_change_bit(unsigned long nr,
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set noreorder # test_and_change_bit \n"
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"1: " __LL " %0, %1 \n"
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" .set push \n"
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" .set noreorder \n"
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" " __SET_MIPS " \n"
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"1: " __LL "%0, %1 # test_and_change_bit \n"
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" xor %2, %0, %3 \n"
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" "__SC "\t%2, %1 \n"
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" " __SC "\t%2, %1 \n"
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" beqz %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set reorder \n"
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" .set pop \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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