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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem
Conflicts: drivers/net/wireless/libertas/if_cs.c drivers/net/wireless/rtlwifi/pci.c net/bluetooth/l2cap_sock.c
This commit is contained in:
John W. Linville
@@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
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if (!ccdev)
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return;
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bus = ccdev->bus;
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/* We support SLOW only on 6..9 */
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if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
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mode = SSB_CLKMODE_DYNAMIC;
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if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
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return; /* PMU controls clockmode, separated function needed */
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SSB_WARN_ON(ccdev->id.revision >= 20);
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/* chipcommon cores prior to rev6 don't support dynamic clock control */
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if (ccdev->id.revision < 6)
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return;
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/* chipcommon cores rev10 are a whole new ball game */
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/* ChipCommon cores rev10+ need testing */
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if (ccdev->id.revision >= 10)
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return;
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if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
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return;
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switch (mode) {
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case SSB_CLKMODE_SLOW:
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case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
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tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
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tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
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chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
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break;
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case SSB_CLKMODE_FAST:
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ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
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tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
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tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
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chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
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if (ccdev->id.revision < 10) {
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ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
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tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
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tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
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chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
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} else {
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chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
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(chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
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SSB_CHIPCO_SYSCLKCTL_FORCEHT));
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/* udelay(150); TODO: not available in early init */
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}
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break;
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case SSB_CLKMODE_DYNAMIC:
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tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
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if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
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tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
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chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
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if (ccdev->id.revision < 10) {
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tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
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if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
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SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
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tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
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chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
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/* for dynamic control, we have to release our xtal_pu "force on" */
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if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
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ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
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/* For dynamic control, we have to release our xtal_pu
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* "force on" */
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if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
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ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
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} else {
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chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
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(chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
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~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
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}
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break;
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default:
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SSB_WARN_ON(1);
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@@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc)
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if (cc->dev->id.revision >= 11)
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cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
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ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
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if (cc->dev->id.revision >= 20) {
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chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
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chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
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}
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ssb_pmu_init(cc);
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chipco_powercontrol_init(cc);
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ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
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@@ -423,6 +423,8 @@ static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
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switch (bus->chip_id) {
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case 0x4312:
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min_msk = 0xCBB;
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break;
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case 0x4322:
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/* We keep the default settings:
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* min_msk = 0xCBB
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@@ -21,6 +21,8 @@ static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
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static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
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u8 address, u16 data);
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static void ssb_commit_settings(struct ssb_bus *bus);
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static inline
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u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
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{
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@@ -412,6 +414,16 @@ static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
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* Workarounds.
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**************************************************/
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static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
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{
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u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
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if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
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tmp &= ~0xF000;
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tmp |= (pc->dev->core_index << 12);
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pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
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}
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}
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static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
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{
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return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
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@@ -430,6 +442,76 @@ static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
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ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
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}
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static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
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{
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struct ssb_device *pdev = pc->dev;
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struct ssb_bus *bus = pdev->bus;
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u32 tmp;
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tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
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tmp |= SSB_PCICORE_SBTOPCI_PREF;
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tmp |= SSB_PCICORE_SBTOPCI_BURST;
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
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if (pdev->id.revision < 5) {
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tmp = ssb_read32(pdev, SSB_IMCFGLO);
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tmp &= ~SSB_IMCFGLO_SERTO;
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tmp |= 2;
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tmp &= ~SSB_IMCFGLO_REQTO;
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tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
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ssb_write32(pdev, SSB_IMCFGLO, tmp);
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ssb_commit_settings(bus);
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} else if (pdev->id.revision >= 11) {
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tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
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tmp |= SSB_PCICORE_SBTOPCI_MRM;
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
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}
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}
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static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
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{
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u32 tmp;
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u8 rev = pc->dev->id.revision;
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if (rev == 0 || rev == 1) {
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/* TLP Workaround register. */
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tmp = ssb_pcie_read(pc, 0x4);
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tmp |= 0x8;
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ssb_pcie_write(pc, 0x4, tmp);
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}
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if (rev == 1) {
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/* DLLP Link Control register. */
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tmp = ssb_pcie_read(pc, 0x100);
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tmp |= 0x40;
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ssb_pcie_write(pc, 0x100, tmp);
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}
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if (rev == 0) {
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const u8 serdes_rx_device = 0x1F;
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ssb_pcie_mdio_write(pc, serdes_rx_device,
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2 /* Timer */, 0x8128);
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ssb_pcie_mdio_write(pc, serdes_rx_device,
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6 /* CDR */, 0x0100);
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ssb_pcie_mdio_write(pc, serdes_rx_device,
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7 /* CDR BW */, 0x1466);
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} else if (rev == 3 || rev == 4 || rev == 5) {
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/* TODO: DLLP Power Management Threshold */
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ssb_pcicore_serdes_workaround(pc);
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/* TODO: ASPM */
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} else if (rev == 7) {
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/* TODO: No PLL down */
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}
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if (rev >= 6) {
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/* Miscellaneous Configuration Fixup */
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tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
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if (!(tmp & 0x8000))
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pcicore_write16(pc, SSB_PCICORE_SPROM(5),
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tmp | 0x8000);
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}
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}
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/**************************************************
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* Generic and Clientmode operation code.
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**************************************************/
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@@ -449,6 +531,8 @@ void ssb_pcicore_init(struct ssb_pcicore *pc)
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if (!ssb_device_is_enabled(dev))
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ssb_device_enable(dev, 0);
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ssb_pcicore_fix_sprom_core_index(pc);
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#ifdef CONFIG_SSB_PCICORE_HOSTMODE
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pc->hostmode = pcicore_is_in_hostmode(pc);
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if (pc->hostmode)
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@@ -457,7 +541,10 @@ void ssb_pcicore_init(struct ssb_pcicore *pc)
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if (!pc->hostmode)
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ssb_pcicore_init_clientmode(pc);
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/* Additional always once-executed workarounds */
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ssb_pcicore_serdes_workaround(pc);
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/* TODO: ASPM */
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/* TODO: Clock Request Update */
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}
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static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
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@@ -522,7 +609,7 @@ static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
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pcicore_write32(pc, mdio_data, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < 200; i++) {
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for (i = 0; i < max_retries; i++) {
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v = pcicore_read32(pc, mdio_control);
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if (v & 0x100 /* Trans complete */) {
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udelay(10);
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@@ -646,48 +733,10 @@ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
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if (pc->setup_done)
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goto out;
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if (pdev->id.coreid == SSB_DEV_PCI) {
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tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
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tmp |= SSB_PCICORE_SBTOPCI_PREF;
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tmp |= SSB_PCICORE_SBTOPCI_BURST;
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
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if (pdev->id.revision < 5) {
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tmp = ssb_read32(pdev, SSB_IMCFGLO);
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tmp &= ~SSB_IMCFGLO_SERTO;
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tmp |= 2;
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tmp &= ~SSB_IMCFGLO_REQTO;
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tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
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ssb_write32(pdev, SSB_IMCFGLO, tmp);
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ssb_commit_settings(bus);
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} else if (pdev->id.revision >= 11) {
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tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
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tmp |= SSB_PCICORE_SBTOPCI_MRM;
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
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}
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ssb_pcicore_pci_setup_workarounds(pc);
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} else {
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WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
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//TODO: Better make defines for all these magic PCIE values.
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if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
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/* TLP Workaround register. */
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tmp = ssb_pcie_read(pc, 0x4);
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tmp |= 0x8;
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ssb_pcie_write(pc, 0x4, tmp);
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}
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if (pdev->id.revision == 0) {
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const u8 serdes_rx_device = 0x1F;
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ssb_pcie_mdio_write(pc, serdes_rx_device,
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2 /* Timer */, 0x8128);
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ssb_pcie_mdio_write(pc, serdes_rx_device,
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6 /* CDR */, 0x0100);
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ssb_pcie_mdio_write(pc, serdes_rx_device,
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7 /* CDR BW */, 0x1466);
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} else if (pdev->id.revision == 1) {
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/* DLLP Link Control register. */
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tmp = ssb_pcie_read(pc, 0x100);
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tmp |= 0x40;
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ssb_pcie_write(pc, 0x100, tmp);
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}
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ssb_pcicore_pcie_setup_workarounds(pc);
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}
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pc->setup_done = 1;
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out:
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+11
-12
@@ -1117,23 +1117,22 @@ static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
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{
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u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
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/* The REJECT bit changed position in TMSLOW between
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* Backplane revisions. */
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/* The REJECT bit seems to be different for Backplane rev 2.3 */
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switch (rev) {
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case SSB_IDLOW_SSBREV_22:
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return SSB_TMSLOW_REJECT_22;
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case SSB_IDLOW_SSBREV_24:
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case SSB_IDLOW_SSBREV_26:
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return SSB_TMSLOW_REJECT;
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case SSB_IDLOW_SSBREV_23:
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return SSB_TMSLOW_REJECT_23;
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case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
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case SSB_IDLOW_SSBREV_25: /* same here */
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case SSB_IDLOW_SSBREV_26: /* same here */
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case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
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case SSB_IDLOW_SSBREV_27: /* same here */
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return SSB_TMSLOW_REJECT_23; /* this is a guess */
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return SSB_TMSLOW_REJECT; /* this is a guess */
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default:
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printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
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WARN_ON(1);
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}
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return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
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return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
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}
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int ssb_device_is_enabled(struct ssb_device *dev)
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@@ -1309,20 +1308,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
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int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
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{
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struct ssb_chipcommon *cc;
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int err;
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enum ssb_clkmode mode;
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err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
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if (err)
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goto error;
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cc = &bus->chipco;
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mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
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ssb_chipco_set_clockmode(cc, mode);
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#ifdef CONFIG_SSB_DEBUG
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bus->powered_up = 1;
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#endif
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mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
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ssb_chipco_set_clockmode(&bus->chipco, mode);
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return 0;
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error:
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ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
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