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[ARM] 5538/1: Freescale STMP: 378n registers definition
Add register definitions for Freescale STMP 378n boards Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
dmitry pervushin
committed by
Russell King
Russell King
parent
fc3fdfd632
commit
a50808b6c4
@@ -0,0 +1,63 @@
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/*
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* stmp378x: AUDIOIN register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
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#define REGS_AUDIOIN_PHYS 0x8004C000
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#define REGS_AUDIOIN_SIZE 0x2000
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#define HW_AUDIOIN_CTRL 0x0
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#define BM_AUDIOIN_CTRL_RUN 0x00000001
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#define BP_AUDIOIN_CTRL_RUN 0
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#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
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#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
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#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
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#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
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#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
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#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
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#define HW_AUDIOIN_STAT 0x10
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#define HW_AUDIOIN_ADCSRR 0x20
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#define HW_AUDIOIN_ADCVOLUME 0x30
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#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
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#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
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#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
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#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
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#define HW_AUDIOIN_ADCDEBUG 0x40
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#define HW_AUDIOIN_ADCVOL 0x50
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#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
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#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
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#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
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#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
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#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
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#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
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#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
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#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
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#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
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#define HW_AUDIOIN_MICLINE 0x60
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#define HW_AUDIOIN_ANACLKCTRL 0x70
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#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
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#define HW_AUDIOIN_DATA 0x80
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@@ -0,0 +1,104 @@
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/*
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* stmp378x: AUDIOOUT register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
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#define REGS_AUDIOOUT_PHYS 0x80048000
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#define REGS_AUDIOOUT_SIZE 0x2000
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#define HW_AUDIOOUT_CTRL 0x0
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#define BM_AUDIOOUT_CTRL_RUN 0x00000001
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#define BP_AUDIOOUT_CTRL_RUN 0
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#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
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#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
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#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
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#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
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#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
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#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
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#define HW_AUDIOOUT_STAT 0x10
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#define HW_AUDIOOUT_DACSRR 0x20
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#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
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#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
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#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
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#define BP_AUDIOOUT_DACSRR_SRC_INT 16
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#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
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#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
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#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
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#define BP_AUDIOOUT_DACSRR_BASEMULT 28
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#define HW_AUDIOOUT_DACVOLUME 0x30
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#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
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#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
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#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
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#define HW_AUDIOOUT_DACDEBUG 0x40
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#define HW_AUDIOOUT_HPVOL 0x50
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#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
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#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
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#define HW_AUDIOOUT_PWRDN 0x70
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#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
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#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
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#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
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#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
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#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
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#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
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#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
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#define HW_AUDIOOUT_REFCTRL 0x80
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#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
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#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
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#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
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#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
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#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
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#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
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#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
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#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
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#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
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#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
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#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
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#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
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#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
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#define HW_AUDIOOUT_ANACTRL 0x90
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#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
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#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
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#define HW_AUDIOOUT_TEST 0xA0
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#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
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#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
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#define HW_AUDIOOUT_BISTCTRL 0xB0
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#define HW_AUDIOOUT_BISTSTAT0 0xC0
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#define HW_AUDIOOUT_BISTSTAT1 0xD0
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#define HW_AUDIOOUT_ANACLKCTRL 0xE0
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#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
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#define HW_AUDIOOUT_DATA 0xF0
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#define HW_AUDIOOUT_SPEAKERCTRL 0x100
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#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
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#define HW_AUDIOOUT_VERSION 0x200
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@@ -0,0 +1,56 @@
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/*
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* stmp378x: BCH register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000)
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#define REGS_BCH_PHYS 0x8000A000
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#define REGS_BCH_SIZE 0x2000
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#define HW_BCH_CTRL 0x0
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#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
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#define BP_BCH_CTRL_COMPLETE_IRQ 0
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#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
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#define HW_BCH_STATUS0 0x10
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#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
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#define BM_BCH_STATUS0_CORRECTED 0x00000008
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#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
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#define BP_BCH_STATUS0_STATUS_BLK0 8
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#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
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#define BP_BCH_STATUS0_COMPLETED_CE 16
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#define HW_BCH_LAYOUTSELECT 0x70
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#define HW_BCH_FLASH0LAYOUT0 0x80
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#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
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#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
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#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
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#define BP_BCH_FLASH0LAYOUT0_ECC0 12
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#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
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#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
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#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
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#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
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#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
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#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
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#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
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#define BP_BCH_FLASH0LAYOUT1_ECCN 12
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#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
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#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
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#define HW_BCH_BLOCKNAME 0x150
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@@ -0,0 +1,87 @@
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/*
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* stmp378x: DCP register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000)
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#define REGS_DCP_PHYS 0x80028000
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#define REGS_DCP_SIZE 0x2000
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#define HW_DCP_CTRL 0x0
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#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF
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#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0
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#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000
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#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000
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#define BM_DCP_CTRL_CLKGATE 0x40000000
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#define BM_DCP_CTRL_SFTRST 0x80000000
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#define HW_DCP_STAT 0x10
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#define BM_DCP_STAT_IRQ 0x0000000F
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#define BP_DCP_STAT_IRQ 0
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#define HW_DCP_CHANNELCTRL 0x20
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#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF
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#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0
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#define HW_DCP_CONTEXT 0x50
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#define BM_DCP_PACKET1_INTERRUPT 0x00000001
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#define BP_DCP_PACKET1_INTERRUPT 0
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#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002
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#define BM_DCP_PACKET1_CHAIN 0x00000004
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#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
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#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020
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#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040
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#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100
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#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200
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#define BM_DCP_PACKET1_OTP_KEY 0x00000400
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#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800
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#define BM_DCP_PACKET1_HASH_INIT 0x00001000
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#define BM_DCP_PACKET1_HASH_TERM 0x00002000
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#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F
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#define BP_DCP_PACKET2_CIPHER_SELECT 0
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#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0
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#define BP_DCP_PACKET2_CIPHER_MODE 4
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#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00
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#define BP_DCP_PACKET2_KEY_SELECT 8
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#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000
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#define BP_DCP_PACKET2_HASH_SELECT 16
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#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000
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#define BP_DCP_PACKET2_CIPHER_CFG 24
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#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40)
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#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40)
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#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40)
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#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40)
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#define HW_DCP_CHnCMDPTR 0x100
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#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40)
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#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40)
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#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40)
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#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40)
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#define HW_DCP_CHnSEMA 0x110
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#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF
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#define BP_DCP_CHnSEMA_INCREMENT 0
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#define HW_DCP_CH0STAT (0x120 + 0 * 0x40)
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#define HW_DCP_CH1STAT (0x120 + 1 * 0x40)
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#define HW_DCP_CH2STAT (0x120 + 2 * 0x40)
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#define HW_DCP_CH3STAT (0x120 + 3 * 0x40)
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#define HW_DCP_CHnSTAT 0x120
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@@ -0,0 +1,38 @@
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/*
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* stmp378x: DIGCTL register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
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#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
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#define REGS_DIGCTL_PHYS 0x8001C000
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#define REGS_DIGCTL_SIZE 0x2000
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#define HW_DIGCTL_CTRL 0x0
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#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
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#define HW_DIGCTL_ARMCACHE 0x2B0
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#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003
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#define BP_DIGCTL_ARMCACHE_ITAG_SS 0
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#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030
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#define BP_DIGCTL_ARMCACHE_DTAG_SS 4
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#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300
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#define BP_DIGCTL_ARMCACHE_CACHE_SS 8
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#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000
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#define BP_DIGCTL_ARMCACHE_DRTY_SS 12
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#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000
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#define BP_DIGCTL_ARMCACHE_VALID_SS 16
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@@ -0,0 +1,27 @@
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/*
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* stmp378x: DRAM register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000)
|
||||
#define REGS_DRAM_PHYS 0x800E0000
|
||||
#define REGS_DRAM_SIZE 0x2000
|
||||
|
||||
#define HW_DRAM_CTL06 0x18
|
||||
|
||||
#define HW_DRAM_CTL08 0x20
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* stmp378x: DRI register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000)
|
||||
#define REGS_DRI_PHYS 0x80074000
|
||||
#define REGS_DRI_SIZE 0x2000
|
||||
|
||||
#define HW_DRI_CTRL 0x0
|
||||
#define BM_DRI_CTRL_RUN 0x00000001
|
||||
#define BP_DRI_CTRL_RUN 0
|
||||
#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002
|
||||
#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004
|
||||
#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008
|
||||
#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200
|
||||
#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400
|
||||
#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800
|
||||
#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000
|
||||
#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000
|
||||
#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000
|
||||
#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000
|
||||
#define BM_DRI_CTRL_CLKGATE 0x40000000
|
||||
#define BM_DRI_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_DRI_TIMING 0x10
|
||||
#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF
|
||||
#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0
|
||||
#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000
|
||||
#define BP_DRI_TIMING_PILOT_REP_RATE 16
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* stmp378x: ECC8 register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
|
||||
#define REGS_ECC8_PHYS 0x80008000
|
||||
#define REGS_ECC8_SIZE 0x2000
|
||||
|
||||
#define HW_ECC8_CTRL 0x0
|
||||
#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
|
||||
#define BP_ECC8_CTRL_COMPLETE_IRQ 0
|
||||
#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
|
||||
#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
|
||||
|
||||
#define HW_ECC8_STATUS0 0x10
|
||||
#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
|
||||
#define BM_ECC8_STATUS0_CORRECTED 0x00000008
|
||||
#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
|
||||
#define BP_ECC8_STATUS0_STATUS_AUX 8
|
||||
#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
|
||||
#define BP_ECC8_STATUS0_COMPLETED_CE 16
|
||||
|
||||
#define HW_ECC8_STATUS1 0x20
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* stmp378x: EMI register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000)
|
||||
#define REGS_EMI_PHYS 0x80020000
|
||||
#define REGS_EMI_SIZE 0x2000
|
||||
|
||||
#define HW_EMI_STAT 0x10
|
||||
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* stmp378x: GPMI register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
|
||||
#define REGS_GPMI_PHYS 0x8000C000
|
||||
#define REGS_GPMI_SIZE 0x2000
|
||||
|
||||
#define HW_GPMI_CTRL0 0x0
|
||||
#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_GPMI_CTRL0_XFER_COUNT 0
|
||||
#define BM_GPMI_CTRL0_CS 0x00300000
|
||||
#define BP_GPMI_CTRL0_CS 20
|
||||
#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
|
||||
#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
|
||||
#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
|
||||
#define BP_GPMI_CTRL0_ADDRESS 17
|
||||
#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
|
||||
#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
|
||||
#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
|
||||
#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
|
||||
#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
|
||||
#define BP_GPMI_CTRL0_COMMAND_MODE 24
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
|
||||
#define BM_GPMI_CTRL0_RUN 0x20000000
|
||||
#define BM_GPMI_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_GPMI_CTRL0_SFTRST 0x80000000
|
||||
#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
|
||||
#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
|
||||
#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
|
||||
#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
|
||||
#define BP_GPMI_ECCCTRL_ECC_CMD 13
|
||||
#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0
|
||||
#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1
|
||||
#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2
|
||||
#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3
|
||||
|
||||
#define HW_GPMI_CTRL1 0x60
|
||||
#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
|
||||
#define BP_GPMI_CTRL1_GPMI_MODE 0
|
||||
#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
|
||||
#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
|
||||
#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
|
||||
#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
|
||||
#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
|
||||
#define BP_GPMI_CTRL1_RDN_DELAY 12
|
||||
#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
|
||||
|
||||
#define HW_GPMI_TIMING0 0x70
|
||||
#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
|
||||
#define BP_GPMI_TIMING0_DATA_SETUP 0
|
||||
#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
|
||||
#define BP_GPMI_TIMING0_DATA_HOLD 8
|
||||
#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
|
||||
#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
|
||||
|
||||
#define HW_GPMI_TIMING1 0x80
|
||||
#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
|
||||
#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
|
||||
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* stmp378x: I2C register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
|
||||
#define REGS_I2C_PHYS 0x80058000
|
||||
#define REGS_I2C_SIZE 0x2000
|
||||
|
||||
#define HW_I2C_CTRL0 0x0
|
||||
#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_I2C_CTRL0_XFER_COUNT 0
|
||||
#define BM_I2C_CTRL0_DIRECTION 0x00010000
|
||||
#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
|
||||
#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
|
||||
#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
|
||||
#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
|
||||
#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
|
||||
#define BM_I2C_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_I2C_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_I2C_TIMING0 0x10
|
||||
|
||||
#define HW_I2C_TIMING1 0x20
|
||||
|
||||
#define HW_I2C_TIMING2 0x30
|
||||
|
||||
#define HW_I2C_CTRL1 0x40
|
||||
#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
|
||||
#define BP_I2C_CTRL1_SLAVE_IRQ 0
|
||||
#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
|
||||
#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
|
||||
#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
|
||||
#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
|
||||
#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
|
||||
#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
|
||||
#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
|
||||
#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
|
||||
|
||||
#define HW_I2C_VERSION 0x90
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* stmp378x: IR register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000)
|
||||
#define REGS_IR_PHYS 0x80078000
|
||||
#define REGS_IR_SIZE 0x2000
|
||||
@@ -0,0 +1,195 @@
|
||||
/*
|
||||
* stmp378x: LCDIF register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
|
||||
#define REGS_LCDIF_PHYS 0x80030000
|
||||
#define REGS_LCDIF_SIZE 0x2000
|
||||
|
||||
#define HW_LCDIF_CTRL 0x0
|
||||
#define BM_LCDIF_CTRL_RUN 0x00000001
|
||||
#define BP_LCDIF_CTRL_RUN 0
|
||||
#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020
|
||||
#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080
|
||||
#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300
|
||||
#define BP_LCDIF_CTRL_WORD_LENGTH 8
|
||||
#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
|
||||
#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10
|
||||
#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000
|
||||
#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14
|
||||
#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000
|
||||
#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000
|
||||
#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000
|
||||
#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000
|
||||
#define BM_LCDIF_CTRL_DVI_MODE 0x00100000
|
||||
#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000
|
||||
#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21
|
||||
#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000
|
||||
#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000
|
||||
#define BM_LCDIF_CTRL_CLKGATE 0x40000000
|
||||
#define BM_LCDIF_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_LCDIF_CTRL1 0x10
|
||||
#define BM_LCDIF_CTRL1_RESET 0x00000001
|
||||
#define BP_LCDIF_CTRL1_RESET 0
|
||||
#define BM_LCDIF_CTRL1_MODE86 0x00000002
|
||||
#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
|
||||
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
|
||||
#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
|
||||
#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
|
||||
#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
|
||||
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
|
||||
#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
|
||||
#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
|
||||
#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
|
||||
#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000
|
||||
|
||||
#define HW_LCDIF_TRANSFER_COUNT 0x20
|
||||
#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
|
||||
#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0
|
||||
#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
|
||||
#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16
|
||||
|
||||
#define HW_LCDIF_CUR_BUF 0x30
|
||||
|
||||
#define HW_LCDIF_NEXT_BUF 0x40
|
||||
|
||||
#define HW_LCDIF_TIMING 0x60
|
||||
|
||||
#define HW_LCDIF_VDCTRL0 0x70
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF
|
||||
#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
|
||||
#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
|
||||
#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
|
||||
#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
|
||||
#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
|
||||
|
||||
#define HW_LCDIF_VDCTRL1 0x80
|
||||
#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF
|
||||
#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
|
||||
|
||||
#define HW_LCDIF_VDCTRL2 0x90
|
||||
#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF
|
||||
#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0
|
||||
#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000
|
||||
#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24
|
||||
|
||||
#define HW_LCDIF_VDCTRL3 0xA0
|
||||
#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF
|
||||
#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
|
||||
#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000
|
||||
#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16
|
||||
|
||||
#define HW_LCDIF_VDCTRL4 0xB0
|
||||
#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF
|
||||
#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0
|
||||
#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000
|
||||
|
||||
#define HW_LCDIF_DVICTRL0 0xC0
|
||||
#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF
|
||||
#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0
|
||||
#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00
|
||||
#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10
|
||||
#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000
|
||||
#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20
|
||||
|
||||
#define HW_LCDIF_DVICTRL1 0xD0
|
||||
#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF
|
||||
#define BP_LCDIF_DVICTRL1_F2_START_LINE 0
|
||||
#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00
|
||||
#define BP_LCDIF_DVICTRL1_F1_END_LINE 10
|
||||
#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
|
||||
#define BP_LCDIF_DVICTRL1_F1_START_LINE 20
|
||||
|
||||
#define HW_LCDIF_DVICTRL2 0xE0
|
||||
#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF
|
||||
#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0
|
||||
#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00
|
||||
#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10
|
||||
#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000
|
||||
#define BP_LCDIF_DVICTRL2_F2_END_LINE 20
|
||||
|
||||
#define HW_LCDIF_DVICTRL3 0xF0
|
||||
#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF
|
||||
#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0
|
||||
#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000
|
||||
#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16
|
||||
|
||||
#define HW_LCDIF_DVICTRL4 0x100
|
||||
#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF
|
||||
#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0
|
||||
#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
|
||||
#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8
|
||||
#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
|
||||
#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16
|
||||
#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000
|
||||
#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24
|
||||
|
||||
#define HW_LCDIF_CSC_COEFF0 0x110
|
||||
#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003
|
||||
#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0
|
||||
#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000
|
||||
#define BP_LCDIF_CSC_COEFF0_C0 16
|
||||
|
||||
#define HW_LCDIF_CSC_COEFF1 0x120
|
||||
#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF
|
||||
#define BP_LCDIF_CSC_COEFF1_C1 0
|
||||
#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000
|
||||
#define BP_LCDIF_CSC_COEFF1_C2 16
|
||||
|
||||
#define HW_LCDIF_CSC_COEFF2 0x130
|
||||
#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF
|
||||
#define BP_LCDIF_CSC_COEFF2_C3 0
|
||||
#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000
|
||||
#define BP_LCDIF_CSC_COEFF2_C4 16
|
||||
|
||||
#define HW_LCDIF_CSC_COEFF3 0x140
|
||||
#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF
|
||||
#define BP_LCDIF_CSC_COEFF3_C5 0
|
||||
#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000
|
||||
#define BP_LCDIF_CSC_COEFF3_C6 16
|
||||
|
||||
#define HW_LCDIF_CSC_COEFF4 0x150
|
||||
#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF
|
||||
#define BP_LCDIF_CSC_COEFF4_C7 0
|
||||
#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000
|
||||
#define BP_LCDIF_CSC_COEFF4_C8 16
|
||||
|
||||
#define HW_LCDIF_CSC_OFFSET 0x160
|
||||
#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF
|
||||
#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0
|
||||
#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
|
||||
#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16
|
||||
|
||||
#define HW_LCDIF_CSC_LIMIT 0x170
|
||||
#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF
|
||||
#define BP_LCDIF_CSC_LIMIT_Y_MAX 0
|
||||
#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00
|
||||
#define BP_LCDIF_CSC_LIMIT_Y_MIN 8
|
||||
#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000
|
||||
#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16
|
||||
#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000
|
||||
#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24
|
||||
|
||||
#define HW_LCDIF_STAT 0x1D0
|
||||
#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000
|
||||
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* stmp378x: LRADC register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
|
||||
#define REGS_LRADC_PHYS 0x80050000
|
||||
#define REGS_LRADC_SIZE 0x2000
|
||||
|
||||
#define HW_LRADC_CTRL0 0x0
|
||||
#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
|
||||
#define BP_LRADC_CTRL0_SCHEDULE 0
|
||||
#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
|
||||
#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
|
||||
#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
|
||||
#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
|
||||
#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
|
||||
#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
|
||||
#define BM_LRADC_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_LRADC_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_LRADC_CTRL1 0x10
|
||||
#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
|
||||
#define BP_LRADC_CTRL1_LRADC0_IRQ 0
|
||||
#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
|
||||
#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
|
||||
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
|
||||
#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
|
||||
#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
|
||||
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
|
||||
|
||||
#define HW_LRADC_CTRL2 0x20
|
||||
#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
|
||||
#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
|
||||
#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
|
||||
#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
|
||||
#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
|
||||
#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
|
||||
|
||||
#define HW_LRADC_CTRL3 0x30
|
||||
#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
|
||||
#define BP_LRADC_CTRL3_CYCLE_TIME 8
|
||||
|
||||
#define HW_LRADC_STATUS 0x40
|
||||
#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
|
||||
#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
|
||||
|
||||
#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
|
||||
#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
|
||||
#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
|
||||
#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
|
||||
#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
|
||||
#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
|
||||
#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
|
||||
#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
|
||||
|
||||
#define HW_LRADC_CHn 0x50
|
||||
#define BM_LRADC_CHn_VALUE 0x0003FFFF
|
||||
#define BP_LRADC_CHn_VALUE 0
|
||||
#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
|
||||
#define BP_LRADC_CHn_NUM_SAMPLES 24
|
||||
#define BM_LRADC_CHn_ACCUMULATE 0x20000000
|
||||
|
||||
#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
|
||||
#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
|
||||
#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
|
||||
#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
|
||||
|
||||
#define HW_LRADC_DELAYn 0xD0
|
||||
#define BM_LRADC_DELAYn_DELAY 0x000007FF
|
||||
#define BP_LRADC_DELAYn_DELAY 0
|
||||
#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
|
||||
#define BP_LRADC_DELAYn_LOOP_COUNT 11
|
||||
#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
|
||||
#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
|
||||
#define BM_LRADC_DELAYn_KICK 0x00100000
|
||||
#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
|
||||
#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
|
||||
|
||||
#define HW_LRADC_CTRL4 0x140
|
||||
#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
|
||||
#define BP_LRADC_CTRL4_LRADC6SELECT 24
|
||||
#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
|
||||
#define BP_LRADC_CTRL4_LRADC7SELECT 28
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* stmp378x: OCOTP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000)
|
||||
#define REGS_OCOTP_PHYS 0x8002C000
|
||||
#define REGS_OCOTP_SIZE 0x2000
|
||||
|
||||
#define HW_OCOTP_CTRL 0x0
|
||||
#define BM_OCOTP_CTRL_BUSY 0x00000100
|
||||
#define BM_OCOTP_CTRL_ERROR 0x00000200
|
||||
#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000
|
||||
#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000
|
||||
#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
|
||||
#define BP_OCOTP_CTRL_WR_UNLOCK 16
|
||||
|
||||
#define HW_OCOTP_DATA 0x10
|
||||
|
||||
#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10)
|
||||
#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10)
|
||||
#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10)
|
||||
#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10)
|
||||
|
||||
#define HW_OCOTP_CUSTn 0x20
|
||||
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* stmp378x: PWM register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
|
||||
#define REGS_PWM_PHYS 0x80064000
|
||||
#define REGS_PWM_SIZE 0x2000
|
||||
|
||||
#define HW_PWM_CTRL 0x0
|
||||
#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
|
||||
#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
|
||||
|
||||
#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
|
||||
#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
|
||||
#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
|
||||
#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
|
||||
|
||||
#define HW_PWM_ACTIVEn 0x10
|
||||
#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
|
||||
#define BP_PWM_ACTIVEn_ACTIVE 0
|
||||
#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
|
||||
#define BP_PWM_ACTIVEn_INACTIVE 16
|
||||
|
||||
#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
|
||||
#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
|
||||
#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
|
||||
#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
|
||||
|
||||
#define HW_PWM_PERIODn 0x20
|
||||
#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
|
||||
#define BP_PWM_PERIODn_PERIOD 0
|
||||
#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
|
||||
#define BP_PWM_PERIODn_ACTIVE_STATE 16
|
||||
#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
|
||||
#define BP_PWM_PERIODn_INACTIVE_STATE 18
|
||||
#define BM_PWM_PERIODn_CDIV 0x00700000
|
||||
#define BP_PWM_PERIODn_CDIV 20
|
||||
@@ -0,0 +1,140 @@
|
||||
/*
|
||||
* stmp378x: PXP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000)
|
||||
#define REGS_PXP_PHYS 0x8002A000
|
||||
#define REGS_PXP_SIZE 0x2000
|
||||
|
||||
#define HW_PXP_CTRL 0x0
|
||||
#define BM_PXP_CTRL_ENABLE 0x00000001
|
||||
#define BP_PXP_CTRL_ENABLE 0
|
||||
#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
|
||||
#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0
|
||||
#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4
|
||||
#define BM_PXP_CTRL_ROTATE 0x00000300
|
||||
#define BP_PXP_CTRL_ROTATE 8
|
||||
#define BM_PXP_CTRL_HFLIP 0x00000400
|
||||
#define BM_PXP_CTRL_VFLIP 0x00000800
|
||||
#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
|
||||
#define BP_PXP_CTRL_S0_FORMAT 12
|
||||
#define BM_PXP_CTRL_SCALE 0x00040000
|
||||
#define BM_PXP_CTRL_CROP 0x00080000
|
||||
|
||||
#define HW_PXP_STAT 0x10
|
||||
#define BM_PXP_STAT_IRQ 0x00000001
|
||||
#define BP_PXP_STAT_IRQ 0
|
||||
|
||||
#define HW_PXP_RGBBUF 0x20
|
||||
|
||||
#define HW_PXP_RGBSIZE 0x40
|
||||
#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF
|
||||
#define BP_PXP_RGBSIZE_HEIGHT 0
|
||||
#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000
|
||||
#define BP_PXP_RGBSIZE_WIDTH 12
|
||||
|
||||
#define HW_PXP_S0BUF 0x50
|
||||
|
||||
#define HW_PXP_S0UBUF 0x60
|
||||
|
||||
#define HW_PXP_S0VBUF 0x70
|
||||
|
||||
#define HW_PXP_S0PARAM 0x80
|
||||
#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
|
||||
#define BP_PXP_S0PARAM_HEIGHT 0
|
||||
#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
|
||||
#define BP_PXP_S0PARAM_WIDTH 8
|
||||
#define BM_PXP_S0PARAM_YBASE 0x00FF0000
|
||||
#define BP_PXP_S0PARAM_YBASE 16
|
||||
#define BM_PXP_S0PARAM_XBASE 0xFF000000
|
||||
#define BP_PXP_S0PARAM_XBASE 24
|
||||
|
||||
#define HW_PXP_S0BACKGROUND 0x90
|
||||
|
||||
#define HW_PXP_S0CROP 0xA0
|
||||
#define BM_PXP_S0CROP_HEIGHT 0x000000FF
|
||||
#define BP_PXP_S0CROP_HEIGHT 0
|
||||
#define BM_PXP_S0CROP_WIDTH 0x0000FF00
|
||||
#define BP_PXP_S0CROP_WIDTH 8
|
||||
#define BM_PXP_S0CROP_YBASE 0x00FF0000
|
||||
#define BP_PXP_S0CROP_YBASE 16
|
||||
#define BM_PXP_S0CROP_XBASE 0xFF000000
|
||||
#define BP_PXP_S0CROP_XBASE 24
|
||||
|
||||
#define HW_PXP_S0SCALE 0xB0
|
||||
#define BM_PXP_S0SCALE_XSCALE 0x00003FFF
|
||||
#define BP_PXP_S0SCALE_XSCALE 0
|
||||
#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000
|
||||
#define BP_PXP_S0SCALE_YSCALE 16
|
||||
|
||||
#define HW_PXP_CSCCOEFF0 0xD0
|
||||
|
||||
#define HW_PXP_CSCCOEFF1 0xE0
|
||||
|
||||
#define HW_PXP_CSCCOEFF2 0xF0
|
||||
|
||||
#define HW_PXP_S0COLORKEYLOW 0x180
|
||||
|
||||
#define HW_PXP_S0COLORKEYHIGH 0x190
|
||||
|
||||
#define HW_PXP_OL0 (0x200 + 0 * 0x40)
|
||||
#define HW_PXP_OL1 (0x200 + 1 * 0x40)
|
||||
#define HW_PXP_OL2 (0x200 + 2 * 0x40)
|
||||
#define HW_PXP_OL3 (0x200 + 3 * 0x40)
|
||||
#define HW_PXP_OL4 (0x200 + 4 * 0x40)
|
||||
#define HW_PXP_OL5 (0x200 + 5 * 0x40)
|
||||
#define HW_PXP_OL6 (0x200 + 6 * 0x40)
|
||||
#define HW_PXP_OL7 (0x200 + 7 * 0x40)
|
||||
|
||||
#define HW_PXP_OLn 0x200
|
||||
|
||||
#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40)
|
||||
#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40)
|
||||
#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40)
|
||||
#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40)
|
||||
#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40)
|
||||
#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40)
|
||||
#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40)
|
||||
#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40)
|
||||
|
||||
#define HW_PXP_OLnSIZE 0x210
|
||||
#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
|
||||
#define BP_PXP_OLnSIZE_HEIGHT 0
|
||||
#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
|
||||
#define BP_PXP_OLnSIZE_WIDTH 8
|
||||
|
||||
#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40)
|
||||
#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40)
|
||||
#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40)
|
||||
#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40)
|
||||
#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40)
|
||||
#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40)
|
||||
#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40)
|
||||
#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40)
|
||||
|
||||
#define HW_PXP_OLnPARAM 0x220
|
||||
#define BM_PXP_OLnPARAM_ENABLE 0x00000001
|
||||
#define BP_PXP_OLnPARAM_ENABLE 0
|
||||
#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
|
||||
#define BP_PXP_OLnPARAM_ALPHA_CNTL 1
|
||||
#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
|
||||
#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
|
||||
#define BP_PXP_OLnPARAM_FORMAT 4
|
||||
#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
|
||||
#define BP_PXP_OLnPARAM_ALPHA 8
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* stmp378x: RTC register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
|
||||
#define REGS_RTC_PHYS 0x8005C000
|
||||
#define REGS_RTC_SIZE 0x2000
|
||||
|
||||
#define HW_RTC_CTRL 0x0
|
||||
#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
|
||||
#define BP_RTC_CTRL_ALARM_IRQ_EN 0
|
||||
#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
|
||||
#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
|
||||
#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
|
||||
#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
|
||||
|
||||
#define HW_RTC_STAT 0x10
|
||||
#define BM_RTC_STAT_NEW_REGS 0x0000FF00
|
||||
#define BP_RTC_STAT_NEW_REGS 8
|
||||
#define BM_RTC_STAT_STALE_REGS 0x00FF0000
|
||||
#define BP_RTC_STAT_STALE_REGS 16
|
||||
#define BM_RTC_STAT_RTC_PRESENT 0x80000000
|
||||
|
||||
#define HW_RTC_SECONDS 0x30
|
||||
|
||||
#define HW_RTC_ALARM 0x40
|
||||
|
||||
#define HW_RTC_WATCHDOG 0x50
|
||||
|
||||
#define HW_RTC_PERSISTENT0 0x60
|
||||
#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
|
||||
#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
|
||||
#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
|
||||
#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
|
||||
#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
|
||||
#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
|
||||
#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
|
||||
|
||||
#define HW_RTC_PERSISTENT1 0x70
|
||||
#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF
|
||||
#define BP_RTC_PERSISTENT1_GENERAL 0
|
||||
|
||||
#define HW_RTC_VERSION 0xD0
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* stmp378x: SAIF register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_SAIF_SIZE 0x2000
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* stmp378x: SPDIF register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000)
|
||||
#define REGS_SPDIF_PHYS 0x80054000
|
||||
#define REGS_SPDIF_SIZE 0x2000
|
||||
|
||||
#define HW_SPDIF_CTRL 0x0
|
||||
#define BM_SPDIF_CTRL_RUN 0x00000001
|
||||
#define BP_SPDIF_CTRL_RUN 0
|
||||
#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
|
||||
#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
|
||||
#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
|
||||
#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010
|
||||
#define BM_SPDIF_CTRL_CLKGATE 0x40000000
|
||||
#define BM_SPDIF_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_SPDIF_STAT 0x10
|
||||
|
||||
#define HW_SPDIF_FRAMECTRL 0x20
|
||||
|
||||
#define HW_SPDIF_SRR 0x30
|
||||
#define BM_SPDIF_SRR_RATE 0x000FFFFF
|
||||
#define BP_SPDIF_SRR_RATE 0
|
||||
#define BM_SPDIF_SRR_BASEMULT 0x70000000
|
||||
#define BP_SPDIF_SRR_BASEMULT 28
|
||||
|
||||
#define HW_SPDIF_DEBUG 0x40
|
||||
|
||||
#define HW_SPDIF_DATA 0x50
|
||||
|
||||
#define HW_SPDIF_VERSION 0x60
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user