Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 3030/2: fix permission check in the obscur cmpxchg syscall
  [ARM] nommu: rename compressed/head.S symbols to a new style
  [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHG
  [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h
  [ARM] Move read of processor ID out of lookup_processor_type()
  [ARM] Fix typo in tlbflush.h
  [ARM] noMMU: removes TLB codes in nommu mode
  [ARM] noMMU: block sys_fork in nommu mode
  [ARM] 3399/1: Fix link problem when CONFIG_PRINTK is disabled
  [ARM] 3398/1: Fix the VFP registers loading/storing base address
  [ARM] 3397/1: AT91RM9200 Header update
  [ARM] 3385/1: Battery support for sharp zaurus sl-5500 (collie)
  [ARM] SMP: don't set cpu_*_map in smp_prepare_boot_cpu
  include/linux/clk.h is betraying its ARM origins
  [ARM] Move enable_irq and disable_irq to assembler.h
  [ARM] 3391/1: use PLAT8250_DEV_PLATFORM{,1} for platform device id instead of 0/1

arch/arm/boot/compressed/head.S

@@ -358,7 +358,7 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
 		str	r1, [r0]
 		mov	pc, lr
 
-__armv4_cache_on:
+__armv4_mmu_cache_on:
 		mov	r12, lr
 		bl	__setup_mmu
 		mov	r0, #0
@@ -367,24 +367,24 @@ __armv4_cache_on:
 		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
 		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement
 		orr	r0, r0, #0x0030
-		bl	__common_cache_on
+		bl	__common_mmu_cache_on
 		mov	r0, #0
 		mcr	p15, 0, r0, c8, c7, 0	@ flush I,D TLBs
 		mov	pc, r12
 
-__arm6_cache_on:
+__arm6_mmu_cache_on:
 		mov	r12, lr
 		bl	__setup_mmu
 		mov	r0, #0
 		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
 		mcr	p15, 0, r0, c5, c0, 0	@ invalidate whole TLB v3
 		mov	r0, #0x30
-		bl	__common_cache_on
+		bl	__common_mmu_cache_on
 		mov	r0, #0
 		mcr	p15, 0, r0, c5, c0, 0	@ invalidate whole TLB v3
 		mov	pc, r12
 
-__common_cache_on:
+__common_mmu_cache_on:
 #ifndef DEBUG
 		orr	r0, r0, #0x000d		@ Write buffer, mmu
 #endif
@@ -471,12 +471,12 @@ call_cache_fn:	adr	r12, proc_types
 proc_types:
 		.word	0x41560600		@ ARM6/610
 		.word	0xffffffe0
-		b	__arm6_cache_off	@ works, but slow
+		b	__arm6_mmu_cache_off	@ works, but slow
-		b	__arm6_cache_off
+		b	__arm6_mmu_cache_off
 		mov	pc, lr
-@		b	__arm6_cache_on		@ untested
+@		b	__arm6_mmu_cache_on		@ untested
-@		b	__arm6_cache_off
+@		b	__arm6_mmu_cache_off
-@		b	__armv3_cache_flush
+@		b	__armv3_mmu_cache_flush
 
 		.word	0x00000000		@ old ARM ID
 		.word	0x0000f000
@@ -486,14 +486,14 @@ proc_types:
 
 		.word	0x41007000		@ ARM7/710
 		.word	0xfff8fe00
-		b	__arm7_cache_off
+		b	__arm7_mmu_cache_off
-		b	__arm7_cache_off
+		b	__arm7_mmu_cache_off
 		mov	pc, lr
 
 		.word	0x41807200		@ ARM720T (writethrough)
 		.word	0xffffff00
-		b	__armv4_cache_on
+		b	__armv4_mmu_cache_on
-		b	__armv4_cache_off
+		b	__armv4_mmu_cache_off
 		mov	pc, lr
 
 		.word	0x00007000		@ ARM7 IDs
@@ -506,41 +506,41 @@ proc_types:
 
 		.word	0x4401a100		@ sa110 / sa1100
 		.word	0xffffffe0
-		b	__armv4_cache_on
+		b	__armv4_mmu_cache_on
-		b	__armv4_cache_off
+		b	__armv4_mmu_cache_off
-		b	__armv4_cache_flush
+		b	__armv4_mmu_cache_flush
 
 		.word	0x6901b110		@ sa1110
 		.word	0xfffffff0
-		b	__armv4_cache_on
+		b	__armv4_mmu_cache_on
-		b	__armv4_cache_off
+		b	__armv4_mmu_cache_off
-		b	__armv4_cache_flush
+		b	__armv4_mmu_cache_flush
 
 		@ These match on the architecture ID
 
 		.word	0x00020000		@ ARMv4T
 		.word	0x000f0000
-		b	__armv4_cache_on
+		b	__armv4_mmu_cache_on
-		b	__armv4_cache_off
+		b	__armv4_mmu_cache_off
-		b	__armv4_cache_flush
+		b	__armv4_mmu_cache_flush
 
 		.word	0x00050000		@ ARMv5TE
 		.word	0x000f0000
-		b	__armv4_cache_on
+		b	__armv4_mmu_cache_on
-		b	__armv4_cache_off
+		b	__armv4_mmu_cache_off
-		b	__armv4_cache_flush
+		b	__armv4_mmu_cache_flush
 
 		.word	0x00060000		@ ARMv5TEJ
 		.word	0x000f0000
-		b	__armv4_cache_on
+		b	__armv4_mmu_cache_on
-		b	__armv4_cache_off
+		b	__armv4_mmu_cache_off
-		b	__armv4_cache_flush
+		b	__armv4_mmu_cache_flush
 
 		.word	0x00070000		@ ARMv6
 		.word	0x000f0000
-		b	__armv4_cache_on
+		b	__armv4_mmu_cache_on
-		b	__armv4_cache_off
+		b	__armv4_mmu_cache_off
-		b	__armv6_cache_flush
+		b	__armv6_mmu_cache_flush
 
 		.word	0			@ unrecognised type
 		.word	0
@@ -562,7 +562,7 @@ proc_types:
 cache_off:	mov	r3, #12			@ cache_off function
 		b	call_cache_fn
 
-__armv4_cache_off:
+__armv4_mmu_cache_off:
 		mrc	p15, 0, r0, c1, c0
 		bic	r0, r0, #0x000d
 		mcr	p15, 0, r0, c1, c0	@ turn MMU and cache off
@@ -571,15 +571,15 @@ __armv4_cache_off:
 		mcr	p15, 0, r0, c8, c7	@ invalidate whole TLB v4
 		mov	pc, lr
 
-__arm6_cache_off:
+__arm6_mmu_cache_off:
 		mov	r0, #0x00000030		@ ARM6 control reg.
-		b	__armv3_cache_off
+		b	__armv3_mmu_cache_off
 
-__arm7_cache_off:
+__arm7_mmu_cache_off:
 		mov	r0, #0x00000070		@ ARM7 control reg.
-		b	__armv3_cache_off
+		b	__armv3_mmu_cache_off
 
-__armv3_cache_off:
+__armv3_mmu_cache_off:
 		mcr	p15, 0, r0, c1, c0, 0	@ turn MMU and cache off
 		mov	r0, #0
 		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
@@ -601,7 +601,7 @@ cache_clean_flush:
 		mov	r3, #16
 		b	call_cache_fn
 
-__armv6_cache_flush:
+__armv6_mmu_cache_flush:
 		mov	r1, #0
 		mcr	p15, 0, r1, c7, c14, 0	@ clean+invalidate D
 		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I+BTB
@@ -609,7 +609,7 @@ __armv6_cache_flush:
 		mcr	p15, 0, r1, c7, c10, 4	@ drain WB
 		mov	pc, lr
 
-__armv4_cache_flush:
+__armv4_mmu_cache_flush:
 		mov	r2, #64*1024		@ default: 32K dcache size (*2)
 		mov	r11, #32		@ default: 32 byte line size
 		mrc	p15, 0, r3, c0, c0, 1	@ read cache type
@@ -637,7 +637,7 @@ no_cache_id:
 		mcr	p15, 0, r1, c7, c10, 4	@ drain WB
 		mov	pc, lr
 
-__armv3_cache_flush:
+__armv3_mmu_cache_flush:
 		mov	r1, #0
 		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
 		mov	pc, lr

arch/arm/kernel/entry-header.S

@@ -37,24 +37,6 @@
 #endif
 	.endm
 
-#if __LINUX_ARM_ARCH__ >= 6
-	.macro	disable_irq
-	cpsid	i
-	.endm
-
-	.macro	enable_irq
-	cpsie	i
-	.endm
-#else
-	.macro	disable_irq
-	msr	cpsr_c, #PSR_I_BIT | SVC_MODE
-	.endm
-
-	.macro	enable_irq
-	msr	cpsr_c, #SVC_MODE
-	.endm
-#endif
-
 	.macro	get_thread_info, rd
 	mov	\rd, sp, lsr #13
 	mov	\rd, \rd, lsl #13

arch/arm/kernel/head.S

@@ -81,6 +81,7 @@
 ENTRY(stext)
 	msr	cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
 						@ and irqs disabled
+	mrc	p15, 0, r9, c0, c0		@ get processor id
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
 	beq	__error_p			@ yes, error 'p'
@@ -155,6 +156,7 @@ ENTRY(secondary_startup)
 	 * as it has already been validated by the primary processor.
 	 */
 	msr	cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
+	mrc	p15, 0, r9, c0, c0		@ get processor id
 	bl	__lookup_processor_type
 	movs	r10, r5				@ invalid processor?
 	moveq	r0, #'p'			@ yes, error 'p'
@@ -449,19 +451,19 @@ __error:
  * (and therefore, we are not in the correct address space).  We have to
  * calculate the offset.
  *
+ *	r9 = cpuid
  * Returns:
  *	r3, r4, r6 corrupted
  *	r5 = proc_info pointer in physical address space
- *	r9 = cpuid
+ *	r9 = cpuid (preserved)
  */
 	.type	__lookup_processor_type, %function
 __lookup_processor_type:
 	adr	r3, 3f
-	ldmda	r3, {r5, r6, r9}
+	ldmda	r3, {r5 - r7}
-	sub	r3, r3, r9			@ get offset between virt&phys
+	sub	r3, r3, r7			@ get offset between virt&phys
 	add	r5, r5, r3			@ convert virt addresses to
 	add	r6, r6, r3			@ physical address space
-	mrc	p15, 0, r9, c0, c0		@ get processor id
 1:	ldmia	r5, {r3, r4}			@ value, mask
 	and	r4, r4, r9			@ mask wanted bits
 	teq	r3, r4
@@ -476,10 +478,11 @@ __lookup_processor_type:
  * This provides a C-API version of the above function.
  */
 ENTRY(lookup_processor_type)
-	stmfd	sp!, {r4 - r6, r9, lr}
+	stmfd	sp!, {r4 - r7, r9, lr}
+	mov	r9, r0
 	bl	__lookup_processor_type
 	mov	r0, r5
-	ldmfd	sp!, {r4 - r6, r9, pc}
+	ldmfd	sp!, {r4 - r7, r9, pc}
 
 /*
  * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for

arch/arm/kernel/setup.c

@@ -278,7 +278,7 @@ int cpu_architecture(void)
  * These functions re-use the assembly code in head.S, which
  * already provide the required functionality.
  */
-extern struct proc_info_list *lookup_processor_type(void);
+extern struct proc_info_list *lookup_processor_type(unsigned int);
 extern struct machine_desc *lookup_machine_type(unsigned int);
 
 static void __init setup_processor(void)
@@ -290,7 +290,7 @@ static void __init setup_processor(void)
 	 * types.  The linker builds this table for us from the
 	 * entries in arch/arm/mm/proc-*.S
 	 */
-	list = lookup_processor_type();
+	list = lookup_processor_type(processor_id);
 	if (!list) {
 		printk("CPU configuration botched (ID %08x), unable "
 		       "to continue.\n", processor_id);

arch/arm/kernel/smp.c

@@ -337,9 +337,6 @@ void __init smp_prepare_boot_cpu(void)
 	unsigned int cpu = smp_processor_id();
 
 	per_cpu(cpu_data, cpu).idle = current;
-
-	cpu_set(cpu, cpu_present_map);
-	cpu_set(cpu, cpu_online_map);
 }
 
 static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg)

arch/arm/kernel/sys_arm.c

@@ -234,7 +234,12 @@ asmlinkage int sys_ipc(uint call, int first, int second, int third,
  */
 asmlinkage int sys_fork(struct pt_regs *regs)
 {
+#ifdef CONFIG_MMU
 	return do_fork(SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL);
+#else
+	/* can not support in nommu mode */
+	return(-EINVAL);
+#endif
 }
 
 /* Clone a task - this clones the calling program thread.

arch/arm/kernel/traps.c

@@ -506,7 +506,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		if (!pmd_present(*pmd))
 			goto bad_access;
 		pte = pte_offset_map_lock(mm, pmd, addr, &ptl);
-		if (!pte_present(*pte) || !pte_write(*pte)) {
+		if (!pte_present(*pte) || !pte_dirty(*pte)) {
 			pte_unmap_unlock(pte, ptl);
 			goto bad_access;
 		}

arch/arm/lib/backtrace.S

@@ -29,7 +29,7 @@ ENTRY(__backtrace)
 
 ENTRY(c_backtrace)
 
-#ifndef CONFIG_FRAME_POINTER
+#if !defined(CONFIG_FRAME_POINTER) || !defined(CONFIG_PRINTK)
 		mov	pc, lr
 #else
 

arch/arm/mach-iop3xx/iop331-setup.c

@@ -103,7 +103,7 @@ static struct plat_serial8250_port iop33x_uart1_data[] = {
 
 static struct platform_device iop33x_uart0 = {
        .name = "serial8250",
-       .id = 0,
+       .id = PLAT8250_DEV_PLATFORM,
        .dev.platform_data = iop33x_uart0_data,
        .num_resources = 2,
        .resource = iop33x_uart0_resources,
@@ -111,7 +111,7 @@ static struct platform_device iop33x_uart0 = {
 
 static struct platform_device iop33x_uart1 = {
        .name = "serial8250",
-       .id = 1,
+       .id = PLAT8250_DEV_PLATFORM1,
        .dev.platform_data = iop33x_uart1_data,
        .num_resources = 2,
        .resource = iop33x_uart1_resources,

arch/arm/mach-omap2/serial.c

@@ -167,7 +167,7 @@ void __init omap_serial_init()
 
 static struct platform_device serial_device = {
 	.name			= "serial8250",
-	.id			= 0,
+	.id			= PLAT8250_DEV_PLATFORM,
 	.dev			= {
 		.platform_data	= serial_platform_data,
 	},

arch/arm/mach-sa1100/assabet.c

@@ -26,6 +26,7 @@
 #include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/page.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 

arch/arm/mach-sa1100/collie_pm.c

@@ -0,0 +1,278 @@
+/*
+ * Based on spitz_pm.c and sharp code.
+ *
+ * Copyright (C) 2001  SHARP
+ * Copyright 2005 Pavel Machek <pavel@suse.cz>
+ *
+ * Distribute under GPLv2.
+ *
+ * Li-ion batteries are angry beasts, and they like to explode. This driver is not finished,
+ * and sometimes charges them when it should not. If it makes angry lithium to come your way...
+ * ...well, you have been warned.
+ */
+
+#include <linux/module.h>
+#include <linux/stat.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/hardware/scoop.h>
+#include <asm/dma.h>
+#include <asm/arch/collie.h>
+#include <asm/mach/sharpsl_param.h>
+#include <asm/hardware/sharpsl_pm.h>
+
+#include "../drivers/mfd/ucb1x00.h"
+
+static struct ucb1x00 *ucb;
+static int ad_revise;
+
+#define ADCtoPower(x)	       ((330 * x * 2) / 1024)
+
+static void collie_charger_init(void)
+{
+	int err;
+
+	if (sharpsl_param.adadj != -1) {
+		ad_revise = sharpsl_param.adadj;
+	}
+
+	/* Register interrupt handler. */
+	if ((err = request_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr, SA_INTERRUPT,
+			       "ACIN", sharpsl_ac_isr))) {
+		printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_AC_IN);
+		return;
+	}
+	if ((err = request_irq(COLLIE_IRQ_GPIO_CO, sharpsl_chrg_full_isr, SA_INTERRUPT,
+			       "CO", sharpsl_chrg_full_isr))) {
+		free_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr);
+		printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_CO);
+		return;
+	}
+
+	ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON |
+			           COLLIE_TC35143_GPIO_BBAT_ON);
+	return;
+}
+
+static void collie_measure_temp(int on)
+{
+	if (on)
+		ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0);
+	else
+		ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON);
+}
+
+static void collie_charge(int on)
+{
+	if (on) {
+		printk("Should start charger\n");
+	} else {
+		printk("Should stop charger\n");
+	}
+#ifdef I_AM_SURE
+
+	/* Zaurus seems to contain LTC1731 ; it should know when to
+	 * stop charging itself, so setting charge on should be
+	 * relatively harmless (as long as it is not done too often).
+	 */
+#define CF_BUF_CTRL_BASE 0xF0800000
+#define        SCOOP_REG(adr) (*(volatile unsigned short*)(CF_BUF_CTRL_BASE+(adr)))
+#define        SCOOP_REG_GPWR    SCOOP_REG(SCOOP_GPWR)
+
+	if (on) {
+		set_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON);
+	} else {
+		reset_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON);
+	}
+#endif
+}
+
+static void collie_discharge(int on)
+{
+}
+
+static void collie_discharge1(int on)
+{
+}
+
+static void collie_presuspend(void)
+{
+}
+
+static void collie_postsuspend(void)
+{
+}
+
+static int collie_should_wakeup(unsigned int resume_on_alarm)
+{
+	return 0;
+}
+
+static unsigned long collie_charger_wakeup(void)
+{
+	return 0;
+}
+
+int collie_read_backup_battery(void)
+{
+	int voltage;
+
+	ucb1x00_adc_enable(ucb);
+
+	/* Gives 75..130 */
+	ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_BBAT_ON, 0);
+	voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC);
+
+	ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON);
+	ucb1x00_adc_disable(ucb);
+
+	printk("Backup battery = %d(%d)\n", ADCtoPower(voltage), voltage);
+
+	return ADCtoPower(voltage);
+}
+
+int collie_read_main_battery(void)
+{
+	int voltage, voltage_rev, voltage_volts;
+
+	ucb1x00_adc_enable(ucb);
+	ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON);
+	ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_MBAT_ON, 0);
+	/* gives values 160..255 with battery removed... and
+	   145..255 with battery inserted. (on AC), goes as low as
+	   80 on DC. */
+	voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC);
+
+	ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON);
+	ucb1x00_adc_disable(ucb);
+
+	voltage_rev = voltage + ((ad_revise * voltage) / 652);
+	voltage_volts = ADCtoPower(voltage_rev);
+
+	printk("Main battery = %d(%d)\n", voltage_volts, voltage);
+
+	if (voltage != -1)
+		return voltage_volts;
+	else
+		return voltage;
+}
+
+int collie_read_temp(void)
+{
+	int voltage;
+
+	/* According to Sharp, temp must be > 973, main battery must be < 465,
+	   FIXME: sharpsl_pm.c has both conditions negated? FIXME: values
+	   are way out of range? */
+
+	ucb1x00_adc_enable(ucb);
+	ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0);
+	/* >1010 = battery removed, 460 = 22C ?, higer = lower temp ? */
+	voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD0, UCB_SYNC);
+	ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON);
+	ucb1x00_adc_disable(ucb);
+
+	printk("Battery temp = %d\n", voltage);
+	return voltage;
+}
+
+static unsigned long read_devdata(int which)
+{
+	switch (which) {
+	case SHARPSL_BATT_VOLT:
+		return collie_read_main_battery();
+	case SHARPSL_BATT_TEMP:
+		return collie_read_temp();
+	case SHARPSL_ACIN_VOLT:
+		return 0x1;
+	case SHARPSL_STATUS_ACIN: {
+		int ret = GPLR & COLLIE_GPIO_AC_IN;
+		printk("AC status = %d\n", ret);
+		return ret;
+	}
+	case SHARPSL_STATUS_FATAL: {
+		int ret = GPLR & COLLIE_GPIO_MAIN_BAT_LOW;
+		printk("Fatal bat = %d\n", ret);
+		return ret;
+	}
+	default:
+		return ~0;
+	}
+}
+
+struct battery_thresh collie_battery_levels[] = {
+	{ 368, 100},
+	{ 358,  25},
+	{ 356,   5},
+	{   0,   0},
+};
+
+struct sharpsl_charger_machinfo collie_pm_machinfo = {
+	.init             = collie_charger_init,
+	.read_devdata	  = read_devdata,
+	.discharge        = collie_discharge,
+	.discharge1       = collie_discharge1,
+	.charge           = collie_charge,
+	.measure_temp     = collie_measure_temp,
+	.presuspend       = collie_presuspend,
+	.postsuspend      = collie_postsuspend,
+	.charger_wakeup   = collie_charger_wakeup,
+	.should_wakeup    = collie_should_wakeup,
+	.bat_levels       = 3,
+	.bat_levels_noac  = collie_battery_levels,
+	.bat_levels_acin  = collie_battery_levels,
+	.status_high_acin = 368,
+	.status_low_acin  = 358,
+	.status_high_noac = 368,
+	.status_low_noac  = 358,
+};
+
+static int __init collie_pm_ucb_add(struct ucb1x00_dev *pdev)
+{
+	sharpsl_pm.machinfo = &collie_pm_machinfo;
+	ucb = pdev->ucb;
+	return 0;
+}
+
+static struct ucb1x00_driver collie_pm_ucb_driver = {
+	.add            = collie_pm_ucb_add,
+};
+
+static struct platform_device *collie_pm_device;
+
+static int __init collie_pm_init(void)
+{
+        int ret;
+
+        collie_pm_device = platform_device_alloc("sharpsl-pm", -1);
+        if (!collie_pm_device)
+                return -ENOMEM;
+
+        collie_pm_device->dev.platform_data = &collie_pm_machinfo;
+        ret = platform_device_add(collie_pm_device);
+
+        if (ret)
+                platform_device_put(collie_pm_device);
+
+	if (!ret)
+		ret = ucb1x00_register_driver(&collie_pm_ucb_driver);
+
+	return ret;
+}
+
+static void __exit collie_pm_exit(void)
+{
+	ucb1x00_unregister_driver(&collie_pm_ucb_driver);
+        platform_device_unregister(collie_pm_device);
+}
+
+module_init(collie_pm_init);
+module_exit(collie_pm_exit);

arch/arm/mm/Kconfig

@@ -266,12 +266,18 @@ config CPU_32v6K
 # This defines the compiler instruction set which depends on the machine type.
 config CPU_32v3
 	bool
+	select TLS_REG_EMUL if SMP
+	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 
 config CPU_32v4
 	bool
+	select TLS_REG_EMUL if SMP
+	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 
 config CPU_32v5
 	bool
+	select TLS_REG_EMUL if SMP
+	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 
 config CPU_32v6
 	bool
@@ -417,7 +423,6 @@ config CPU_BPREDICT_DISABLE
 
 config TLS_REG_EMUL
 	bool
-	default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
 	help
 	  An SMP system using a pre-ARMv6 processor (there are apparently
 	  a few prototypes like that in existence) and therefore access to
@@ -436,7 +441,6 @@ config HAS_TLS_REG
 
 config NEEDS_SYSCALL_FOR_CMPXCHG
 	bool
-	default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
 	help
 	  SMP on a pre-ARMv6 processor?  Well OK then.
 	  Forget about fast user space cmpxchg support.

arch/arm/mm/proc-arm1020.S

@@ -29,6 +29,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>

arch/arm/mm/proc-arm1020e.S

@@ -29,6 +29,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>

arch/arm/mm/proc-arm1022.S

@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>

arch/arm/mm/proc-arm1026.S

@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>

arch/arm/mm/proc-arm6_7.S

@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>

arch/arm/mm/proc-arm720.S

@@ -34,6 +34,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>

arch/arm/mm/proc-arm920.S

@@ -28,6 +28,7 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/page.h>