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Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm tree changes from Dave Airlie:
"This is the main drm pull request, I have some overlap with sound and
arm-soc, the sound patch is acked and may conflict based on -next
reports but should be a trivial fixup, which I'll leave to you!
Highlights:
- new drivers:
MSM driver from Rob Clark
- non-drm:
switcheroo and hdmi audio driver support for secondary GPU
poweroff, so drivers can use runtime PM to poweroff the GPUs. This
can save 5 or 6W on some optimus laptops.
- drm core:
combined GEM and TTM VMA manager
per-filp mmap permission tracking
initial rendernode support (via a runtime enable for now, until we get api stable),
remove old proc support,
lots of cleanups of legacy code
hdmi vendor infoframes and 4k modes
lots of gem/prime locking and races fixes
async pageflip scaffolding
drm bridge objects
- i915:
Haswell PC8+ support and eLLC support, HDMI 4K support, initial
per-process VMA pieces, watermark reworks, convert to generic hdmi
infoframes, encoder reworking, fastboot support,
- radeon:
CIK PM support, remove 3d blit code in favour of DMA engines,
Berlin GPU support, HDMI audio fixes
- nouveau:
secondary GPU power down support for optimus laptops, lots of
fixes, use MSI, VP3 engine support
- exynos:
runtime pm support for g2d, DT support, remove non-DT,
- tda998x i2c driver:
lots of fixes for sync issues
- gma500:
lots of cleanups
- rcar:
add LVDS support, fbdev emulation,
- tegra:
just minor fixes"
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (684 commits)
drm/exynos: Fix build error with exynos_drm_connector.c
drm/exynos: Remove non-DT support in exynos_drm_fimd
drm/exynos: Remove non-DT support in exynos_hdmi
drm/exynos: Remove non-DT support in exynos_drm_g2d
drm/exynos: Remove non-DT support in exynos_hdmiphy
drm/exynos: Remove non-DT support in exynos_ddc
drm/exynos: Make Exynos DRM drivers depend on OF
drm/exynos: Consider fallback option to allocation fail
drm/exynos: fimd: move platform data parsing to separate function
drm/exynos: fimd: get signal polarities from device tree
drm/exynos: fimd: replace struct fb_videomode with videomode
drm/exynos: check a pixel format to a particular window layer
drm/exynos: fix fimd pixel format setting
drm/exynos: Add NULL pointer check
drm/exynos: Remove redundant error messages
drm/exynos: Add missing of.h header include
drm/exynos: Remove redundant NULL check in exynos_drm_buf
drm/exynos: add device tree support for rotator
drm/exynos: Add missing includes
drm/exynos: add runtime pm interfaces to g2d driver
...
This commit is contained in:
Linus Torvalds
@@ -16,3 +16,4 @@ header-y += sis_drm.h
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header-y += tegra_drm.h
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header-y += via_drm.h
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header-y += vmwgfx_drm.h
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header-y += msm_drm.h
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@@ -181,7 +181,7 @@ enum drm_map_type {
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_DRM_AGP = 3, /**< AGP/GART */
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_DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
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_DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
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_DRM_GEM = 6, /**< GEM object */
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_DRM_GEM = 6, /**< GEM object (obsolete) */
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};
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/**
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@@ -780,6 +780,7 @@ struct drm_event_vblank {
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#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
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#define DRM_CAP_PRIME 0x5
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#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
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#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
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#define DRM_PRIME_CAP_IMPORT 0x1
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#define DRM_PRIME_CAP_EXPORT 0x2
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@@ -412,7 +412,8 @@ struct drm_mode_crtc_lut {
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};
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#define DRM_MODE_PAGE_FLIP_EVENT 0x01
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#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
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#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
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#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC)
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/*
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* Request a page flip on the specified crtc.
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@@ -426,11 +427,14 @@ struct drm_mode_crtc_lut {
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* flip is already pending as the ioctl is called, EBUSY will be
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* returned.
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*
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* The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
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* request that drm sends back a vblank event (see drm.h: struct
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* drm_event_vblank) when the page flip is done. The user_data field
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* passed in with this ioctl will be returned as the user_data field
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* in the vblank event struct.
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* Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank
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* event (see drm.h: struct drm_event_vblank) when the page flip is
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* done. The user_data field passed in with this ioctl will be
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* returned as the user_data field in the vblank event struct.
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*
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* Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen
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* 'as soon as possible', meaning that it not delay waiting for vblank.
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* This may cause tearing on the screen.
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*
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* The reserved field must be zero until we figure out something
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* clever to use it for.
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@@ -33,6 +33,30 @@
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* subject to backwards-compatibility constraints.
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*/
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/**
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* DOC: uevents generated by i915 on it's device node
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*
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* I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
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* event from the gpu l3 cache. Additional information supplied is ROW,
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* BANK, SUBBANK of the affected cacheline. Userspace should keep track of
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* these events and if a specific cache-line seems to have a persistent
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* error remap it with the l3 remapping tool supplied in intel-gpu-tools.
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* The value supplied with the event is always 1.
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*
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* I915_ERROR_UEVENT - Generated upon error detection, currently only via
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* hangcheck. The error detection event is a good indicator of when things
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* began to go badly. The value supplied with the event is a 1 upon error
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* detection, and a 0 upon reset completion, signifying no more error
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* exists. NOTE: Disabling hangcheck or reset via module parameter will
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* cause the related events to not be seen.
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*
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* I915_RESET_UEVENT - Event is generated just before an attempt to reset the
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* the GPU. The value supplied with the event is always 1. NOTE: Disable
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* reset via module parameter will cause this event to not be seen.
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*/
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#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
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#define I915_ERROR_UEVENT "ERROR"
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#define I915_RESET_UEVENT "RESET"
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/* Each region is a minimum of 16k, and there are at most 255 of them.
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*/
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@@ -310,6 +334,7 @@ typedef struct drm_i915_irq_wait {
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#define I915_PARAM_HAS_PINNED_BATCHES 24
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#define I915_PARAM_HAS_EXEC_NO_RELOC 25
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#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
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#define I915_PARAM_HAS_WT 27
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typedef struct drm_i915_getparam {
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int param;
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@@ -744,8 +769,32 @@ struct drm_i915_gem_busy {
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__u32 busy;
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};
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/**
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* I915_CACHING_NONE
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*
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* GPU access is not coherent with cpu caches. Default for machines without an
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* LLC.
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*/
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#define I915_CACHING_NONE 0
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/**
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* I915_CACHING_CACHED
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*
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* GPU access is coherent with cpu caches and furthermore the data is cached in
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* last-level caches shared between cpu cores and the gpu GT. Default on
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* machines with HAS_LLC.
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*/
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#define I915_CACHING_CACHED 1
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/**
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* I915_CACHING_DISPLAY
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*
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* Special GPU caching mode which is coherent with the scanout engines.
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* Transparently falls back to I915_CACHING_NONE on platforms where no special
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* cache mode (like write-through or gfdt flushing) is available. The kernel
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* automatically sets this mode when using a buffer as a scanout target.
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* Userspace can manually set this mode to avoid a costly stall and clflush in
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* the hotpath of drawing the first frame.
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*/
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#define I915_CACHING_DISPLAY 2
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struct drm_i915_gem_caching {
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/**
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@@ -0,0 +1,207 @@
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MSM_DRM_H__
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#define __MSM_DRM_H__
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#include <stddef.h>
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#include <drm/drm.h>
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints:
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* 1) Do not use pointers, use uint64_t instead for 32 bit / 64 bit
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* user/kernel compatibility
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* 2) Keep fields aligned to their size
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* 3) Because of how drm_ioctl() works, we can add new fields at
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* the end of an ioctl if some care is taken: drm_ioctl() will
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* zero out the new fields at the tail of the ioctl, so a zero
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* value should have a backwards compatible meaning. And for
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* output params, userspace won't see the newly added output
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* fields.. so that has to be somehow ok.
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*/
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#define MSM_PIPE_NONE 0x00
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#define MSM_PIPE_2D0 0x01
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#define MSM_PIPE_2D1 0x02
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#define MSM_PIPE_3D0 0x10
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/* timeouts are specified in clock-monotonic absolute times (to simplify
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* restarting interrupted ioctls). The following struct is logically the
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* same as 'struct timespec' but 32/64b ABI safe.
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*/
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struct drm_msm_timespec {
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int64_t tv_sec; /* seconds */
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int64_t tv_nsec; /* nanoseconds */
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};
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#define MSM_PARAM_GPU_ID 0x01
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#define MSM_PARAM_GMEM_SIZE 0x02
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struct drm_msm_param {
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uint32_t pipe; /* in, MSM_PIPE_x */
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uint32_t param; /* in, MSM_PARAM_x */
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uint64_t value; /* out (get_param) or in (set_param) */
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};
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/*
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* GEM buffers:
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*/
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#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
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#define MSM_BO_GPU_READONLY 0x00000002
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#define MSM_BO_CACHE_MASK 0x000f0000
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/* cache modes */
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#define MSM_BO_CACHED 0x00010000
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#define MSM_BO_WC 0x00020000
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#define MSM_BO_UNCACHED 0x00040000
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struct drm_msm_gem_new {
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uint64_t size; /* in */
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uint32_t flags; /* in, mask of MSM_BO_x */
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uint32_t handle; /* out */
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};
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struct drm_msm_gem_info {
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uint32_t handle; /* in */
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uint32_t pad;
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uint64_t offset; /* out, offset to pass to mmap() */
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};
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#define MSM_PREP_READ 0x01
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#define MSM_PREP_WRITE 0x02
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#define MSM_PREP_NOSYNC 0x04
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struct drm_msm_gem_cpu_prep {
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uint32_t handle; /* in */
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uint32_t op; /* in, mask of MSM_PREP_x */
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struct drm_msm_timespec timeout; /* in */
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};
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struct drm_msm_gem_cpu_fini {
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uint32_t handle; /* in */
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};
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/*
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* Cmdstream Submission:
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*/
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/* The value written into the cmdstream is logically:
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*
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* ((relocbuf->gpuaddr + reloc_offset) << shift) | or
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*
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* When we have GPU's w/ >32bit ptrs, it should be possible to deal
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* with this by emit'ing two reloc entries with appropriate shift
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* values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
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*
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* NOTE that reloc's must be sorted by order of increasing submit_offset,
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* otherwise EINVAL.
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*/
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struct drm_msm_gem_submit_reloc {
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uint32_t submit_offset; /* in, offset from submit_bo */
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uint32_t or; /* in, value OR'd with result */
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int32_t shift; /* in, amount of left shift (can be negative) */
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uint32_t reloc_idx; /* in, index of reloc_bo buffer */
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uint64_t reloc_offset; /* in, offset from start of reloc_bo */
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};
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/* submit-types:
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* BUF - this cmd buffer is executed normally.
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* IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
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* processed normally, but the kernel does not setup an IB to
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* this buffer in the first-level ringbuffer
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* CTX_RESTORE_BUF - only executed if there has been a GPU context
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* switch since the last SUBMIT ioctl
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*/
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#define MSM_SUBMIT_CMD_BUF 0x0001
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#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
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#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
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struct drm_msm_gem_submit_cmd {
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uint32_t type; /* in, one of MSM_SUBMIT_CMD_x */
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uint32_t submit_idx; /* in, index of submit_bo cmdstream buffer */
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uint32_t submit_offset; /* in, offset into submit_bo */
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uint32_t size; /* in, cmdstream size */
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uint32_t pad;
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uint32_t nr_relocs; /* in, number of submit_reloc's */
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uint64_t __user relocs; /* in, ptr to array of submit_reloc's */
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};
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/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
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* cmdstream buffer(s) themselves or reloc entries) has one (and only
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* one) entry in the submit->bos[] table.
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*
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* As a optimization, the current buffer (gpu virtual address) can be
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* passed back through the 'presumed' field. If on a subsequent reloc,
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* userspace passes back a 'presumed' address that is still valid,
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* then patching the cmdstream for this entry is skipped. This can
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* avoid kernel needing to map/access the cmdstream bo in the common
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* case.
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*/
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#define MSM_SUBMIT_BO_READ 0x0001
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#define MSM_SUBMIT_BO_WRITE 0x0002
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struct drm_msm_gem_submit_bo {
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uint32_t flags; /* in, mask of MSM_SUBMIT_BO_x */
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uint32_t handle; /* in, GEM handle */
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uint64_t presumed; /* in/out, presumed buffer address */
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};
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/* Each cmdstream submit consists of a table of buffers involved, and
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* one or more cmdstream buffers. This allows for conditional execution
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* (context-restore), and IB buffers needed for per tile/bin draw cmds.
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*/
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struct drm_msm_gem_submit {
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uint32_t pipe; /* in, MSM_PIPE_x */
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uint32_t fence; /* out */
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uint32_t nr_bos; /* in, number of submit_bo's */
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uint32_t nr_cmds; /* in, number of submit_cmd's */
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uint64_t __user bos; /* in, ptr to array of submit_bo's */
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uint64_t __user cmds; /* in, ptr to array of submit_cmd's */
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};
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/* The normal way to synchronize with the GPU is just to CPU_PREP on
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* a buffer if you need to access it from the CPU (other cmdstream
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* submission from same or other contexts, PAGE_FLIP ioctl, etc, all
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* handle the required synchronization under the hood). This ioctl
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* mainly just exists as a way to implement the gallium pipe_fence
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* APIs without requiring a dummy bo to synchronize on.
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*/
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struct drm_msm_wait_fence {
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uint32_t fence; /* in */
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uint32_t pad;
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struct drm_msm_timespec timeout; /* in */
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};
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#define DRM_MSM_GET_PARAM 0x00
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/* placeholder:
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#define DRM_MSM_SET_PARAM 0x01
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*/
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#define DRM_MSM_GEM_NEW 0x02
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#define DRM_MSM_GEM_INFO 0x03
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#define DRM_MSM_GEM_CPU_PREP 0x04
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#define DRM_MSM_GEM_CPU_FINI 0x05
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#define DRM_MSM_GEM_SUBMIT 0x06
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#define DRM_MSM_WAIT_FENCE 0x07
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#define DRM_MSM_NUM_IOCTLS 0x08
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#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
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#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
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#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
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#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
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#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
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#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
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#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
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#endif /* __MSM_DRM_H__ */
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@@ -979,6 +979,8 @@ struct drm_radeon_cs {
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#define RADEON_INFO_RING_WORKING 0x15
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/* SI tile mode array */
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#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
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/* query if CP DMA is supported on the compute ring */
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#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
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struct drm_radeon_info {
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