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MIPS: OCTEON: Rename Kconfig CAVIUM_OCTEON_REFERENCE_BOARD to CAVIUM_OCTEON_SOC
CAVIUM_OCTEON_SOC most place we used to use CPU_CAVIUM_OCTEON. This allows us to CPU_CAVIUM_OCTEON in places where we have no OCTEON SOC. Remove CAVIUM_OCTEON_SIMULATOR as it doesn't really do anything, we can get the same configuration with CAVIUM_OCTEON_SOC. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-ide@vger.kernel.org Cc: linux-edac@vger.kernel.org Cc: linux-i2c@vger.kernel.org Cc: netdev@vger.kernel.org Cc: spi-devel-general@lists.sourceforge.net Cc: devel@driverdev.osuosl.org Cc: linux-usb@vger.kernel.org Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com> Patchwork: https://patchwork.linux-mips.org/patch/5295/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle
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@@ -349,21 +349,21 @@ config EDAC_OCTEON_PC
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config EDAC_OCTEON_L2C
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tristate "Cavium Octeon Secondary Caches (L2C)"
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depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
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depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
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help
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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config EDAC_OCTEON_LMC
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tristate "Cavium Octeon DRAM Memory Controller (LMC)"
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depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
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depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
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help
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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config EDAC_OCTEON_PCI
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tristate "Cavium Octeon PCI Controller"
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depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
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depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
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help
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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