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arm: sunxi: Revert changes merged through net-next.
This reverts commits2c0cba482e("arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control module") to2428fd0fe5("arm64: defconfig: Enable dwmac-sun8i driver on defconfig") and3432a86e64("arm: sun8i: orangepipc: use internal phy-mode") to5a79b4f2a5("arm: sun8i: orangepi-2: use internal phy-mode") that should be merged through the arm-soc tree, and end up in merge conflicts and build failures. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller
parent
f1efece4e2
commit
9d46b7701c
@@ -67,14 +67,6 @@
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};
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};
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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phy-mode = "rgmii";
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phy-handle = <&ext_rgmii_phy>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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@@ -85,13 +77,6 @@
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bias-pull-up;
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};
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&mdio {
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ext_rgmii_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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@@ -46,20 +46,5 @@
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model = "Pine64+";
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compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
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/* TODO: Camera, touchscreen, etc. */
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};
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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phy-mode = "rgmii";
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phy-handle = <&ext_rgmii_phy>;
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status = "okay";
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};
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&mdio {
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ext_rgmii_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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/* TODO: Camera, Ethernet PHY, touchscreen, etc. */
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};
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@@ -70,15 +70,6 @@
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status = "okay";
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};
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&rmii_pins>;
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phy-mode = "rmii";
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phy-handle = <&ext_rmii_phy1>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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@@ -89,13 +80,6 @@
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bias-pull-up;
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};
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&mdio {
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ext_rmii_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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@@ -129,12 +129,6 @@
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#size-cells = <1>;
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ranges;
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syscon: syscon@1c00000 {
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compatible = "allwinner,sun50i-a64-system-controller",
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"syscon";
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reg = <0x01c00000 0x1000>;
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c0f000 0x1000>;
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@@ -287,21 +281,6 @@
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bias-pull-up;
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};
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rmii_pins: rmii_pins {
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pins = "PD10", "PD11", "PD13", "PD14", "PD17",
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"PD18", "PD19", "PD20", "PD22", "PD23";
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function = "emac";
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drive-strength = <40>;
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};
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rgmii_pins: rgmii_pins {
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pins = "PD8", "PD9", "PD10", "PD11", "PD12",
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"PD13", "PD15", "PD16", "PD17", "PD18",
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"PD19", "PD20", "PD21", "PD22", "PD23";
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function = "emac";
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drive-strength = <40>;
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};
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uart0_pins_a: uart0@0 {
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pins = "PB8", "PB9";
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function = "uart0";
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@@ -406,26 +385,6 @@
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#size-cells = <0>;
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};
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emac: ethernet@1c30000 {
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compatible = "allwinner,sun50i-a64-emac";
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syscon = <&syscon>;
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reg = <0x01c30000 0x100>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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reset-names = "stmmaceth";
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clocks = <&ccu CLK_BUS_EMAC>;
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clock-names = "stmmaceth";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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gic: interrupt-controller@1c81000 {
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compatible = "arm,gic-400";
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reg = <0x01c81000 0x1000>,
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