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Merge commit 'v2.6.38-rc8' into spi/next
Conflicts: drivers/spi/pxa2xx_spi_pci.c
This commit is contained in:
Grant Likely
@@ -0,0 +1,29 @@
|
||||
* Freescale 8xxx/3.0 Gb/s SATA nodes
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA port should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-sata", where CHIP is the processor
|
||||
(mpc8315, mpc8379, etc.) and the second is
|
||||
"fsl,pq-sata"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- cell-index : controller index.
|
||||
1 for controller @ 0x18000
|
||||
2 for controller @ 0x19000
|
||||
3 for controller @ 0x1a000
|
||||
4 for controller @ 0x1b000
|
||||
|
||||
Optional properties:
|
||||
- interrupt-parent : optional, if needed for interrupt mapping
|
||||
- reg : <registers mapping>
|
||||
|
||||
Example:
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
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||||
reg = <0x18000 0x1000>;
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||||
cell-index = <1>;
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||||
interrupts = <2c 8>;
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||||
interrupt-parent = < &ipic >;
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||||
};
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||||
@@ -0,0 +1,28 @@
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||||
EEPROMs (I2C)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "<manufacturer>,<type>"
|
||||
If there is no specific driver for <manufacturer>, a generic
|
||||
driver based on <type> is selected. Possible types are:
|
||||
24c00, 24c01, 24c02, 24c04, 24c08, 24c16, 24c32, 24c64,
|
||||
24c128, 24c256, 24c512, 24c1024, spd
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||||
|
||||
- reg : the I2C address of the EEPROM
|
||||
|
||||
Optional properties:
|
||||
|
||||
- pagesize : the length of the pagesize for writing. Please consult the
|
||||
manual of your device, that value varies a lot. A wrong value
|
||||
may result in data loss! If not specified, a safety value of
|
||||
'1' is used which will be very slow.
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||||
|
||||
- read-only: this parameterless property disables writes to the eeprom
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||||
|
||||
Example:
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||||
|
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eeprom@52 {
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compatible = "atmel,24c32";
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reg = <0x52>;
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||||
pagesize = <32>;
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};
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@@ -0,0 +1,60 @@
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GPIO controllers on MPC8xxx SoCs
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||||
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||||
This is for the non-QE/CPM/GUTs GPIO controllers as found on
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8349, 8572, 8610 and compatible.
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|
||||
Every GPIO controller node must have #gpio-cells property defined,
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this information will be used to translate gpio-specifiers.
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|
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Required properties:
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||||
- compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for
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83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
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- #gpio-cells : Should be two. The first cell is the pin number and the
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||||
second cell is used to specify optional parameters (currently unused).
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- interrupts : Interrupt mapping for GPIO IRQ.
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- interrupt-parent : Phandle for the interrupt controller that
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services interrupts for this device.
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- gpio-controller : Marks the port as GPIO controller.
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||||
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||||
Example of gpio-controller nodes for a MPC8347 SoC:
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gpio1: gpio-controller@c00 {
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#gpio-cells = <2>;
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||||
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
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reg = <0xc00 0x100>;
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interrupts = <74 0x8>;
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interrupt-parent = <&ipic>;
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||||
gpio-controller;
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};
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|
||||
gpio2: gpio-controller@d00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
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reg = <0xd00 0x100>;
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interrupts = <75 0x8>;
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||||
interrupt-parent = <&ipic>;
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||||
gpio-controller;
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};
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||||
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||||
See booting-without-of.txt for details of how to specify GPIO
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||||
information for devices.
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||||
|
||||
To use GPIO pins as interrupt sources for peripherals, specify the
|
||||
GPIO controller as the interrupt parent and define GPIO number +
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||||
trigger mode using the interrupts property, which is defined like
|
||||
this:
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||||
|
||||
interrupts = <number trigger>, where:
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||||
- number: GPIO pin (0..31)
|
||||
- trigger: trigger mode:
|
||||
2 = trigger on falling edge
|
||||
3 = trigger on both edges
|
||||
|
||||
Example of device using this is:
|
||||
|
||||
funkyfpga@0 {
|
||||
compatible = "funky-fpga";
|
||||
...
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||||
interrupts = <4 3>;
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||||
interrupt-parent = <&gpio1>;
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||||
};
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||||
@@ -0,0 +1,50 @@
|
||||
Specifying GPIO information for devices
|
||||
============================================
|
||||
|
||||
1) gpios property
|
||||
-----------------
|
||||
|
||||
Nodes that makes use of GPIOs should define them using `gpios' property,
|
||||
format of which is: <&gpio-controller1-phandle gpio1-specifier
|
||||
&gpio-controller2-phandle gpio2-specifier
|
||||
0 /* holes are permitted, means no GPIO 3 */
|
||||
&gpio-controller4-phandle gpio4-specifier
|
||||
...>;
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||||
|
||||
Note that gpio-specifier length is controller dependent.
|
||||
|
||||
gpio-specifier may encode: bank, pin position inside the bank,
|
||||
whether pin is open-drain and whether pin is logically inverted.
|
||||
|
||||
Example of the node using GPIOs:
|
||||
|
||||
node {
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gpios = <&qe_pio_e 18 0>;
|
||||
};
|
||||
|
||||
In this example gpio-specifier is "18 0" and encodes GPIO pin number,
|
||||
and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
|
||||
|
||||
2) gpio-controller nodes
|
||||
------------------------
|
||||
|
||||
Every GPIO controller node must have #gpio-cells property defined,
|
||||
this information will be used to translate gpio-specifiers.
|
||||
|
||||
Example of two SOC GPIO banks defined as gpio-controller nodes:
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||||
qe_pio_a: gpio-controller@1400 {
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#gpio-cells = <2>;
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||||
compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
|
||||
reg = <0x1400 0x18>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
qe_pio_e: gpio-controller@1460 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
|
||||
reg = <0x1460 0x18>;
|
||||
gpio-controller;
|
||||
};
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||||
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||||
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@@ -0,0 +1,58 @@
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||||
LEDs connected to GPIO lines
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "gpio-leds".
|
||||
|
||||
Each LED is represented as a sub-node of the gpio-leds device. Each
|
||||
node's name represents the name of the corresponding LED.
|
||||
|
||||
LED sub-node properties:
|
||||
- gpios : Should specify the LED's GPIO, see "Specifying GPIO information
|
||||
for devices" in Documentation/powerpc/booting-without-of.txt. Active
|
||||
low LEDs should be indicated using flags in the GPIO specifier.
|
||||
- label : (optional) The label for this LED. If omitted, the label is
|
||||
taken from the node name (excluding the unit address).
|
||||
- linux,default-trigger : (optional) This parameter, if present, is a
|
||||
string defining the trigger assigned to the LED. Current triggers are:
|
||||
"backlight" - LED will act as a back-light, controlled by the framebuffer
|
||||
system
|
||||
"default-on" - LED will turn on, but see "default-state" below
|
||||
"heartbeat" - LED "double" flashes at a load average based rate
|
||||
"ide-disk" - LED indicates disk activity
|
||||
"timer" - LED flashes at a fixed, configurable rate
|
||||
- default-state: (optional) The initial state of the LED. Valid
|
||||
values are "on", "off", and "keep". If the LED is already on or off
|
||||
and the default-state property is set the to same value, then no
|
||||
glitch should be produced where the LED momentarily turns off (or
|
||||
on). The "keep" setting will keep the LED at whatever its current
|
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state is, without producing a glitch. The default is off if this
|
||||
property is not present.
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||||
Examples:
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||||
leds {
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compatible = "gpio-leds";
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hdd {
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||||
label = "IDE Activity";
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gpios = <&mcu_pio 0 1>; /* Active low */
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linux,default-trigger = "ide-disk";
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};
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fault {
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gpios = <&mcu_pio 1 0>;
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/* Keep LED on if BIOS detected hardware fault */
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default-state = "keep";
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};
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};
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run-control {
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compatible = "gpio-leds";
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red {
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gpios = <&mpc8572 6 0>;
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default-state = "off";
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};
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green {
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gpios = <&mpc8572 7 0>;
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default-state = "on";
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};
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}
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@@ -0,0 +1,64 @@
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* I2C
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Required properties :
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- reg : Offset and length of the register set for the device
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||||
- compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
|
||||
compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
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mpc5200 or mpc5200b. For the mpc5121, an additional node
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"fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
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Recommended properties :
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||||
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- interrupts : <a b> where a is the interrupt number and b is a
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field that represents an encoding of the sense and level
|
||||
information for the interrupt. This should be encoded based on
|
||||
the information in section 2) depending on the type of interrupt
|
||||
controller you have.
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||||
- interrupt-parent : the phandle for the interrupt controller that
|
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services interrupts for this device.
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||||
- fsl,preserve-clocking : boolean; if defined, the clock settings
|
||||
from the bootloader are preserved (not touched).
|
||||
- clock-frequency : desired I2C bus clock frequency in Hz.
|
||||
- fsl,timeout : I2C bus timeout in microseconds.
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|
||||
Examples :
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/* MPC5121 based board */
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i2c@1740 {
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#address-cells = <1>;
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#size-cells = <0>;
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||||
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1740 0x20>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <100000>;
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};
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i2ccontrol@1760 {
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||||
compatible = "fsl,mpc5121-i2c-ctrl";
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||||
reg = <0x1760 0x8>;
|
||||
};
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||||
|
||||
/* MPC5200B based board */
|
||||
i2c@3d00 {
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||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
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||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
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reg = <0x3d00 0x40>;
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||||
interrupts = <2 15 0>;
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||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,preserve-clocking;
|
||||
};
|
||||
|
||||
/* MPC8544 base board */
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc8544-i2c", "fsl-i2c";
|
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reg = <0x3100 0x100>;
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||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
clock-frequency = <400000>;
|
||||
fsl,timeout = <10000>;
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,29 @@
|
||||
* Freescale Enhanced Secure Digital Host Controller (eSDHC)
|
||||
|
||||
The Enhanced Secure Digital Host Controller provides an interface
|
||||
for MMC, SD, and SDIO types of memory cards.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be
|
||||
"fsl,<chip>-esdhc", "fsl,esdhc"
|
||||
- reg : should contain eSDHC registers location and length.
|
||||
- interrupts : should contain eSDHC interrupt.
|
||||
- interrupt-parent : interrupt source phandle.
|
||||
- clock-frequency : specifies eSDHC base clock frequency.
|
||||
- sdhci,wp-inverted : (optional) specifies that eSDHC controller
|
||||
reports inverted write-protect state;
|
||||
- sdhci,1-bit-only : (optional) specifies that a controller can
|
||||
only handle 1-bit data transfers.
|
||||
- sdhci,auto-cmd12: (optional) specifies that a controller can
|
||||
only handle auto CMD12.
|
||||
|
||||
Example:
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
@@ -0,0 +1,30 @@
|
||||
MMC/SD/SDIO slot directly connected to a SPI bus
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "mmc-spi-slot".
|
||||
- reg : should specify SPI address (chip-select number).
|
||||
- spi-max-frequency : maximum frequency for this device (Hz).
|
||||
- voltage-ranges : two cells are required, first cell specifies minimum
|
||||
slot voltage (mV), second cell specifies maximum slot voltage (mV).
|
||||
Several ranges could be specified.
|
||||
|
||||
Optional properties:
|
||||
- gpios : may specify GPIOs in this order: Card-Detect GPIO,
|
||||
Write-Protect GPIO.
|
||||
- interrupts : the interrupt of a card detect interrupt.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
|
||||
Example:
|
||||
|
||||
mmc-slot@0 {
|
||||
compatible = "fsl,mpc8323rdb-mmc-slot",
|
||||
"mmc-spi-slot";
|
||||
reg = <0>;
|
||||
gpios = <&qe_pio_d 14 1
|
||||
&qe_pio_d 15 0>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
spi-max-frequency = <50000000>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
@@ -0,0 +1,63 @@
|
||||
Freescale Localbus UPM programmed to work with NAND flash
|
||||
|
||||
Required properties:
|
||||
- compatible : "fsl,upm-nand".
|
||||
- reg : should specify localbus chip select and size used for the chip.
|
||||
- fsl,upm-addr-offset : UPM pattern offset for the address latch.
|
||||
- fsl,upm-cmd-offset : UPM pattern offset for the command latch.
|
||||
|
||||
Optional properties:
|
||||
- fsl,upm-wait-flags : add chip-dependent short delays after running the
|
||||
UPM pattern (0x1), after writing a data byte (0x2) or after
|
||||
writing out a buffer (0x4).
|
||||
- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
|
||||
The corresponding address lines are used to select the chip.
|
||||
- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
|
||||
(R/B#). For multi-chip devices, "n" GPIO definitions are required
|
||||
according to the number of chips.
|
||||
- chip-delay : chip dependent delay for transfering data from array to
|
||||
read registers (tR). Required if property "gpios" is not used
|
||||
(R/B# pins not connected).
|
||||
|
||||
Examples:
|
||||
|
||||
upm@1,0 {
|
||||
compatible = "fsl,upm-nand";
|
||||
reg = <1 0 1>;
|
||||
fsl,upm-addr-offset = <16>;
|
||||
fsl,upm-cmd-offset = <8>;
|
||||
gpios = <&qe_pio_e 18 0>;
|
||||
|
||||
flash {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "...";
|
||||
|
||||
partition@0 {
|
||||
...
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
upm@3,0 {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
|
||||
reg = <3 0x0 0x800>;
|
||||
fsl,upm-addr-offset = <0x10>;
|
||||
fsl,upm-cmd-offset = <0x08>;
|
||||
/* Multi-chip NAND device */
|
||||
fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
|
||||
fsl,upm-wait-flags = <0x5>;
|
||||
chip-delay = <25>; // in micro-seconds
|
||||
|
||||
nand@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "fs";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,90 @@
|
||||
CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
|
||||
|
||||
Flash chips (Memory Technology Devices) are often used for solid state
|
||||
file systems on embedded devices.
|
||||
|
||||
- compatible : should contain the specific model of mtd chip(s)
|
||||
used, if known, followed by either "cfi-flash", "jedec-flash"
|
||||
or "mtd-ram".
|
||||
- reg : Address range(s) of the mtd chip(s)
|
||||
It's possible to (optionally) define multiple "reg" tuples so that
|
||||
non-identical chips can be described in one node.
|
||||
- bank-width : Width (in bytes) of the bank. Equal to the
|
||||
device width times the number of interleaved chips.
|
||||
- device-width : (optional) Width of a single mtd chip. If
|
||||
omitted, assumed to be equal to 'bank-width'.
|
||||
- #address-cells, #size-cells : Must be present if the device has
|
||||
sub-nodes representing partitions (see below). In this case
|
||||
both #address-cells and #size-cells must be equal to 1.
|
||||
|
||||
For JEDEC compatible devices, the following additional properties
|
||||
are defined:
|
||||
|
||||
- vendor-id : Contains the flash chip's vendor id (1 byte).
|
||||
- device-id : Contains the flash chip's device id (1 byte).
|
||||
|
||||
In addition to the information on the mtd bank itself, the
|
||||
device tree may optionally contain additional information
|
||||
describing partitions of the address space. This can be
|
||||
used on platforms which have strong conventions about which
|
||||
portions of a flash are used for what purposes, but which don't
|
||||
use an on-flash partition table such as RedBoot.
|
||||
|
||||
Each partition is represented as a sub-node of the mtd device.
|
||||
Each node's name represents the name of the corresponding
|
||||
partition of the mtd device.
|
||||
|
||||
Flash partitions
|
||||
- reg : The partition's offset and size within the mtd bank.
|
||||
- label : (optional) The label / name for this partition.
|
||||
If omitted, the label is taken from the node name (excluding
|
||||
the unit address).
|
||||
- read-only : (optional) This parameter, if present, is a hint to
|
||||
Linux that this partition should only be mounted
|
||||
read-only. This is usually used for flash partitions
|
||||
containing early-boot firmware images or data which should not
|
||||
be clobbered.
|
||||
|
||||
Example:
|
||||
|
||||
flash@ff000000 {
|
||||
compatible = "amd,am29lv128ml", "cfi-flash";
|
||||
reg = <ff000000 01000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
fs@0 {
|
||||
label = "fs";
|
||||
reg = <0 f80000>;
|
||||
};
|
||||
firmware@f80000 {
|
||||
label ="firmware";
|
||||
reg = <f80000 80000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
Here an example with multiple "reg" tuples:
|
||||
|
||||
flash@f0000000,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "intel,PC48F4400P0VB", "cfi-flash";
|
||||
reg = <0 0x00000000 0x02000000
|
||||
0 0x02000000 0x02000000>;
|
||||
bank-width = <2>;
|
||||
partition@0 {
|
||||
label = "test-part1";
|
||||
reg = <0 0x04000000>;
|
||||
};
|
||||
};
|
||||
|
||||
An example using SRAM:
|
||||
|
||||
sram@2,0 {
|
||||
compatible = "samsung,k6f1616u6a", "mtd-ram";
|
||||
reg = <2 0 0x00200000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
CAN Device Tree Bindings
|
||||
------------------------
|
||||
|
||||
(c) 2006-2009 Secret Lab Technologies Ltd
|
||||
Grant Likely <grant.likely@secretlab.ca>
|
||||
|
||||
fsl,mpc5200-mscan nodes
|
||||
-----------------------
|
||||
In addition to the required compatible-, reg- and interrupt-properties, you can
|
||||
also specify which clock source shall be used for the controller:
|
||||
|
||||
- fsl,mscan-clock-source : a string describing the clock source. Valid values
|
||||
are: "ip" for ip bus clock
|
||||
"ref" for reference clock (XTAL)
|
||||
"ref" is default in case this property is not
|
||||
present.
|
||||
|
||||
fsl,mpc5121-mscan nodes
|
||||
-----------------------
|
||||
In addition to the required compatible-, reg- and interrupt-properties, you can
|
||||
also specify which clock source and divider shall be used for the controller:
|
||||
|
||||
- fsl,mscan-clock-source : a string describing the clock source. Valid values
|
||||
are: "ip" for ip bus clock
|
||||
"ref" for reference clock
|
||||
"sys" for system clock
|
||||
If this property is not present, an optimal CAN
|
||||
clock source and frequency based on the system
|
||||
clock will be selected. If this is not possible,
|
||||
the reference clock will be used.
|
||||
|
||||
- fsl,mscan-clock-divider: for the reference and system clock, an additional
|
||||
clock divider can be specified. By default, a
|
||||
value of 1 is used.
|
||||
|
||||
Note that the MPC5121 Rev. 1 processor is not supported.
|
||||
|
||||
Examples:
|
||||
can@1300 {
|
||||
compatible = "fsl,mpc5121-mscan";
|
||||
interrupts = <12 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
reg = <0x1300 0x80>;
|
||||
};
|
||||
|
||||
can@1380 {
|
||||
compatible = "fsl,mpc5121-mscan";
|
||||
interrupts = <13 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
reg = <0x1380 0x80>;
|
||||
fsl,mscan-clock-source = "ref";
|
||||
fsl,mscan-clock-divider = <3>;
|
||||
};
|
||||
@@ -0,0 +1,53 @@
|
||||
Memory mapped SJA1000 CAN controller from NXP (formerly Philips)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "nxp,sja1000".
|
||||
|
||||
- reg : should specify the chip select, address offset and size required
|
||||
to map the registers of the SJA1000. The size is usually 0x80.
|
||||
|
||||
- interrupts: property with a value describing the interrupt source
|
||||
(number and sensitivity) required for the SJA1000.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- nxp,external-clock-frequency : Frequency of the external oscillator
|
||||
clock in Hz. Note that the internal clock frequency used by the
|
||||
SJA1000 is half of that value. If not specified, a default value
|
||||
of 16000000 (16 MHz) is used.
|
||||
|
||||
- nxp,tx-output-mode : operation mode of the TX output control logic:
|
||||
<0x0> : bi-phase output mode
|
||||
<0x1> : normal output mode (default)
|
||||
<0x2> : test output mode
|
||||
<0x3> : clock output mode
|
||||
|
||||
- nxp,tx-output-config : TX output pin configuration:
|
||||
<0x01> : TX0 invert
|
||||
<0x02> : TX0 pull-down (default)
|
||||
<0x04> : TX0 pull-up
|
||||
<0x06> : TX0 push-pull
|
||||
<0x08> : TX1 invert
|
||||
<0x10> : TX1 pull-down
|
||||
<0x20> : TX1 pull-up
|
||||
<0x30> : TX1 push-pull
|
||||
|
||||
- nxp,clock-out-frequency : clock frequency in Hz on the CLKOUT pin.
|
||||
If not specified or if the specified value is 0, the CLKOUT pin
|
||||
will be disabled.
|
||||
|
||||
- nxp,no-comparator-bypass : Allows to disable the CAN input comperator.
|
||||
|
||||
For futher information, please have a look to the SJA1000 data sheet.
|
||||
|
||||
Examples:
|
||||
|
||||
can@3,100 {
|
||||
compatible = "nxp,sja1000";
|
||||
reg = <3 0x100 0x80>;
|
||||
interrupts = <2 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
nxp,external-clock-frequency = <16000000>;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,76 @@
|
||||
* MDIO IO device
|
||||
|
||||
The MDIO is a bus to which the PHY devices are connected. For each
|
||||
device that exists on this bus, a child node should be created. See
|
||||
the definition of the PHY node in booting-without-of.txt for an example
|
||||
of how to define a PHY.
|
||||
|
||||
Required properties:
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : Should define the compatible device type for the
|
||||
mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
|
||||
|
||||
Example:
|
||||
|
||||
mdio@24520 {
|
||||
reg = <24520 20>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
|
||||
ethernet-phy@0 {
|
||||
......
|
||||
};
|
||||
};
|
||||
|
||||
* TBI Internal MDIO bus
|
||||
|
||||
As of this writing, every tsec is associated with an internal TBI PHY.
|
||||
This PHY is accessed through the local MDIO bus. These buses are defined
|
||||
similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi".
|
||||
The TBI PHYs underneath them are similar to normal PHYs, but the reg property
|
||||
is considered instructive, rather than descriptive. The reg property should
|
||||
be chosen so it doesn't interfere with other PHYs on the bus.
|
||||
|
||||
* Gianfar-compatible ethernet nodes
|
||||
|
||||
Properties:
|
||||
|
||||
- device_type : Should be "network"
|
||||
- model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
|
||||
- compatible : Should be "gianfar"
|
||||
- reg : Offset and length of the register set for the device
|
||||
- local-mac-address : List of bytes representing the ethernet address of
|
||||
this controller
|
||||
- interrupts : For FEC devices, the first interrupt is the device's
|
||||
interrupt. For TSEC and eTSEC devices, the first interrupt is
|
||||
transmit, the second is receive, and the third is error.
|
||||
- phy-handle : The phandle for the PHY connected to this ethernet
|
||||
controller.
|
||||
- fixed-link : <a b c d e> where a is emulated phy id - choose any,
|
||||
but unique to the all specified fixed-links, b is duplex - 0 half,
|
||||
1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
|
||||
pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
|
||||
- phy-connection-type : a string naming the controller/PHY interface type,
|
||||
i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
|
||||
"tbi", or "rtbi". This property is only really needed if the connection
|
||||
is of type "rgmii-id", as all other connection types are detected by
|
||||
hardware.
|
||||
- fsl,magic-packet : If present, indicates that the hardware supports
|
||||
waking up via magic packet.
|
||||
- bd-stash : If present, indicates that the hardware supports stashing
|
||||
buffer descriptors in the L2.
|
||||
- rx-stash-len : Denotes the number of bytes of a received buffer to stash
|
||||
in the L2.
|
||||
- rx-stash-idx : Denotes the index of the first byte from the received
|
||||
buffer to stash in the L2.
|
||||
|
||||
Example:
|
||||
ethernet@24000 {
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 E0 0C 00 73 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy0>
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
MDIO on GPIOs
|
||||
|
||||
Currently defined compatibles:
|
||||
- virtual,gpio-mdio
|
||||
|
||||
MDC and MDIO lines connected to GPIO controllers are listed in the
|
||||
gpios property as described in section VIII.1 in the following order:
|
||||
|
||||
MDC, MDIO.
|
||||
|
||||
Example:
|
||||
|
||||
mdio {
|
||||
compatible = "virtual,mdio-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&qe_pio_a 11
|
||||
&qe_pio_c 6>;
|
||||
};
|
||||
@@ -0,0 +1,25 @@
|
||||
PHY nodes
|
||||
|
||||
Required properties:
|
||||
|
||||
- device_type : Should be "ethernet-phy"
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
field that represents an encoding of the sense and level
|
||||
information for the interrupt. This should be encoded based on
|
||||
the information in section 2) depending on the type of interrupt
|
||||
controller you have.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
- reg : The ID number for the phy, usually a small integer
|
||||
- linux,phandle : phandle for this node; likely referenced by an
|
||||
ethernet controller node.
|
||||
|
||||
Example:
|
||||
|
||||
ethernet-phy@0 {
|
||||
linux,phandle = <2452000>
|
||||
interrupt-parent = <40000>;
|
||||
interrupts = <35 1>;
|
||||
reg = <0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
@@ -0,0 +1,40 @@
|
||||
* Freescale 83xx and 512x PCI bridges
|
||||
|
||||
Freescale 83xx and 512x SOCs include the same pci bridge core.
|
||||
|
||||
83xx/512x specific notes:
|
||||
- reg: should contain two address length tuples
|
||||
The first is for the internal pci bridge registers
|
||||
The second is for the pci config space access registers
|
||||
|
||||
Example (MPC8313ERDB)
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0E -mini PCI */
|
||||
0x7000 0x0 0x0 0x1 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x2 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x3 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x4 &ipic 18 0x8
|
||||
|
||||
/* IDSEL 0x0F - PCI slot */
|
||||
0x7800 0x0 0x0 0x1 &ipic 17 0x8
|
||||
0x7800 0x0 0x0 0x2 &ipic 18 0x8
|
||||
0x7800 0x0 0x0 0x3 &ipic 17 0x8
|
||||
0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100 /* internal registers */
|
||||
0xe0008300 0x8>; /* config space access registers */
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
@@ -0,0 +1,52 @@
|
||||
PPC4xx Clock Power Management (CPM) node
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, currently only "ibm,cpm"
|
||||
- dcr-access-method : "native"
|
||||
- dcr-reg : < DCR register range >
|
||||
|
||||
Optional properties:
|
||||
- er-offset : All 4xx SoCs with a CPM controller have
|
||||
one of two different order for the CPM
|
||||
registers. Some have the CPM registers
|
||||
in the following order (ER,FR,SR). The
|
||||
others have them in the following order
|
||||
(SR,ER,FR). For the second case set
|
||||
er-offset = <1>.
|
||||
- unused-units : specifier consist of one cell. For each
|
||||
bit in the cell, the corresponding bit
|
||||
in CPM will be set to turn off unused
|
||||
devices.
|
||||
- idle-doze : specifier consist of one cell. For each
|
||||
bit in the cell, the corresponding bit
|
||||
in CPM will be set to turn off unused
|
||||
devices. This is usually just CPM[CPU].
|
||||
- standby : specifier consist of one cell. For each
|
||||
bit in the cell, the corresponding bit
|
||||
in CPM will be set on standby and
|
||||
restored on resume.
|
||||
- suspend : specifier consist of one cell. For each
|
||||
bit in the cell, the corresponding bit
|
||||
in CPM will be set on suspend (mem) and
|
||||
restored on resume. Note, for standby
|
||||
and suspend the corresponding bits can
|
||||
be different or the same. Usually for
|
||||
standby only class 2 and 3 units are set.
|
||||
However, the interface does not care.
|
||||
If they are the same, the additional
|
||||
power saving will be seeing if support
|
||||
is available to put the DDR in self
|
||||
refresh mode and any additional power
|
||||
saving techniques for the specific SoC.
|
||||
|
||||
Example:
|
||||
CPM0: cpm {
|
||||
compatible = "ibm,cpm";
|
||||
dcr-access-method = "native";
|
||||
dcr-reg = <0x160 0x003>;
|
||||
er-offset = <0>;
|
||||
unused-units = <0x00000100>;
|
||||
idle-doze = <0x02000000>;
|
||||
standby = <0xfeff0000>;
|
||||
suspend = <0xfeff791d>;
|
||||
};
|
||||
@@ -0,0 +1,148 @@
|
||||
4xx/Axon EMAC ethernet nodes
|
||||
|
||||
The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
|
||||
the Axon bridge. To operate this needs to interact with a ths
|
||||
special McMAL DMA controller, and sometimes an RGMII or ZMII
|
||||
interface. In addition to the nodes and properties described
|
||||
below, the node for the OPB bus on which the EMAC sits must have a
|
||||
correct clock-frequency property.
|
||||
|
||||
i) The EMAC node itself
|
||||
|
||||
Required properties:
|
||||
- device_type : "network"
|
||||
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
|
||||
405gp, Axon) and second is either "ibm,emac" or
|
||||
"ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
|
||||
"ibm,emac4"
|
||||
- interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
|
||||
- interrupt-parent : optional, if needed for interrupt mapping
|
||||
- reg : <registers mapping>
|
||||
- local-mac-address : 6 bytes, MAC address
|
||||
- mal-device : phandle of the associated McMAL node
|
||||
- mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
|
||||
with this EMAC
|
||||
- mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
|
||||
with this EMAC
|
||||
- cell-index : 1 cell, hardware index of the EMAC cell on a given
|
||||
ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
|
||||
each Axon chip)
|
||||
- max-frame-size : 1 cell, maximum frame size supported in bytes
|
||||
- rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
|
||||
operations.
|
||||
For Axon, 2048
|
||||
- tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
|
||||
operations.
|
||||
For Axon, 2048.
|
||||
- fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
|
||||
thresholds).
|
||||
For Axon, 0x00000010
|
||||
- mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
|
||||
in bytes.
|
||||
For Axon, 0x00000100 (I think ...)
|
||||
- phy-mode : string, mode of operations of the PHY interface.
|
||||
Supported values are: "mii", "rmii", "smii", "rgmii",
|
||||
"tbi", "gmii", rtbi", "sgmii".
|
||||
For Axon on CAB, it is "rgmii"
|
||||
- mdio-device : 1 cell, required iff using shared MDIO registers
|
||||
(440EP). phandle of the EMAC to use to drive the
|
||||
MDIO lines for the PHY used by this EMAC.
|
||||
- zmii-device : 1 cell, required iff connected to a ZMII. phandle of
|
||||
the ZMII device node
|
||||
- zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
|
||||
channel or 0xffffffff if ZMII is only used for MDIO.
|
||||
- rgmii-device : 1 cell, required iff connected to an RGMII. phandle
|
||||
of the RGMII device node.
|
||||
For Axon: phandle of plb5/plb4/opb/rgmii
|
||||
- rgmii-channel : 1 cell, required iff connected to an RGMII. Which
|
||||
RGMII channel is used by this EMAC.
|
||||
Fox Axon: present, whatever value is appropriate for each
|
||||
EMAC, that is the content of the current (bogus) "phy-port"
|
||||
property.
|
||||
|
||||
Optional properties:
|
||||
- phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
|
||||
a search is performed.
|
||||
- phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
|
||||
for, used if phy-address is absent. bit 0x00000001 is
|
||||
MDIO address 0.
|
||||
For Axon it can be absent, though my current driver
|
||||
doesn't handle phy-address yet so for now, keep
|
||||
0x00ffffff in it.
|
||||
- rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
|
||||
operations (if absent the value is the same as
|
||||
rx-fifo-size). For Axon, either absent or 2048.
|
||||
- tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
|
||||
operations (if absent the value is the same as
|
||||
tx-fifo-size). For Axon, either absent or 2048.
|
||||
- tah-device : 1 cell, optional. If connected to a TAH engine for
|
||||
offload, phandle of the TAH device node.
|
||||
- tah-channel : 1 cell, optional. If appropriate, channel used on the
|
||||
TAH engine.
|
||||
|
||||
Example:
|
||||
|
||||
EMAC0: ethernet@40000800 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1c 4 1d 4>;
|
||||
reg = <40000800 70>;
|
||||
local-mac-address = [00 04 AC E3 1B 1E];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0 1>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
};
|
||||
|
||||
ii) McMAL node
|
||||
|
||||
Required properties:
|
||||
- device_type : "dma-controller"
|
||||
- compatible : compatible list, containing 2 entries, first is
|
||||
"ibm,mcmal-CHIP" where CHIP is the host ASIC (like
|
||||
emac) and the second is either "ibm,mcmal" or
|
||||
"ibm,mcmal2".
|
||||
For Axon, "ibm,mcmal-axon","ibm,mcmal2"
|
||||
- interrupts : <interrupt mapping for the MAL interrupts sources:
|
||||
5 sources: tx_eob, rx_eob, serr, txde, rxde>.
|
||||
For Axon: This is _different_ from the current
|
||||
firmware. We use the "delayed" interrupts for txeob
|
||||
and rxeob. Thus we end up with mapping those 5 MPIC
|
||||
interrupts, all level positive sensitive: 10, 11, 32,
|
||||
33, 34 (in decimal)
|
||||
- dcr-reg : < DCR registers range >
|
||||
- dcr-parent : if needed for dcr-reg
|
||||
- num-tx-chans : 1 cell, number of Tx channels
|
||||
- num-rx-chans : 1 cell, number of Rx channels
|
||||
|
||||
iii) ZMII node
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, containing 2 entries, first is
|
||||
"ibm,zmii-CHIP" where CHIP is the host ASIC (like
|
||||
EMAC) and the second is "ibm,zmii".
|
||||
For Axon, there is no ZMII node.
|
||||
- reg : <registers mapping>
|
||||
|
||||
iv) RGMII node
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, containing 2 entries, first is
|
||||
"ibm,rgmii-CHIP" where CHIP is the host ASIC (like
|
||||
EMAC) and the second is "ibm,rgmii".
|
||||
For Axon, "ibm,rgmii-axon","ibm,rgmii"
|
||||
- reg : <registers mapping>
|
||||
- revision : as provided by the RGMII new version register if
|
||||
available.
|
||||
For Axon: 0x0000012a
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
AMCC NDFC (NanD Flash Controller)
|
||||
|
||||
Required properties:
|
||||
- compatible : "ibm,ndfc".
|
||||
- reg : should specify chip select and size used for the chip (0x2000).
|
||||
|
||||
Optional properties:
|
||||
- ccr : NDFC config and control register value (default 0).
|
||||
- bank-settings : NDFC bank configuration register value (default 0).
|
||||
|
||||
Notes:
|
||||
- partition(s) - follows the OF MTD standard for partitions
|
||||
|
||||
Example:
|
||||
|
||||
ndfc@1,0 {
|
||||
compatible = "ibm,ndfc";
|
||||
reg = <0x00000001 0x00000000 0x00002000>;
|
||||
ccr = <0x00001000>;
|
||||
bank-settings = <0x80002222>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x03E00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user