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arm64: Kernel booting and initialisation
The patch adds the kernel booting and the initial setup code. Documentation/arm64/booting.txt describes the booting protocol on the AArch64 Linux kernel. This is subject to change following the work on boot standardisation, ACPI. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Catalin Marinas
@@ -0,0 +1,152 @@
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Booting AArch64 Linux
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=====================
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Author: Will Deacon <will.deacon@arm.com>
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Date : 07 September 2012
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This document is based on the ARM booting document by Russell King and
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is relevant to all public releases of the AArch64 Linux kernel.
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The AArch64 exception model is made up of a number of exception levels
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(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
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counterpart. EL2 is the hypervisor level and exists only in non-secure
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mode. EL3 is the highest priority level and exists only in secure mode.
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For the purposes of this document, we will use the term `boot loader'
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simply to define all software that executes on the CPU(s) before control
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is passed to the Linux kernel. This may include secure monitor and
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hypervisor code, or it may just be a handful of instructions for
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preparing a minimal boot environment.
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Essentially, the boot loader should provide (as a minimum) the
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following:
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1. Setup and initialise the RAM
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2. Setup the device tree
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3. Decompress the kernel image
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4. Call the kernel image
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1. Setup and initialise RAM
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---------------------------
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Requirement: MANDATORY
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The boot loader is expected to find and initialise all RAM that the
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kernel will use for volatile data storage in the system. It performs
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this in a machine dependent manner. (It may use internal algorithms
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to automatically locate and size all RAM, or it may use knowledge of
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the RAM in the machine, or any other method the boot loader designer
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sees fit.)
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2. Setup the device tree
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-------------------------
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Requirement: MANDATORY
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The device tree blob (dtb) must be no bigger than 2 megabytes in size
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and placed at a 2-megabyte boundary within the first 512 megabytes from
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the start of the kernel image. This is to allow the kernel to map the
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blob using a single section mapping in the initial page tables.
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3. Decompress the kernel image
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------------------------------
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Requirement: OPTIONAL
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The AArch64 kernel does not currently provide a decompressor and
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therefore requires decompression (gzip etc.) to be performed by the boot
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loader if a compressed Image target (e.g. Image.gz) is used. For
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bootloaders that do not implement this requirement, the uncompressed
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Image target is available instead.
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4. Call the kernel image
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------------------------
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Requirement: MANDATORY
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The decompressed kernel image contains a 32-byte header as follows:
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u32 magic = 0x14000008; /* branch to stext, little-endian */
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u32 res0 = 0; /* reserved */
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u64 text_offset; /* Image load offset */
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u64 res1 = 0; /* reserved */
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u64 res2 = 0; /* reserved */
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The image must be placed at the specified offset (currently 0x80000)
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from the start of the system RAM and called there. The start of the
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system RAM must be aligned to 2MB.
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Before jumping into the kernel, the following conditions must be met:
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- Quiesce all DMA capable devices so that memory does not get
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corrupted by bogus network packets or disk data. This will save
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you many hours of debug.
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- Primary CPU general-purpose register settings
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x0 = physical address of device tree blob (dtb) in system RAM.
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x1 = 0 (reserved for future use)
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x2 = 0 (reserved for future use)
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x3 = 0 (reserved for future use)
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- CPU mode
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All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
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IRQ and FIQ).
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The CPU must be in either EL2 (RECOMMENDED in order to have access to
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the virtualisation extensions) or non-secure EL1.
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- Caches, MMUs
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The MMU must be off.
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Instruction cache may be on or off.
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Data cache must be off and invalidated.
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External caches (if present) must be configured and disabled.
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- Architected timers
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CNTFRQ must be programmed with the timer frequency.
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If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0)
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set where available.
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- Coherency
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All CPUs to be booted by the kernel must be part of the same coherency
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domain on entry to the kernel. This may require IMPLEMENTATION DEFINED
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initialisation to enable the receiving of maintenance operations on
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each CPU.
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- System registers
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All writable architected system registers at the exception level where
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the kernel image will be entered must be initialised by software at a
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higher exception level to prevent execution in an UNKNOWN state.
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The boot loader is expected to enter the kernel on each CPU in the
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following manner:
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- The primary CPU must jump directly to the first instruction of the
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kernel image. The device tree blob passed by this CPU must contain
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for each CPU node:
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1. An 'enable-method' property. Currently, the only supported value
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for this field is the string "spin-table".
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2. A 'cpu-release-addr' property identifying a 64-bit,
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zero-initialised memory location.
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It is expected that the bootloader will generate these device tree
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properties and insert them into the blob prior to kernel entry.
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- Any secondary CPUs must spin outside of the kernel in a reserved area
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of memory (communicated to the kernel by a /memreserve/ region in the
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device tree) polling their cpu-release-addr location, which must be
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contained in the reserved region. A wfe instruction may be inserted
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to reduce the overhead of the busy-loop and a sev will be issued by
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the primary CPU. When a read of the location pointed to by the
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cpu-release-addr returns a non-zero value, the CPU must jump directly
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to this value.
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- Secondary CPU general-purpose register settings
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x0 = 0 (reserved for future use)
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x1 = 0 (reserved for future use)
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x2 = 0 (reserved for future use)
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x3 = 0 (reserved for future use)
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@@ -0,0 +1,26 @@
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/*
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* Based on arch/arm/include/asm/setup.h
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*
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* Copyright (C) 1997-1999 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_SETUP_H
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#define __ASM_SETUP_H
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#include <linux/types.h>
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#define COMMAND_LINE_SIZE 2048
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#endif
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,347 @@
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/*
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* Based on arch/arm/kernel/setup.c
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*
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* Copyright (C) 1995-2001 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/utsname.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/bootmem.h>
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#include <linux/seq_file.h>
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#include <linux/screen_info.h>
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#include <linux/init.h>
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#include <linux/kexec.h>
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#include <linux/crash_dump.h>
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#include <linux/root_dev.h>
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/fs.h>
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#include <linux/proc_fs.h>
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#include <linux/memblock.h>
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#include <linux/of_fdt.h>
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#include <asm/cputype.h>
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#include <asm/elf.h>
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#include <asm/cputable.h>
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#include <asm/sections.h>
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#include <asm/setup.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/traps.h>
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#include <asm/memblock.h>
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unsigned int processor_id;
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EXPORT_SYMBOL(processor_id);
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unsigned int elf_hwcap __read_mostly;
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EXPORT_SYMBOL_GPL(elf_hwcap);
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static const char *cpu_name;
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static const char *machine_name;
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phys_addr_t __fdt_pointer __initdata;
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/*
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* Standard memory resources
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*/
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static struct resource mem_res[] = {
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{
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.name = "Kernel code",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_MEM
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},
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{
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.name = "Kernel data",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_MEM
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}
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};
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#define kernel_code mem_res[0]
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#define kernel_data mem_res[1]
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void __init early_print(const char *str, ...)
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{
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char buf[256];
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va_list ap;
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va_start(ap, str);
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vsnprintf(buf, sizeof(buf), str, ap);
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va_end(ap);
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printk("%s", buf);
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}
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static void __init setup_processor(void)
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{
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struct cpu_info *cpu_info;
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/*
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* locate processor in the list of supported processor
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* types. The linker builds this table for us from the
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* entries in arch/arm/mm/proc.S
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*/
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cpu_info = lookup_processor_type(read_cpuid_id());
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if (!cpu_info) {
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printk("CPU configuration botched (ID %08x), unable to continue.\n",
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read_cpuid_id());
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while (1);
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}
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cpu_name = cpu_info->cpu_name;
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printk("CPU: %s [%08x] revision %d\n",
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cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
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sprintf(init_utsname()->machine, "aarch64");
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elf_hwcap = 0;
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}
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static void __init setup_machine_fdt(phys_addr_t dt_phys)
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{
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struct boot_param_header *devtree;
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unsigned long dt_root;
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/* Check we have a non-NULL DT pointer */
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if (!dt_phys) {
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early_print("\n"
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"Error: NULL or invalid device tree blob\n"
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"The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
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"\nPlease check your bootloader.\n");
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while (true)
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cpu_relax();
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}
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devtree = phys_to_virt(dt_phys);
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/* Check device tree validity */
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if (be32_to_cpu(devtree->magic) != OF_DT_HEADER) {
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early_print("\n"
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"Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
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"Expected 0x%x, found 0x%x\n"
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"\nPlease check your bootloader.\n",
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dt_phys, devtree, OF_DT_HEADER,
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be32_to_cpu(devtree->magic));
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|
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while (true)
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cpu_relax();
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}
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initial_boot_params = devtree;
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dt_root = of_get_flat_dt_root();
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machine_name = of_get_flat_dt_prop(dt_root, "model", NULL);
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if (!machine_name)
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machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL);
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if (!machine_name)
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machine_name = "<unknown>";
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pr_info("Machine: %s\n", machine_name);
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/* Retrieve various information from the /chosen node */
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of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line);
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|
/* Initialize {size,address}-cells info */
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of_scan_flat_dt(early_init_dt_scan_root, NULL);
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/* Setup memory, calling early_init_dt_add_memory_arch */
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of_scan_flat_dt(early_init_dt_scan_memory, NULL);
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|
}
|
||||||
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|
||||||
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void __init early_init_dt_add_memory_arch(u64 base, u64 size)
|
||||||
|
{
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||||||
|
size &= PAGE_MASK;
|
||||||
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memblock_add(base, size);
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||||||
|
}
|
||||||
|
|
||||||
|
void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
|
||||||
|
{
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||||||
|
return __va(memblock_alloc(size, align));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Limit the memory size that was specified via FDT.
|
||||||
|
*/
|
||||||
|
static int __init early_mem(char *p)
|
||||||
|
{
|
||||||
|
phys_addr_t limit;
|
||||||
|
|
||||||
|
if (!p)
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
limit = memparse(p, &p) & PAGE_MASK;
|
||||||
|
pr_notice("Memory limited to %lldMB\n", limit >> 20);
|
||||||
|
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||||||
|
memblock_enforce_memory_limit(limit);
|
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|
|
||||||
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return 0;
|
||||||
|
}
|
||||||
|
early_param("mem", early_mem);
|
||||||
|
|
||||||
|
static void __init request_standard_resources(void)
|
||||||
|
{
|
||||||
|
struct memblock_region *region;
|
||||||
|
struct resource *res;
|
||||||
|
|
||||||
|
kernel_code.start = virt_to_phys(_text);
|
||||||
|
kernel_code.end = virt_to_phys(_etext - 1);
|
||||||
|
kernel_data.start = virt_to_phys(_sdata);
|
||||||
|
kernel_data.end = virt_to_phys(_end - 1);
|
||||||
|
|
||||||
|
for_each_memblock(memory, region) {
|
||||||
|
res = alloc_bootmem_low(sizeof(*res));
|
||||||
|
res->name = "System RAM";
|
||||||
|
res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
|
||||||
|
res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
|
||||||
|
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
||||||
|
|
||||||
|
request_resource(&iomem_resource, res);
|
||||||
|
|
||||||
|
if (kernel_code.start >= res->start &&
|
||||||
|
kernel_code.end <= res->end)
|
||||||
|
request_resource(res, &kernel_code);
|
||||||
|
if (kernel_data.start >= res->start &&
|
||||||
|
kernel_data.end <= res->end)
|
||||||
|
request_resource(res, &kernel_data);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void __init setup_arch(char **cmdline_p)
|
||||||
|
{
|
||||||
|
setup_processor();
|
||||||
|
|
||||||
|
setup_machine_fdt(__fdt_pointer);
|
||||||
|
|
||||||
|
init_mm.start_code = (unsigned long) _text;
|
||||||
|
init_mm.end_code = (unsigned long) _etext;
|
||||||
|
init_mm.end_data = (unsigned long) _edata;
|
||||||
|
init_mm.brk = (unsigned long) _end;
|
||||||
|
|
||||||
|
*cmdline_p = boot_command_line;
|
||||||
|
|
||||||
|
parse_early_param();
|
||||||
|
|
||||||
|
arm64_memblock_init();
|
||||||
|
|
||||||
|
paging_init();
|
||||||
|
request_standard_resources();
|
||||||
|
|
||||||
|
unflatten_device_tree();
|
||||||
|
|
||||||
|
#ifdef CONFIG_SMP
|
||||||
|
smp_init_cpus();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_VT
|
||||||
|
#if defined(CONFIG_VGA_CONSOLE)
|
||||||
|
conswitchp = &vga_con;
|
||||||
|
#elif defined(CONFIG_DUMMY_CONSOLE)
|
||||||
|
conswitchp = &dummy_con;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
static DEFINE_PER_CPU(struct cpu, cpu_data);
|
||||||
|
|
||||||
|
static int __init topology_init(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for_each_possible_cpu(i) {
|
||||||
|
struct cpu *cpu = &per_cpu(cpu_data, i);
|
||||||
|
cpu->hotpluggable = 1;
|
||||||
|
register_cpu(cpu, i);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
subsys_initcall(topology_init);
|
||||||
|
|
||||||
|
static const char *hwcap_str[] = {
|
||||||
|
"fp",
|
||||||
|
"asimd",
|
||||||
|
NULL
|
||||||
|
};
|
||||||
|
|
||||||
|
static int c_show(struct seq_file *m, void *v)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
seq_printf(m, "Processor\t: %s rev %d (%s)\n",
|
||||||
|
cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
|
||||||
|
|
||||||
|
for_each_online_cpu(i) {
|
||||||
|
/*
|
||||||
|
* glibc reads /proc/cpuinfo to determine the number of
|
||||||
|
* online processors, looking for lines beginning with
|
||||||
|
* "processor". Give glibc what it expects.
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_SMP
|
||||||
|
seq_printf(m, "processor\t: %d\n", i);
|
||||||
|
#endif
|
||||||
|
seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
|
||||||
|
loops_per_jiffy / (500000UL/HZ),
|
||||||
|
loops_per_jiffy / (5000UL/HZ) % 100);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* dump out the processor features */
|
||||||
|
seq_puts(m, "Features\t: ");
|
||||||
|
|
||||||
|
for (i = 0; hwcap_str[i]; i++)
|
||||||
|
if (elf_hwcap & (1 << i))
|
||||||
|
seq_printf(m, "%s ", hwcap_str[i]);
|
||||||
|
|
||||||
|
seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
|
||||||
|
seq_printf(m, "CPU architecture: AArch64\n");
|
||||||
|
seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
|
||||||
|
seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
|
||||||
|
seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
|
||||||
|
|
||||||
|
seq_puts(m, "\n");
|
||||||
|
|
||||||
|
seq_printf(m, "Hardware\t: %s\n", machine_name);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void *c_start(struct seq_file *m, loff_t *pos)
|
||||||
|
{
|
||||||
|
return *pos < 1 ? (void *)1 : NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
|
||||||
|
{
|
||||||
|
++*pos;
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void c_stop(struct seq_file *m, void *v)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
const struct seq_operations cpuinfo_op = {
|
||||||
|
.start = c_start,
|
||||||
|
.next = c_next,
|
||||||
|
.stop = c_stop,
|
||||||
|
.show = c_show
|
||||||
|
};
|
||||||
Reference in New Issue
Block a user