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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (47 commits) forcedeth: fix a few sparse warnings (variable shadowing) forcedeth: Improve stats counters forcedeth: remove unneeded stats updates forcedeth: Acknowledge only interrupts that are being processed forcedeth: fix race when unloading module MAINTAINERS/rds: update maintainer wanrouter: Remove kernel_lock annotations usbnet: fix oops in usbnet_start_xmit ixgbe: Fix compile for kernel without CONFIG_PCI_IOV defined etherh: Add MAINTAINERS entry for etherh bonding: comparing a u8 with -1 is always false sky2: fix regression on Yukon Optima netlink: clarify attribute length check documentation netlink: validate NLA_MSECS length i825xx:xscale:8390:freescale: Fix Kconfig dependancies macvlan: receive multicast with local address tg3: Update version to 3.121 tg3: Eliminate timer race with reset_task tg3: Schedule at most one tg3_reset_task run tg3: Obtain PCI function number from device ...
This commit is contained in:
+2
-1
@@ -1032,6 +1032,7 @@ F: arch/arm/include/asm/hardware/ioc.h
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F: arch/arm/include/asm/hardware/iomd.h
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F: arch/arm/include/asm/hardware/memc.h
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F: arch/arm/mach-rpc/
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F: drivers/net/ethernet/8390/etherh.c
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F: drivers/net/ethernet/i825xx/ether1*
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F: drivers/net/ethernet/seeq/ether3*
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F: drivers/scsi/arm/
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@@ -5470,7 +5471,7 @@ S: Maintained
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F: drivers/net/ethernet/rdc/r6040.c
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RDS - RELIABLE DATAGRAM SOCKETS
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M: Andy Grover <andy.grover@oracle.com>
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M: Venkat Venkatsubra <venkat.x.venkatsubra@oracle.com>
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L: rds-devel@oss.oracle.com (moderated for non-subscribers)
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S: Supported
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F: net/rds/
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@@ -105,7 +105,7 @@ static int ath3k_load_firmware(struct usb_device *udev,
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pipe = usb_sndctrlpipe(udev, 0);
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send_buf = kmalloc(BULK_SIZE, GFP_ATOMIC);
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send_buf = kmalloc(BULK_SIZE, GFP_KERNEL);
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if (!send_buf) {
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BT_ERR("Can't allocate memory chunk for firmware");
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return -ENOMEM;
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@@ -176,7 +176,7 @@ static int ath3k_load_fwfile(struct usb_device *udev,
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count = firmware->size;
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send_buf = kmalloc(BULK_SIZE, GFP_ATOMIC);
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send_buf = kmalloc(BULK_SIZE, GFP_KERNEL);
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if (!send_buf) {
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BT_ERR("Can't allocate memory chunk for firmware");
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return -ENOMEM;
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@@ -24,6 +24,7 @@
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#include <linux/module.h>
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#include <linux/atomic.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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@@ -65,6 +66,7 @@ struct bcm203x_data {
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unsigned long state;
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struct work_struct work;
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atomic_t shutdown;
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struct urb *urb;
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unsigned char *buffer;
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@@ -97,6 +99,7 @@ static void bcm203x_complete(struct urb *urb)
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data->state = BCM203X_SELECT_MEMORY;
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/* use workqueue to have a small delay */
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schedule_work(&data->work);
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break;
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@@ -155,7 +158,10 @@ static void bcm203x_work(struct work_struct *work)
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struct bcm203x_data *data =
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container_of(work, struct bcm203x_data, work);
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if (usb_submit_urb(data->urb, GFP_ATOMIC) < 0)
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if (atomic_read(&data->shutdown))
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return;
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if (usb_submit_urb(data->urb, GFP_KERNEL) < 0)
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BT_ERR("Can't submit URB");
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}
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@@ -243,6 +249,7 @@ static int bcm203x_probe(struct usb_interface *intf, const struct usb_device_id
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usb_set_intfdata(intf, data);
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/* use workqueue to have a small delay */
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schedule_work(&data->work);
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return 0;
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@@ -254,6 +261,9 @@ static void bcm203x_disconnect(struct usb_interface *intf)
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BT_DBG("intf %p", intf);
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atomic_inc(&data->shutdown);
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cancel_work_sync(&data->work);
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usb_kill_urb(data->urb);
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usb_set_intfdata(intf, NULL);
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@@ -568,22 +568,23 @@ static int bfusb_load_firmware(struct bfusb_data *data,
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BT_INFO("BlueFRITZ! USB loading firmware");
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buf = kmalloc(BFUSB_MAX_BLOCK_SIZE + 3, GFP_KERNEL);
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if (!buf) {
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BT_ERR("Can't allocate memory chunk for firmware");
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return -ENOMEM;
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}
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pipe = usb_sndctrlpipe(data->udev, 0);
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if (usb_control_msg(data->udev, pipe, USB_REQ_SET_CONFIGURATION,
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0, 1, 0, NULL, 0, USB_CTRL_SET_TIMEOUT) < 0) {
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BT_ERR("Can't change to loading configuration");
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kfree(buf);
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return -EBUSY;
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}
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data->udev->toggle[0] = data->udev->toggle[1] = 0;
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buf = kmalloc(BFUSB_MAX_BLOCK_SIZE + 3, GFP_ATOMIC);
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if (!buf) {
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BT_ERR("Can't allocate memory chunk for firmware");
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return -ENOMEM;
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}
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pipe = usb_sndbulkpipe(data->udev, data->bulk_out_ep);
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while (count) {
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@@ -560,8 +560,8 @@ static int bond_update_speed_duplex(struct slave *slave)
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u32 slave_speed;
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int res;
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slave->speed = -1;
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slave->duplex = -1;
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slave->speed = SPEED_UNKNOWN;
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slave->duplex = DUPLEX_UNKNOWN;
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res = __ethtool_get_settings(slave_dev, &ecmd);
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if (res < 0)
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@@ -158,12 +158,12 @@ static void bond_info_show_slave(struct seq_file *seq,
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seq_printf(seq, "\nSlave Interface: %s\n", slave->dev->name);
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seq_printf(seq, "MII Status: %s\n",
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(slave->link == BOND_LINK_UP) ? "up" : "down");
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if (slave->speed == -1)
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if (slave->speed == SPEED_UNKNOWN)
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seq_printf(seq, "Speed: %s\n", "Unknown");
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else
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seq_printf(seq, "Speed: %d Mbps\n", slave->speed);
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if (slave->duplex == -1)
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if (slave->duplex == DUPLEX_UNKNOWN)
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seq_printf(seq, "Duplex: %s\n", "Unknown");
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else
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seq_printf(seq, "Duplex: %s\n", slave->duplex ? "full" : "half");
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@@ -89,10 +89,10 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
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#define DRV_MODULE_NAME "tg3"
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#define TG3_MAJ_NUM 3
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#define TG3_MIN_NUM 120
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#define TG3_MIN_NUM 121
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#define DRV_MODULE_VERSION \
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__stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
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#define DRV_MODULE_RELDATE "August 18, 2011"
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#define DRV_MODULE_RELDATE "November 2, 2011"
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#define RESET_KIND_SHUTDOWN 0
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#define RESET_KIND_INIT 1
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@@ -628,19 +628,23 @@ static void tg3_ape_lock_init(struct tg3 *tp)
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regbase = TG3_APE_PER_LOCK_GRANT;
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/* Make sure the driver hasn't any stale locks. */
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for (i = 0; i < 8; i++) {
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if (i == TG3_APE_LOCK_GPIO)
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continue;
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tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
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for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
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switch (i) {
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case TG3_APE_LOCK_PHY0:
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case TG3_APE_LOCK_PHY1:
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case TG3_APE_LOCK_PHY2:
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case TG3_APE_LOCK_PHY3:
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bit = APE_LOCK_GRANT_DRIVER;
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break;
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default:
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if (!tp->pci_fn)
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bit = APE_LOCK_GRANT_DRIVER;
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else
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bit = 1 << tp->pci_fn;
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}
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tg3_ape_write32(tp, regbase + 4 * i, bit);
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}
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/* Clear the correct bit of the GPIO lock too. */
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if (!tp->pci_fn)
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bit = APE_LOCK_GRANT_DRIVER;
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else
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bit = 1 << tp->pci_fn;
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tg3_ape_write32(tp, regbase + 4 * TG3_APE_LOCK_GPIO, bit);
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}
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static int tg3_ape_lock(struct tg3 *tp, int locknum)
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@@ -658,6 +662,10 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
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return 0;
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case TG3_APE_LOCK_GRC:
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case TG3_APE_LOCK_MEM:
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if (!tp->pci_fn)
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bit = APE_LOCK_REQ_DRIVER;
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else
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bit = 1 << tp->pci_fn;
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break;
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default:
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return -EINVAL;
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@@ -673,11 +681,6 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
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off = 4 * locknum;
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if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn)
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bit = APE_LOCK_REQ_DRIVER;
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else
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bit = 1 << tp->pci_fn;
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tg3_ape_write32(tp, req + off, bit);
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/* Wait for up to 1 millisecond to acquire lock. */
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@@ -710,6 +713,10 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
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return;
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case TG3_APE_LOCK_GRC:
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case TG3_APE_LOCK_MEM:
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if (!tp->pci_fn)
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bit = APE_LOCK_GRANT_DRIVER;
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else
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bit = 1 << tp->pci_fn;
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break;
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default:
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return;
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@@ -720,11 +727,6 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
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else
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gnt = TG3_APE_PER_LOCK_GRANT;
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if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn)
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bit = APE_LOCK_GRANT_DRIVER;
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else
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bit = 1 << tp->pci_fn;
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tg3_ape_write32(tp, gnt + 4 * locknum, bit);
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}
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@@ -5927,6 +5929,18 @@ static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
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return work_done;
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}
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static inline void tg3_reset_task_schedule(struct tg3 *tp)
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{
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if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
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schedule_work(&tp->reset_task);
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}
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static inline void tg3_reset_task_cancel(struct tg3 *tp)
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{
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cancel_work_sync(&tp->reset_task);
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tg3_flag_clear(tp, RESET_TASK_PENDING);
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}
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static int tg3_poll_msix(struct napi_struct *napi, int budget)
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{
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struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
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@@ -5967,7 +5981,7 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
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tx_recovery:
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/* work_done is guaranteed to be less than budget. */
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napi_complete(napi);
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schedule_work(&tp->reset_task);
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tg3_reset_task_schedule(tp);
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return work_done;
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}
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@@ -6002,7 +6016,7 @@ static void tg3_process_error(struct tg3 *tp)
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tg3_dump_state(tp);
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tg3_flag_set(tp, ERROR_PROCESSED);
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||||
schedule_work(&tp->reset_task);
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||||
tg3_reset_task_schedule(tp);
|
||||
}
|
||||
|
||||
static int tg3_poll(struct napi_struct *napi, int budget)
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||||
@@ -6049,7 +6063,7 @@ static int tg3_poll(struct napi_struct *napi, int budget)
|
||||
tx_recovery:
|
||||
/* work_done is guaranteed to be less than budget. */
|
||||
napi_complete(napi);
|
||||
schedule_work(&tp->reset_task);
|
||||
tg3_reset_task_schedule(tp);
|
||||
return work_done;
|
||||
}
|
||||
|
||||
@@ -6338,11 +6352,11 @@ static void tg3_reset_task(struct work_struct *work)
|
||||
{
|
||||
struct tg3 *tp = container_of(work, struct tg3, reset_task);
|
||||
int err;
|
||||
unsigned int restart_timer;
|
||||
|
||||
tg3_full_lock(tp, 0);
|
||||
|
||||
if (!netif_running(tp->dev)) {
|
||||
tg3_flag_clear(tp, RESET_TASK_PENDING);
|
||||
tg3_full_unlock(tp);
|
||||
return;
|
||||
}
|
||||
@@ -6355,9 +6369,6 @@ static void tg3_reset_task(struct work_struct *work)
|
||||
|
||||
tg3_full_lock(tp, 1);
|
||||
|
||||
restart_timer = tg3_flag(tp, RESTART_TIMER);
|
||||
tg3_flag_clear(tp, RESTART_TIMER);
|
||||
|
||||
if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
|
||||
tp->write32_tx_mbox = tg3_write32_tx_mbox;
|
||||
tp->write32_rx_mbox = tg3_write_flush_reg32;
|
||||
@@ -6372,14 +6383,13 @@ static void tg3_reset_task(struct work_struct *work)
|
||||
|
||||
tg3_netif_start(tp);
|
||||
|
||||
if (restart_timer)
|
||||
mod_timer(&tp->timer, jiffies + 1);
|
||||
|
||||
out:
|
||||
tg3_full_unlock(tp);
|
||||
|
||||
if (!err)
|
||||
tg3_phy_start(tp);
|
||||
|
||||
tg3_flag_clear(tp, RESET_TASK_PENDING);
|
||||
}
|
||||
|
||||
static void tg3_tx_timeout(struct net_device *dev)
|
||||
@@ -6391,7 +6401,7 @@ static void tg3_tx_timeout(struct net_device *dev)
|
||||
tg3_dump_state(tp);
|
||||
}
|
||||
|
||||
schedule_work(&tp->reset_task);
|
||||
tg3_reset_task_schedule(tp);
|
||||
}
|
||||
|
||||
/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
|
||||
@@ -6442,31 +6452,26 @@ static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
|
||||
hwbug = 1;
|
||||
|
||||
if (tg3_flag(tp, 4K_FIFO_LIMIT)) {
|
||||
u32 prvidx = *entry;
|
||||
u32 tmp_flag = flags & ~TXD_FLAG_END;
|
||||
while (len > TG3_TX_BD_DMA_MAX) {
|
||||
while (len > TG3_TX_BD_DMA_MAX && *budget) {
|
||||
u32 frag_len = TG3_TX_BD_DMA_MAX;
|
||||
len -= TG3_TX_BD_DMA_MAX;
|
||||
|
||||
if (len) {
|
||||
tnapi->tx_buffers[*entry].fragmented = true;
|
||||
/* Avoid the 8byte DMA problem */
|
||||
if (len <= 8) {
|
||||
len += TG3_TX_BD_DMA_MAX / 2;
|
||||
frag_len = TG3_TX_BD_DMA_MAX / 2;
|
||||
}
|
||||
} else
|
||||
tmp_flag = flags;
|
||||
|
||||
if (*budget) {
|
||||
tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
|
||||
frag_len, tmp_flag, mss, vlan);
|
||||
(*budget)--;
|
||||
*entry = NEXT_TX(*entry);
|
||||
} else {
|
||||
hwbug = 1;
|
||||
break;
|
||||
/* Avoid the 8byte DMA problem */
|
||||
if (len <= 8) {
|
||||
len += TG3_TX_BD_DMA_MAX / 2;
|
||||
frag_len = TG3_TX_BD_DMA_MAX / 2;
|
||||
}
|
||||
|
||||
tnapi->tx_buffers[*entry].fragmented = true;
|
||||
|
||||
tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
|
||||
frag_len, tmp_flag, mss, vlan);
|
||||
*budget -= 1;
|
||||
prvidx = *entry;
|
||||
*entry = NEXT_TX(*entry);
|
||||
|
||||
map += frag_len;
|
||||
}
|
||||
|
||||
@@ -6474,10 +6479,11 @@ static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
|
||||
if (*budget) {
|
||||
tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
|
||||
len, flags, mss, vlan);
|
||||
(*budget)--;
|
||||
*budget -= 1;
|
||||
*entry = NEXT_TX(*entry);
|
||||
} else {
|
||||
hwbug = 1;
|
||||
tnapi->tx_buffers[prvidx].fragmented = false;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
@@ -6509,7 +6515,7 @@ static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
|
||||
txb = &tnapi->tx_buffers[entry];
|
||||
}
|
||||
|
||||
for (i = 0; i < last; i++) {
|
||||
for (i = 0; i <= last; i++) {
|
||||
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
|
||||
|
||||
entry = NEXT_TX(entry);
|
||||
@@ -6559,6 +6565,8 @@ static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
|
||||
dev_kfree_skb(new_skb);
|
||||
ret = -1;
|
||||
} else {
|
||||
u32 save_entry = *entry;
|
||||
|
||||
base_flags |= TXD_FLAG_END;
|
||||
|
||||
tnapi->tx_buffers[*entry].skb = new_skb;
|
||||
@@ -6568,7 +6576,7 @@ static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
|
||||
if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
|
||||
new_skb->len, base_flags,
|
||||
mss, vlan)) {
|
||||
tg3_tx_skb_unmap(tnapi, *entry, 0);
|
||||
tg3_tx_skb_unmap(tnapi, save_entry, -1);
|
||||
dev_kfree_skb(new_skb);
|
||||
ret = -1;
|
||||
}
|
||||
@@ -6758,11 +6766,10 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||
|
||||
if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
|
||||
((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
|
||||
mss, vlan))
|
||||
mss, vlan)) {
|
||||
would_hit_hwbug = 1;
|
||||
|
||||
/* Now loop through additional data fragments, and queue them. */
|
||||
if (skb_shinfo(skb)->nr_frags > 0) {
|
||||
} else if (skb_shinfo(skb)->nr_frags > 0) {
|
||||
u32 tmp_mss = mss;
|
||||
|
||||
if (!tg3_flag(tp, HW_TSO_1) &&
|
||||
@@ -6784,11 +6791,14 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||
if (dma_mapping_error(&tp->pdev->dev, mapping))
|
||||
goto dma_error;
|
||||
|
||||
if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
|
||||
if (!budget ||
|
||||
tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
|
||||
len, base_flags |
|
||||
((i == last) ? TXD_FLAG_END : 0),
|
||||
tmp_mss, vlan))
|
||||
tmp_mss, vlan)) {
|
||||
would_hit_hwbug = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -6828,7 +6838,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||
return NETDEV_TX_OK;
|
||||
|
||||
dma_error:
|
||||
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
|
||||
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
|
||||
tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
|
||||
drop:
|
||||
dev_kfree_skb(skb);
|
||||
@@ -7281,7 +7291,8 @@ static void tg3_free_rings(struct tg3 *tp)
|
||||
if (!skb)
|
||||
continue;
|
||||
|
||||
tg3_tx_skb_unmap(tnapi, i, skb_shinfo(skb)->nr_frags);
|
||||
tg3_tx_skb_unmap(tnapi, i,
|
||||
skb_shinfo(skb)->nr_frags - 1);
|
||||
|
||||
dev_kfree_skb_any(skb);
|
||||
}
|
||||
@@ -9200,7 +9211,7 @@ static void tg3_timer(unsigned long __opaque)
|
||||
{
|
||||
struct tg3 *tp = (struct tg3 *) __opaque;
|
||||
|
||||
if (tp->irq_sync)
|
||||
if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
|
||||
goto restart_timer;
|
||||
|
||||
spin_lock(&tp->lock);
|
||||
@@ -9223,10 +9234,9 @@ static void tg3_timer(unsigned long __opaque)
|
||||
}
|
||||
|
||||
if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
|
||||
tg3_flag_set(tp, RESTART_TIMER);
|
||||
spin_unlock(&tp->lock);
|
||||
schedule_work(&tp->reset_task);
|
||||
return;
|
||||
tg3_reset_task_schedule(tp);
|
||||
goto restart_timer;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -9674,15 +9684,14 @@ static int tg3_open(struct net_device *dev)
|
||||
struct tg3_napi *tnapi = &tp->napi[i];
|
||||
err = tg3_request_irq(tp, i);
|
||||
if (err) {
|
||||
for (i--; i >= 0; i--)
|
||||
for (i--; i >= 0; i--) {
|
||||
tnapi = &tp->napi[i];
|
||||
free_irq(tnapi->irq_vec, tnapi);
|
||||
break;
|
||||
}
|
||||
goto err_out2;
|
||||
}
|
||||
}
|
||||
|
||||
if (err)
|
||||
goto err_out2;
|
||||
|
||||
tg3_full_lock(tp, 0);
|
||||
|
||||
err = tg3_init_hw(tp, 1);
|
||||
@@ -9783,7 +9792,7 @@ static int tg3_close(struct net_device *dev)
|
||||
struct tg3 *tp = netdev_priv(dev);
|
||||
|
||||
tg3_napi_disable(tp);
|
||||
cancel_work_sync(&tp->reset_task);
|
||||
tg3_reset_task_cancel(tp);
|
||||
|
||||
netif_tx_stop_all_queues(dev);
|
||||
|
||||
@@ -11520,7 +11529,7 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
|
||||
break;
|
||||
}
|
||||
|
||||
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, 0);
|
||||
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
|
||||
dev_kfree_skb(skb);
|
||||
|
||||
if (tx_idx != tnapi->tx_prod)
|
||||
@@ -14228,12 +14237,30 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
|
||||
val = tr32(MEMARB_MODE);
|
||||
tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
|
||||
|
||||
if (tg3_flag(tp, PCIX_MODE)) {
|
||||
pci_read_config_dword(tp->pdev,
|
||||
tp->pcix_cap + PCI_X_STATUS, &val);
|
||||
tp->pci_fn = val & 0x7;
|
||||
} else {
|
||||
tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
|
||||
tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
|
||||
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
|
||||
tg3_flag(tp, 5780_CLASS)) {
|
||||
if (tg3_flag(tp, PCIX_MODE)) {
|
||||
pci_read_config_dword(tp->pdev,
|
||||
tp->pcix_cap + PCI_X_STATUS,
|
||||
&val);
|
||||
tp->pci_fn = val & 0x7;
|
||||
}
|
||||
} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
|
||||
tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
|
||||
if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
|
||||
NIC_SRAM_CPMUSTAT_SIG) {
|
||||
tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
|
||||
tp->pci_fn = tp->pci_fn ? 1 : 0;
|
||||
}
|
||||
} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
|
||||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
|
||||
tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
|
||||
if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
|
||||
NIC_SRAM_CPMUSTAT_SIG) {
|
||||
tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
|
||||
TG3_CPMU_STATUS_FSHFT_5719;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get eeprom hw config before calling tg3_set_power_state().
|
||||
@@ -15665,7 +15692,7 @@ static void __devexit tg3_remove_one(struct pci_dev *pdev)
|
||||
if (tp->fw)
|
||||
release_firmware(tp->fw);
|
||||
|
||||
cancel_work_sync(&tp->reset_task);
|
||||
tg3_reset_task_cancel(tp);
|
||||
|
||||
if (tg3_flag(tp, USE_PHYLIB)) {
|
||||
tg3_phy_fini(tp);
|
||||
@@ -15699,7 +15726,7 @@ static int tg3_suspend(struct device *device)
|
||||
if (!netif_running(dev))
|
||||
return 0;
|
||||
|
||||
flush_work_sync(&tp->reset_task);
|
||||
tg3_reset_task_cancel(tp);
|
||||
tg3_phy_stop(tp);
|
||||
tg3_netif_stop(tp);
|
||||
|
||||
@@ -15812,12 +15839,10 @@ static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
|
||||
tg3_netif_stop(tp);
|
||||
|
||||
del_timer_sync(&tp->timer);
|
||||
tg3_flag_clear(tp, RESTART_TIMER);
|
||||
|
||||
/* Want to make sure that the reset task doesn't run */
|
||||
cancel_work_sync(&tp->reset_task);
|
||||
tg3_reset_task_cancel(tp);
|
||||
tg3_flag_clear(tp, TX_RECOVERY_PENDING);
|
||||
tg3_flag_clear(tp, RESTART_TIMER);
|
||||
|
||||
netif_device_detach(netdev);
|
||||
|
||||
|
||||
@@ -1095,6 +1095,11 @@
|
||||
#define TG3_CPMU_CLCK_ORIDE 0x00003624
|
||||
#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
|
||||
|
||||
#define TG3_CPMU_STATUS 0x0000362c
|
||||
#define TG3_CPMU_STATUS_FMSK_5717 0x20000000
|
||||
#define TG3_CPMU_STATUS_FMSK_5719 0xc0000000
|
||||
#define TG3_CPMU_STATUS_FSHFT_5719 30
|
||||
|
||||
#define TG3_CPMU_CLCK_STAT 0x00003630
|
||||
#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
|
||||
#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
|
||||
@@ -2128,6 +2133,10 @@
|
||||
#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
|
||||
#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
|
||||
|
||||
#define NIC_SRAM_CPMU_STATUS 0x00000e00
|
||||
#define NIC_SRAM_CPMUSTAT_SIG 0x0000362c
|
||||
#define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff
|
||||
|
||||
#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
|
||||
|
||||
#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
|
||||
@@ -2344,9 +2353,13 @@
|
||||
#define APE_PER_LOCK_GRANT_DRIVER 0x00001000
|
||||
|
||||
/* APE convenience enumerations. */
|
||||
#define TG3_APE_LOCK_GRC 1
|
||||
#define TG3_APE_LOCK_MEM 4
|
||||
#define TG3_APE_LOCK_GPIO 7
|
||||
#define TG3_APE_LOCK_PHY0 0
|
||||
#define TG3_APE_LOCK_GRC 1
|
||||
#define TG3_APE_LOCK_PHY1 2
|
||||
#define TG3_APE_LOCK_PHY2 3
|
||||
#define TG3_APE_LOCK_MEM 4
|
||||
#define TG3_APE_LOCK_PHY3 5
|
||||
#define TG3_APE_LOCK_GPIO 7
|
||||
|
||||
#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
|
||||
|
||||
@@ -2866,7 +2879,6 @@ enum TG3_FLAGS {
|
||||
TG3_FLAG_JUMBO_CAPABLE,
|
||||
TG3_FLAG_CHIP_RESETTING,
|
||||
TG3_FLAG_INIT_COMPLETE,
|
||||
TG3_FLAG_RESTART_TIMER,
|
||||
TG3_FLAG_TSO_BUG,
|
||||
TG3_FLAG_IS_5788,
|
||||
TG3_FLAG_MAX_RXPEND_64,
|
||||
@@ -2909,6 +2921,7 @@ enum TG3_FLAGS {
|
||||
TG3_FLAG_APE_HAS_NCSI,
|
||||
TG3_FLAG_5717_PLUS,
|
||||
TG3_FLAG_4K_FIFO_LIMIT,
|
||||
TG3_FLAG_RESET_TASK_PENDING,
|
||||
|
||||
/* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
|
||||
TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
|
||||
|
||||
@@ -7,8 +7,7 @@ config NET_VENDOR_FREESCALE
|
||||
default y
|
||||
depends on FSL_SOC || QUICC_ENGINE || CPM1 || CPM2 || PPC_MPC512x || \
|
||||
M523x || M527x || M5272 || M528x || M520x || M532x || \
|
||||
ARCH_MXC || ARCH_MXS || \
|
||||
(PPC_MPC52xx && PPC_BESTCOMM)
|
||||
ARCH_MXC || ARCH_MXS || (PPC_MPC52xx && PPC_BESTCOMM)
|
||||
---help---
|
||||
If you have a network (Ethernet) card belonging to this class, say Y
|
||||
and read the Ethernet-HOWTO, available from
|
||||
|
||||
@@ -5,7 +5,11 @@
|
||||
config NET_VENDOR_INTEL
|
||||
bool "Intel devices"
|
||||
default y
|
||||
depends on PCI || PCI_MSI
|
||||
depends on PCI || PCI_MSI || ISA || ISA_DMA_API || ARM || \
|
||||
ARCH_ACORN || MCA || MCA_LEGACY || SNI_RM || SUN3 || \
|
||||
GSC || BVME6000 || MVME16x || ARCH_ENP2611 || \
|
||||
(ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR) || \
|
||||
EXPERIMENTAL
|
||||
---help---
|
||||
If you have a network (Ethernet) card belonging to this class, say Y
|
||||
and read the Ethernet-HOWTO, available from
|
||||
|
||||
@@ -442,12 +442,14 @@ static int ixgbe_set_vf_macvlan(struct ixgbe_adapter *adapter,
|
||||
|
||||
int ixgbe_check_vf_assignment(struct ixgbe_adapter *adapter)
|
||||
{
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
int i;
|
||||
for (i = 0; i < adapter->num_vfs; i++) {
|
||||
if (adapter->vfinfo[i].vfdev->dev_flags &
|
||||
PCI_DEV_FLAGS_ASSIGNED)
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
@@ -42,11 +42,11 @@ int ixgbe_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, bool setting);
|
||||
int ixgbe_ndo_get_vf_config(struct net_device *netdev,
|
||||
int vf, struct ifla_vf_info *ivi);
|
||||
void ixgbe_check_vf_rate_limit(struct ixgbe_adapter *adapter);
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
void ixgbe_disable_sriov(struct ixgbe_adapter *adapter);
|
||||
int ixgbe_check_vf_assignment(struct ixgbe_adapter *adapter);
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
void ixgbe_enable_sriov(struct ixgbe_adapter *adapter,
|
||||
const struct ixgbe_info *ii);
|
||||
int ixgbe_check_vf_assignment(struct ixgbe_adapter *adapter);
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
@@ -366,17 +366,6 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
|
||||
gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
|
||||
}
|
||||
} else {
|
||||
if (hw->chip_id >= CHIP_ID_YUKON_OPT) {
|
||||
u16 ctrl2 = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL_2);
|
||||
|
||||
/* enable PHY Reverse Auto-Negotiation */
|
||||
ctrl2 |= 1u << 13;
|
||||
|
||||
/* Write PHY changes (SW-reset must follow) */
|
||||
gm_phy_write(hw, port, PHY_MARV_EXT_CTRL_2, ctrl2);
|
||||
}
|
||||
|
||||
|
||||
/* disable energy detect */
|
||||
ctrl &= ~PHY_M_PC_EN_DET_MSK;
|
||||
|
||||
|
||||
@@ -5,7 +5,10 @@
|
||||
config NET_VENDOR_NATSEMI
|
||||
bool "National Semi-conductor devices"
|
||||
default y
|
||||
depends on MCA || MAC || MACH_JAZZ || PCI || XTENSA_PLATFORM_XT2000
|
||||
depends on AMIGA_PCMCIA || ARM || EISA || EXPERIMENTAL || H8300 || \
|
||||
ISA || M32R || MAC || MACH_JAZZ || MACH_TX49XX || MCA || \
|
||||
MCA_LEGACY || MIPS || PCI || PCMCIA || SUPERH || \
|
||||
XTENSA_PLATFORM_XT2000 || ZORRO
|
||||
---help---
|
||||
If you have a network (Ethernet) card belonging to this class, say Y
|
||||
and read the Ethernet-HOWTO, available from
|
||||
|
||||
@@ -1682,6 +1682,7 @@ static void nv_get_hw_stats(struct net_device *dev)
|
||||
np->estats.tx_pause += readl(base + NvRegTxPause);
|
||||
np->estats.rx_pause += readl(base + NvRegRxPause);
|
||||
np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
|
||||
np->estats.rx_errors_total += np->estats.rx_drop_frame;
|
||||
}
|
||||
|
||||
if (np->driver_data & DEV_HAS_STATISTICS_V3) {
|
||||
@@ -1706,11 +1707,14 @@ static struct net_device_stats *nv_get_stats(struct net_device *dev)
|
||||
nv_get_hw_stats(dev);
|
||||
|
||||
/* copy to net_device stats */
|
||||
dev->stats.tx_packets = np->estats.tx_packets;
|
||||
dev->stats.rx_bytes = np->estats.rx_bytes;
|
||||
dev->stats.tx_bytes = np->estats.tx_bytes;
|
||||
dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
|
||||
dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
|
||||
dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
|
||||
dev->stats.rx_over_errors = np->estats.rx_over_errors;
|
||||
dev->stats.rx_fifo_errors = np->estats.rx_drop_frame;
|
||||
dev->stats.rx_errors = np->estats.rx_errors_total;
|
||||
dev->stats.tx_errors = np->estats.tx_errors_total;
|
||||
}
|
||||
@@ -2099,10 +2103,10 @@ static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||
|
||||
/* add fragments to entries count */
|
||||
for (i = 0; i < fragments; i++) {
|
||||
u32 size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
|
||||
u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
|
||||
|
||||
entries += (size >> NV_TX2_TSO_MAX_SHIFT) +
|
||||
((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
|
||||
entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
|
||||
((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&np->lock, flags);
|
||||
@@ -2141,13 +2145,13 @@ static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||
/* setup the fragments */
|
||||
for (i = 0; i < fragments; i++) {
|
||||
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
|
||||
u32 size = skb_frag_size(frag);
|
||||
u32 frag_size = skb_frag_size(frag);
|
||||
offset = 0;
|
||||
|
||||
do {
|
||||
prev_tx = put_tx;
|
||||
prev_tx_ctx = np->put_tx_ctx;
|
||||
bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
|
||||
bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
|
||||
np->put_tx_ctx->dma = skb_frag_dma_map(
|
||||
&np->pci_dev->dev,
|
||||
frag, offset,
|
||||
@@ -2159,12 +2163,12 @@ static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||
put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
|
||||
|
||||
offset += bcnt;
|
||||
size -= bcnt;
|
||||
frag_size -= bcnt;
|
||||
if (unlikely(put_tx++ == np->last_tx.orig))
|
||||
put_tx = np->first_tx.orig;
|
||||
if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
|
||||
np->put_tx_ctx = np->first_tx_ctx;
|
||||
} while (size);
|
||||
} while (frag_size);
|
||||
}
|
||||
|
||||
/* set last fragment flag */
|
||||
@@ -2213,10 +2217,10 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
|
||||
|
||||
/* add fragments to entries count */
|
||||
for (i = 0; i < fragments; i++) {
|
||||
u32 size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
|
||||
u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
|
||||
|
||||
entries += (size >> NV_TX2_TSO_MAX_SHIFT) +
|
||||
((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
|
||||
entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
|
||||
((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&np->lock, flags);
|
||||
@@ -2257,13 +2261,13 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
|
||||
/* setup the fragments */
|
||||
for (i = 0; i < fragments; i++) {
|
||||
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
|
||||
u32 size = skb_frag_size(frag);
|
||||
u32 frag_size = skb_frag_size(frag);
|
||||
offset = 0;
|
||||
|
||||
do {
|
||||
prev_tx = put_tx;
|
||||
prev_tx_ctx = np->put_tx_ctx;
|
||||
bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
|
||||
bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
|
||||
np->put_tx_ctx->dma = skb_frag_dma_map(
|
||||
&np->pci_dev->dev,
|
||||
frag, offset,
|
||||
@@ -2276,12 +2280,12 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
|
||||
put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
|
||||
|
||||
offset += bcnt;
|
||||
size -= bcnt;
|
||||
frag_size -= bcnt;
|
||||
if (unlikely(put_tx++ == np->last_tx.ex))
|
||||
put_tx = np->first_tx.ex;
|
||||
if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
|
||||
np->put_tx_ctx = np->first_tx_ctx;
|
||||
} while (size);
|
||||
} while (frag_size);
|
||||
}
|
||||
|
||||
/* set last fragment flag */
|
||||
@@ -2374,16 +2378,8 @@ static int nv_tx_done(struct net_device *dev, int limit)
|
||||
if (np->desc_ver == DESC_VER_1) {
|
||||
if (flags & NV_TX_LASTPACKET) {
|
||||
if (flags & NV_TX_ERROR) {
|
||||
if (flags & NV_TX_UNDERFLOW)
|
||||
dev->stats.tx_fifo_errors++;
|
||||
if (flags & NV_TX_CARRIERLOST)
|
||||
dev->stats.tx_carrier_errors++;
|
||||
if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
|
||||
nv_legacybackoff_reseed(dev);
|
||||
dev->stats.tx_errors++;
|
||||
} else {
|
||||
dev->stats.tx_packets++;
|
||||
dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
|
||||
}
|
||||
dev_kfree_skb_any(np->get_tx_ctx->skb);
|
||||
np->get_tx_ctx->skb = NULL;
|
||||
@@ -2392,16 +2388,8 @@ static int nv_tx_done(struct net_device *dev, int limit)
|
||||
} else {
|
||||
if (flags & NV_TX2_LASTPACKET) {
|
||||
if (flags & NV_TX2_ERROR) {
|
||||
if (flags & NV_TX2_UNDERFLOW)
|
||||
dev->stats.tx_fifo_errors++;
|
||||
if (flags & NV_TX2_CARRIERLOST)
|
||||
dev->stats.tx_carrier_errors++;
|
||||
if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
|
||||
nv_legacybackoff_reseed(dev);
|
||||
dev->stats.tx_errors++;
|
||||
} else {
|
||||
dev->stats.tx_packets++;
|
||||
dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
|
||||
}
|
||||
dev_kfree_skb_any(np->get_tx_ctx->skb);
|
||||
np->get_tx_ctx->skb = NULL;
|
||||
@@ -2434,9 +2422,7 @@ static int nv_tx_done_optimized(struct net_device *dev, int limit)
|
||||
nv_unmap_txskb(np, np->get_tx_ctx);
|
||||
|
||||
if (flags & NV_TX2_LASTPACKET) {
|
||||
if (!(flags & NV_TX2_ERROR))
|
||||
dev->stats.tx_packets++;
|
||||
else {
|
||||
if (flags & NV_TX2_ERROR) {
|
||||
if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
|
||||
if (np->driver_data & DEV_HAS_GEAR_MODE)
|
||||
nv_gear_backoff_reseed(dev);
|
||||
@@ -2636,7 +2622,6 @@ static int nv_rx_process(struct net_device *dev, int limit)
|
||||
if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
|
||||
len = nv_getlen(dev, skb->data, len);
|
||||
if (len < 0) {
|
||||
dev->stats.rx_errors++;
|
||||
dev_kfree_skb(skb);
|
||||
goto next_pkt;
|
||||
}
|
||||
@@ -2650,11 +2635,6 @@ static int nv_rx_process(struct net_device *dev, int limit)
|
||||
else {
|
||||
if (flags & NV_RX_MISSEDFRAME)
|
||||
dev->stats.rx_missed_errors++;
|
||||
if (flags & NV_RX_CRCERR)
|
||||
dev->stats.rx_crc_errors++;
|
||||
if (flags & NV_RX_OVERFLOW)
|
||||
dev->stats.rx_over_errors++;
|
||||
dev->stats.rx_errors++;
|
||||
dev_kfree_skb(skb);
|
||||
goto next_pkt;
|
||||
}
|
||||
@@ -2670,7 +2650,6 @@ static int nv_rx_process(struct net_device *dev, int limit)
|
||||
if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
|
||||
len = nv_getlen(dev, skb->data, len);
|
||||
if (len < 0) {
|
||||
dev->stats.rx_errors++;
|
||||
dev_kfree_skb(skb);
|
||||
goto next_pkt;
|
||||
}
|
||||
@@ -2682,11 +2661,6 @@ static int nv_rx_process(struct net_device *dev, int limit)
|
||||
}
|
||||
/* the rest are hard errors */
|
||||
else {
|
||||
if (flags & NV_RX2_CRCERR)
|
||||
dev->stats.rx_crc_errors++;
|
||||
if (flags & NV_RX2_OVERFLOW)
|
||||
dev->stats.rx_over_errors++;
|
||||
dev->stats.rx_errors++;
|
||||
dev_kfree_skb(skb);
|
||||
goto next_pkt;
|
||||
}
|
||||
@@ -2704,7 +2678,6 @@ static int nv_rx_process(struct net_device *dev, int limit)
|
||||
skb->protocol = eth_type_trans(skb, dev);
|
||||
napi_gro_receive(&np->napi, skb);
|
||||
dev->stats.rx_packets++;
|
||||
dev->stats.rx_bytes += len;
|
||||
next_pkt:
|
||||
if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
|
||||
np->get_rx.orig = np->first_rx.orig;
|
||||
@@ -2787,9 +2760,7 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
|
||||
__vlan_hwaccel_put_tag(skb, vid);
|
||||
}
|
||||
napi_gro_receive(&np->napi, skb);
|
||||
|
||||
dev->stats.rx_packets++;
|
||||
dev->stats.rx_bytes += len;
|
||||
} else {
|
||||
dev_kfree_skb(skb);
|
||||
}
|
||||
@@ -2962,11 +2933,11 @@ static void nv_set_multicast(struct net_device *dev)
|
||||
struct netdev_hw_addr *ha;
|
||||
|
||||
netdev_for_each_mc_addr(ha, dev) {
|
||||
unsigned char *addr = ha->addr;
|
||||
unsigned char *hw_addr = ha->addr;
|
||||
u32 a, b;
|
||||
|
||||
a = le32_to_cpu(*(__le32 *) addr);
|
||||
b = le16_to_cpu(*(__le16 *) (&addr[4]));
|
||||
a = le32_to_cpu(*(__le32 *) hw_addr);
|
||||
b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
|
||||
alwaysOn[0] &= a;
|
||||
alwaysOff[0] &= ~a;
|
||||
alwaysOn[1] &= b;
|
||||
@@ -3398,7 +3369,8 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data)
|
||||
|
||||
for (i = 0;; i++) {
|
||||
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
|
||||
writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
|
||||
writel(events, base + NvRegMSIXIrqStatus);
|
||||
netdev_dbg(dev, "tx irq events: %08x\n", events);
|
||||
if (!(events & np->irqmask))
|
||||
break;
|
||||
|
||||
@@ -3509,7 +3481,8 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data)
|
||||
|
||||
for (i = 0;; i++) {
|
||||
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
|
||||
writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
|
||||
writel(events, base + NvRegMSIXIrqStatus);
|
||||
netdev_dbg(dev, "rx irq events: %08x\n", events);
|
||||
if (!(events & np->irqmask))
|
||||
break;
|
||||
|
||||
@@ -3553,7 +3526,8 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data)
|
||||
|
||||
for (i = 0;; i++) {
|
||||
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
|
||||
writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
|
||||
writel(events, base + NvRegMSIXIrqStatus);
|
||||
netdev_dbg(dev, "irq events: %08x\n", events);
|
||||
if (!(events & np->irqmask))
|
||||
break;
|
||||
|
||||
@@ -3617,10 +3591,10 @@ static irqreturn_t nv_nic_irq_test(int foo, void *data)
|
||||
|
||||
if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
|
||||
events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
|
||||
writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
|
||||
writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
|
||||
} else {
|
||||
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
|
||||
writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
|
||||
writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
|
||||
}
|
||||
pci_push(base);
|
||||
if (!(events & NVREG_IRQ_TIMER))
|
||||
@@ -4566,7 +4540,7 @@ static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *e
|
||||
struct fe_priv *np = netdev_priv(dev);
|
||||
|
||||
/* update stats */
|
||||
nv_do_stats_poll((unsigned long)dev);
|
||||
nv_get_hw_stats(dev);
|
||||
|
||||
memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
|
||||
}
|
||||
|
||||
@@ -192,6 +192,13 @@ static rx_handler_result_t macvlan_handle_frame(struct sk_buff **pskb)
|
||||
*/
|
||||
macvlan_broadcast(skb, port, src->dev,
|
||||
MACVLAN_MODE_VEPA);
|
||||
else {
|
||||
/* forward to original port. */
|
||||
vlan = src;
|
||||
ret = macvlan_broadcast_one(skb, vlan, eth, 0);
|
||||
goto out;
|
||||
}
|
||||
|
||||
return RX_HANDLER_PASS;
|
||||
}
|
||||
|
||||
|
||||
@@ -1057,7 +1057,8 @@ netdev_tx_t usbnet_start_xmit (struct sk_buff *skb,
|
||||
unsigned long flags;
|
||||
int retval;
|
||||
|
||||
skb_tx_timestamp(skb);
|
||||
if (skb)
|
||||
skb_tx_timestamp(skb);
|
||||
|
||||
// some devices want funky USB-level framing, for
|
||||
// win32 driver (usually) and/or hardware quirks
|
||||
|
||||
@@ -868,10 +868,6 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
|
||||
/* Do PA Calibration */
|
||||
ar9002_hw_pa_cal(ah, true);
|
||||
|
||||
/* Do NF Calibration after DC offset and other calibrations */
|
||||
ath9k_hw_loadnf(ah, chan);
|
||||
ath9k_hw_start_nfcal(ah, true);
|
||||
|
||||
if (ah->caldata)
|
||||
ah->caldata->nfcal_pending = true;
|
||||
|
||||
|
||||
@@ -908,12 +908,15 @@ static bool ar9003_hw_rtt_restore(struct ath_hw *ah, struct ath9k_channel *chan)
|
||||
int i;
|
||||
bool restore;
|
||||
|
||||
if (!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT) || !ah->caldata)
|
||||
if (!ah->caldata)
|
||||
return false;
|
||||
|
||||
hist = &ah->caldata->rtt_hist;
|
||||
if (!hist->num_readings)
|
||||
return false;
|
||||
|
||||
ar9003_hw_rtt_enable(ah);
|
||||
ar9003_hw_rtt_set_mask(ah, 0x10);
|
||||
ar9003_hw_rtt_set_mask(ah, 0x00);
|
||||
for (i = 0; i < AR9300_MAX_CHAINS; i++) {
|
||||
if (!(ah->rxchainmask & (1 << i)))
|
||||
continue;
|
||||
@@ -1070,6 +1073,7 @@ skip_tx_iqcal:
|
||||
if (is_reusable && (hist->num_readings < RTT_HIST_MAX)) {
|
||||
u32 *table;
|
||||
|
||||
hist->num_readings++;
|
||||
for (i = 0; i < AR9300_MAX_CHAINS; i++) {
|
||||
if (!(ah->rxchainmask & (1 << i)))
|
||||
continue;
|
||||
@@ -1081,9 +1085,6 @@ skip_tx_iqcal:
|
||||
ar9003_hw_rtt_disable(ah);
|
||||
}
|
||||
|
||||
ath9k_hw_loadnf(ah, chan);
|
||||
ath9k_hw_start_nfcal(ah, true);
|
||||
|
||||
/* Initialize list pointers */
|
||||
ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
|
||||
ah->supp_cals = IQ_MISMATCH_CAL;
|
||||
|
||||
@@ -572,14 +572,14 @@
|
||||
|
||||
#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
|
||||
|
||||
#define AR_PHY_TX_IQCAL_CONTROL_0 (AR_SM_BASE + AR_SREV_9485(ah) ? \
|
||||
0x3c4 : 0x444)
|
||||
#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + AR_SREV_9485(ah) ? \
|
||||
0x3c8 : 0x448)
|
||||
#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + AR_SREV_9485(ah) ? \
|
||||
0x3c4 : 0x440)
|
||||
#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + AR_SREV_9485(ah) ? \
|
||||
0x3f0 : 0x48c)
|
||||
#define AR_PHY_TX_IQCAL_CONTROL_0 (AR_SM_BASE + (AR_SREV_9485(ah) ? \
|
||||
0x3c4 : 0x444))
|
||||
#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + (AR_SREV_9485(ah) ? \
|
||||
0x3c8 : 0x448))
|
||||
#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + (AR_SREV_9485(ah) ? \
|
||||
0x3c4 : 0x440))
|
||||
#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + (AR_SREV_9485(ah) ? \
|
||||
0x3f0 : 0x48c))
|
||||
#define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \
|
||||
(AR_SREV_9485(ah) ? \
|
||||
0x3d0 : 0x450) + ((_i) << 2))
|
||||
@@ -651,7 +651,7 @@
|
||||
#define AR_SWITCH_TABLE_ALL_S (0)
|
||||
|
||||
#define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 :\
|
||||
(AR_SREV_9485(ah) ? 0x1628c : 0x16294))
|
||||
(AR_SREV_9462(ah) ? 0x16294 : 0x1628c))
|
||||
|
||||
#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
|
||||
#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
|
||||
@@ -668,12 +668,12 @@
|
||||
#define AR_PHY_65NM_CH2_RXTX2 0x16904
|
||||
|
||||
#define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : \
|
||||
(AR_SREV_9485(ah) ? 0x16284 : 0x16290))
|
||||
(AR_SREV_9462(ah) ? 0x16290 : 0x16284))
|
||||
#define AR_CH0_TOP2_XPABIASLVL 0xf000
|
||||
#define AR_CH0_TOP2_XPABIASLVL_S 12
|
||||
|
||||
#define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \
|
||||
(AR_SREV_9485(ah) ? 0x16290 : 0x16298))
|
||||
(AR_SREV_9462(ah) ? 0x16298 : 0x16290))
|
||||
#define AR_CH0_XTAL_CAPINDAC 0x7f000000
|
||||
#define AR_CH0_XTAL_CAPINDAC_S 24
|
||||
#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
|
||||
@@ -908,8 +908,8 @@
|
||||
#define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208)
|
||||
#define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c)
|
||||
#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
|
||||
#define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + (AR_SREV_AR9300(ah) ? \
|
||||
0x240 : 0x280))
|
||||
#define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + (AR_SREV_AR9462(ah) ? \
|
||||
0x280 : 0x240))
|
||||
#define AR_PHY_TPC_19_B1 (AR_SM1_BASE + 0x240)
|
||||
#define AR_PHY_TPC_19_B1_ALPHA_THERM 0xff
|
||||
#define AR_PHY_TPC_19_B1_ALPHA_THERM_S 0
|
||||
@@ -931,10 +931,10 @@
|
||||
#define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0)
|
||||
#define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4)
|
||||
|
||||
#define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + (i) ? \
|
||||
AR_SM1_BASE : AR_SM_BASE)
|
||||
#define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + (i) ? \
|
||||
AR_SM1_BASE : AR_SM_BASE)
|
||||
#define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + ((i) ? \
|
||||
AR_SM1_BASE : AR_SM_BASE))
|
||||
#define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + ((i) ? \
|
||||
AR_SM1_BASE : AR_SM_BASE))
|
||||
/*
|
||||
* Channel 2 Register Map
|
||||
*/
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user