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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Olof Johansson:
"We were expecting to sit on this branch through most of the merge
window since the contents was merged into our tree late, but we ended
up sitting on all of our contents so it can go in with the rest.
The contents here is:
- a large branch of cleanups of the CM/PRM blocks on OMAP.
- a couple of patches plumbing up CM/PRM on OMAP5 and DRA7.
- a branch with DT updates for Freescale i.MX. including some
shuffling from .dts to .dtsi (include) files that causes a little
churn"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (78 commits)
ARM: OMAP2+: Fix booting with configs that don't have MFD_SYSCON
ARM: OMAP4+: control: add support for initializing control module via DT
ARM: dts: dra7: add minimal l4 bus layout with control module support
ARM: dts: omap5: add minimal l4 bus layout with control module support
ARM: OMAP4+: control: remove support for legacy pad read/write
ARM: OMAP4: display: convert display to use syscon for dsi muxing
ARM: dts: omap4: add minimal l4 bus layout with control module support
ARM: dts: am4372: add minimal l4 bus layout with control module support
ARM: dts: am43xx-epos-evm: fix pinmux node layout
ARM: dts: am33xx: add minimal l4 bus layout with control module support
ARM: dts: omap3: add minimal l4 bus layout with control module support
ARM: dts: omap24xx: add minimal l4 bus layout with control module support
ARM: OMAP2+: control: add syscon support for register accesses
ARM: OMAP2+: id: cache omap_type value
ARM: OMAP2+: control: remove API for getting control module base address
ARM: OMAP2+: clock: add low-level support for regmap
ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init
ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags
ARM: OMAP2+: CM: move SoC specific init calls within a generic API
ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,79 @@
|
||||
OMAP Control Module bindings
|
||||
|
||||
Control Module contains miscellaneous features under it based on SoC type.
|
||||
Pincontrol is one common feature, and it has a specialized support
|
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described in [1]. Typically some clock nodes are also under control module.
|
||||
Syscon is used to share register level access to drivers external to
|
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control module driver itself.
|
||||
|
||||
See [2] for documentation about clock/clockdomain nodes.
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||||
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||||
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
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||||
[2] Documentation/devicetree/bindings/clock/ti/*
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|
||||
Required properties:
|
||||
- compatible: Must be one of:
|
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"ti,am3-scm"
|
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"ti,am4-scm"
|
||||
"ti,dm814-scrm"
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"ti,dm816-scrm"
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"ti,omap2-scm"
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"ti,omap3-scm"
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"ti,omap4-scm-core"
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"ti,omap4-scm-padconf-core"
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"ti,omap5-scm-core"
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"ti,omap5-scm-padconf-core"
|
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"ti,dra7-scm-core"
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- reg: Contains Control Module register address range
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(base address and length)
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Optional properties:
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- clocks: clocks for this module
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- clockdomains: clockdomains for this module
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||||
|
||||
Examples:
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|
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scm: scm@2000 {
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compatible = "ti,omap3-scm", "simple-bus";
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reg = <0x2000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2000 0x2000>;
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|
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omap3_pmx_core: pinmux@30 {
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compatible = "ti,omap3-padconf",
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"pinctrl-single";
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reg = <0x30 0x230>;
|
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#address-cells = <1>;
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#size-cells = <0>;
|
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#interrupt-cells = <1>;
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interrupt-controller;
|
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
|
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};
|
||||
|
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scm_conf: scm_conf@270 {
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compatible = "syscon";
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reg = <0x270 0x330>;
|
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#address-cells = <1>;
|
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#size-cells = <1>;
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|
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scm_clocks: clocks {
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
||||
};
|
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};
|
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|
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scm_clockdomains: clockdomains {
|
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};
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}
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|
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&scm_clocks {
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mcbsp5_mux_fck: mcbsp5_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&core_96m_fck>, <&mcbsp_clks>;
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ti,bit-shift = <4>;
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reg = <0x02d8>;
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};
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};
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@@ -0,0 +1,26 @@
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L4 interconnect bindings
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These bindings describe the OMAP SoCs L4 interconnect bus.
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Required properties:
|
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- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
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Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
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Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
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Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
|
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Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
|
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Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
|
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Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
|
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Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
|
||||
Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus
|
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Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
|
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Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
|
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- ranges : contains the IO map range for the bus
|
||||
|
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Examples:
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l4: l4@48000000 {
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compatible "ti,omap2-l4", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x48000000 0x100000>;
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};
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@@ -10,14 +10,10 @@ documentation about the individual clock/clockdomain nodes.
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Required properties:
|
||||
- compatible: Must be one of:
|
||||
"ti,am3-prcm"
|
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"ti,am3-scrm"
|
||||
"ti,am4-prcm"
|
||||
"ti,am4-scrm"
|
||||
"ti,omap2-prcm"
|
||||
"ti,omap2-scrm"
|
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"ti,omap3-prm"
|
||||
"ti,omap3-cm"
|
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"ti,omap3-scrm"
|
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"ti,omap4-cm1"
|
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"ti,omap4-prm"
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"ti,omap4-cm2"
|
||||
@@ -29,6 +25,8 @@ Required properties:
|
||||
"ti,dra7-prm"
|
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"ti,dra7-cm-core-aon"
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"ti,dra7-cm-core"
|
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"ti,dm814-prcm"
|
||||
"ti,dm816-prcm"
|
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- reg: Contains PRCM module register address range
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(base address and length)
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- clocks: clocks for this module
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@@ -307,9 +307,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
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imx6q-wandboard.dtb \
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imx6q-wandboard-revb1.dtb
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dtb-$(CONFIG_SOC_IMX6SL) += \
|
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imx6sl-evk.dtb
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imx6sl-evk.dtb \
|
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imx6sl-warp.dtb
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dtb-$(CONFIG_SOC_IMX6SX) += \
|
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imx6sx-sabreauto.dtb \
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imx6sx-sdb-reva.dtb \
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imx6sx-sdb.dtb
|
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dtb-$(CONFIG_SOC_LS1021A) += \
|
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ls1021a-qds.dtb \
|
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|
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@@ -7,7 +7,7 @@
|
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* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
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&scrm_clocks {
|
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&scm_clocks {
|
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sys_clkin_ck: sys_clkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
|
||||
@@ -83,20 +83,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
am33xx_control_module: control_module@4a002000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x44e10000 0x7fc>;
|
||||
};
|
||||
|
||||
am33xx_pinmux: pinmux@44e10800 {
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compatible = "pinctrl-single";
|
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reg = <0x44e10800 0x0238>;
|
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#address-cells = <1>;
|
||||
#size-cells = <0>;
|
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pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x7f>;
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the AM33XX interconnect.
|
||||
* The real AM33XX interconnect network is quite complex. Since
|
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@@ -111,35 +97,56 @@
|
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ranges;
|
||||
ti,hwmods = "l3_main";
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||||
|
||||
prcm: prcm@44e00000 {
|
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compatible = "ti,am3-prcm";
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reg = <0x44e00000 0x4000>;
|
||||
l4_wkup: l4_wkup@44c00000 {
|
||||
compatible = "ti,am3-l4-wkup", "simple-bus";
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#address-cells = <1>;
|
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#size-cells = <1>;
|
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ranges = <0 0x44c00000 0x280000>;
|
||||
|
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prcm_clocks: clocks {
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prcm: prcm@200000 {
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compatible = "ti,am3-prcm";
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reg = <0x200000 0x4000>;
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||||
|
||||
prcm_clocks: clocks {
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#address-cells = <1>;
|
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#size-cells = <0>;
|
||||
};
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
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scm: scm@210000 {
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compatible = "ti,am3-scm", "simple-bus";
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reg = <0x210000 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <1>;
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ranges = <0 0x210000 0x2000>;
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am33xx_pinmux: pinmux@800 {
|
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compatible = "pinctrl-single";
|
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reg = <0x800 0x238>;
|
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#address-cells = <1>;
|
||||
#size-cells = <0>;
|
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pinctrl-single,register-width = <32>;
|
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pinctrl-single,function-mask = <0x7f>;
|
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};
|
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|
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scm_conf: scm_conf@0 {
|
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compatible = "syscon";
|
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reg = <0x0 0x800>;
|
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#address-cells = <1>;
|
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#size-cells = <1>;
|
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|
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scm_clocks: clocks {
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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};
|
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};
|
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|
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scm_clockdomains: clockdomains {
|
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};
|
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};
|
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|
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prcm_clockdomains: clockdomains {
|
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};
|
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};
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scrm: scrm@44e10000 {
|
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compatible = "ti,am3-scrm";
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reg = <0x44e10000 0x2000>;
|
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|
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scrm_clocks: clocks {
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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};
|
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|
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scrm_clockdomains: clockdomains {
|
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};
|
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};
|
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|
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cm: syscon@44e10000 {
|
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compatible = "ti,am33xx-controlmodule", "syscon";
|
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reg = <0x44e10000 0x800>;
|
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};
|
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|
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intc: interrupt-controller@48200000 {
|
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@@ -350,7 +357,7 @@
|
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reg = <0x481cc000 0x2000>;
|
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clocks = <&dcan0_fck>;
|
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clock-names = "fck";
|
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syscon-raminit = <&am33xx_control_module 0x644 0>;
|
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syscon-raminit = <&scm_conf 0x644 0>;
|
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interrupts = <52>;
|
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status = "disabled";
|
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};
|
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@@ -361,7 +368,7 @@
|
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reg = <0x481d0000 0x2000>;
|
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clocks = <&dcan1_fck>;
|
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clock-names = "fck";
|
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syscon-raminit = <&am33xx_control_module 0x644 1>;
|
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syscon-raminit = <&scm_conf 0x644 1>;
|
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interrupts = <55>;
|
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status = "disabled";
|
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};
|
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@@ -720,7 +727,7 @@
|
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*/
|
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interrupts = <40 41 42 43>;
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ranges;
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syscon = <&cm>;
|
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syscon = <&scm_conf>;
|
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status = "disabled";
|
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|
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davinci_mdio: mdio@4a101000 {
|
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|
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@@ -31,7 +31,7 @@
|
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status = "disabled";
|
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reg = <0x5c000000 0x30000>;
|
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interrupts = <67 68 69 70>;
|
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syscon = <&omap3_scm_general>;
|
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syscon = <&scm_conf>;
|
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ti,davinci-ctrl-reg-offset = <0x10000>;
|
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ti,davinci-ctrl-mod-reg-offset = <0>;
|
||||
ti,davinci-ctrl-ram-offset = <0x20000>;
|
||||
|
||||
@@ -7,7 +7,7 @@
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&scrm_clocks {
|
||||
&scm_clocks {
|
||||
emac_ick: emac_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
|
||||
@@ -66,22 +66,6 @@
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
am43xx_control_module: control_module@4a002000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x44e10000 0x7f4>;
|
||||
};
|
||||
|
||||
am43xx_pinmux: pinmux@44e10800 {
|
||||
compatible = "ti,am437-padconf", "pinctrl-single";
|
||||
reg = <0x44e10800 0x31c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
ocp {
|
||||
compatible = "ti,am4372-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@@ -93,29 +77,58 @@
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
prcm: prcm@44df0000 {
|
||||
compatible = "ti,am4-prcm";
|
||||
reg = <0x44df0000 0x11000>;
|
||||
l4_wkup: l4_wkup@44c00000 {
|
||||
compatible = "ti,am4-l4-wkup", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x44c00000 0x287000>;
|
||||
|
||||
prcm_clocks: clocks {
|
||||
prcm: prcm@1f0000 {
|
||||
compatible = "ti,am4-prcm";
|
||||
reg = <0x1f0000 0x11000>;
|
||||
|
||||
prcm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scm: scm@210000 {
|
||||
compatible = "ti,am4-scm", "simple-bus";
|
||||
reg = <0x210000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x210000 0x4000>;
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
am43xx_pinmux: pinmux@800 {
|
||||
compatible = "ti,am437-padconf",
|
||||
"pinctrl-single";
|
||||
reg = <0x800 0x31c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
scrm: scrm@44e10000 {
|
||||
compatible = "ti,am4-scrm";
|
||||
reg = <0x44e10000 0x2000>;
|
||||
scm_conf: scm_conf@0 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0x800>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
scm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
scm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -942,7 +955,7 @@
|
||||
clocks = <&dcan0_fck>;
|
||||
clock-names = "fck";
|
||||
reg = <0x481cc000 0x2000>;
|
||||
syscon-raminit = <&am43xx_control_module 0x644 0>;
|
||||
syscon-raminit = <&scm_conf 0x644 0>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -953,7 +966,7 @@
|
||||
clocks = <&dcan1_fck>;
|
||||
clock-names = "fck";
|
||||
reg = <0x481d0000 0x2000>;
|
||||
syscon-raminit = <&am43xx_control_module 0x644 1>;
|
||||
syscon-raminit = <&scm_conf 0x644 1>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -69,7 +69,48 @@
|
||||
};
|
||||
};
|
||||
|
||||
am43xx_pinmux: pinmux@44e10800 {
|
||||
matrix_keypad: matrix_keypad@0 {
|
||||
compatible = "gpio-matrix-keypad";
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <2>;
|
||||
|
||||
row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
|
||||
&gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
|
||||
&gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
|
||||
&gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
|
||||
|
||||
col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
|
||||
&gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
|
||||
&gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
|
||||
&gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
|
||||
|
||||
linux,keymap = <0x00000201 /* P1 */
|
||||
0x01000204 /* P4 */
|
||||
0x02000207 /* P7 */
|
||||
0x0300020a /* NUMERIC_STAR */
|
||||
0x00010202 /* P2 */
|
||||
0x01010205 /* P5 */
|
||||
0x02010208 /* P8 */
|
||||
0x03010200 /* P0 */
|
||||
0x00020203 /* P3 */
|
||||
0x01020206 /* P6 */
|
||||
0x02020209 /* P9 */
|
||||
0x0302020b /* NUMERIC_POUND */
|
||||
0x00030067 /* UP */
|
||||
0x0103006a /* RIGHT */
|
||||
0x0203006c /* DOWN */
|
||||
0x03030069>; /* LEFT */
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
|
||||
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&am43xx_pinmux {
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
@@ -279,47 +320,6 @@
|
||||
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
matrix_keypad: matrix_keypad@0 {
|
||||
compatible = "gpio-matrix-keypad";
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <2>;
|
||||
|
||||
row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
|
||||
&gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
|
||||
&gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
|
||||
&gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
|
||||
|
||||
col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
|
||||
&gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
|
||||
&gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
|
||||
&gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
|
||||
|
||||
linux,keymap = <0x00000201 /* P1 */
|
||||
0x01000204 /* P4 */
|
||||
0x02000207 /* P7 */
|
||||
0x0300020a /* NUMERIC_STAR */
|
||||
0x00010202 /* P2 */
|
||||
0x01010205 /* P5 */
|
||||
0x02010208 /* P8 */
|
||||
0x03010200 /* P0 */
|
||||
0x00020203 /* P3 */
|
||||
0x01020206 /* P6 */
|
||||
0x02020209 /* P9 */
|
||||
0x0302020b /* NUMERIC_POUND */
|
||||
0x00030067 /* UP */
|
||||
0x0103006a /* RIGHT */
|
||||
0x0203006c /* DOWN */
|
||||
0x03030069>; /* LEFT */
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
|
||||
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
|
||||
@@ -7,7 +7,7 @@
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&scrm_clocks {
|
||||
&scm_clocks {
|
||||
sys_clkin_ck: sys_clkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
|
||||
+93
-63
@@ -102,17 +102,101 @@
|
||||
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
prm: prm@4ae06000 {
|
||||
compatible = "ti,dra7-prm";
|
||||
reg = <0x4ae06000 0x3000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
l4_cfg: l4@4a000000 {
|
||||
compatible = "ti,dra7-l4-cfg", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x4a000000 0x22c000>;
|
||||
|
||||
prm_clocks: clocks {
|
||||
scm: scm@2000 {
|
||||
compatible = "ti,dra7-scm-core", "simple-bus";
|
||||
reg = <0x2000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x2000 0x2000>;
|
||||
|
||||
scm_conf: scm_conf@0 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0x1400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pbias_regulator: pbias_regulator {
|
||||
compatible = "ti,pbias-omap";
|
||||
reg = <0xe00 0x4>;
|
||||
syscon = <&scm_conf>;
|
||||
pbias_mmc_reg: pbias_mmc_omap5 {
|
||||
regulator-name = "pbias_mmc_omap5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dra7_pmx_core: pinmux@1400 {
|
||||
compatible = "ti,dra7-padconf",
|
||||
"pinctrl-single";
|
||||
reg = <0x1400 0x0464>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x3fffffff>;
|
||||
};
|
||||
};
|
||||
|
||||
prm_clockdomains: clockdomains {
|
||||
cm_core_aon: cm_core_aon@5000 {
|
||||
compatible = "ti,dra7-cm-core-aon";
|
||||
reg = <0x5000 0x2000>;
|
||||
|
||||
cm_core_aon_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_core_aon_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm_core: cm_core@8000 {
|
||||
compatible = "ti,dra7-cm-core";
|
||||
reg = <0x8000 0x3000>;
|
||||
|
||||
cm_core_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_core_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
l4_wkup: l4@4ae00000 {
|
||||
compatible = "ti,dra7-l4-wkup", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x4ae00000 0x3f000>;
|
||||
|
||||
counter32k: counter@4000 {
|
||||
compatible = "ti,omap-counter32k";
|
||||
reg = <0x4000 0x40>;
|
||||
ti,hwmods = "counter_32k";
|
||||
};
|
||||
|
||||
prm: prm@6000 {
|
||||
compatible = "ti,dra7-prm";
|
||||
reg = <0x6000 0x3000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
prm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -197,38 +281,6 @@
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
cm_core_aon: cm_core_aon@4a005000 {
|
||||
compatible = "ti,dra7-cm-core-aon";
|
||||
reg = <0x4a005000 0x2000>;
|
||||
|
||||
cm_core_aon_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_core_aon_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm_core: cm_core@4a008000 {
|
||||
compatible = "ti,dra7-cm-core";
|
||||
reg = <0x4a008000 0x3000>;
|
||||
|
||||
cm_core_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_core_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
counter32k: counter@4ae04000 {
|
||||
compatible = "ti,omap-counter32k";
|
||||
reg = <0x4ae04000 0x40>;
|
||||
ti,hwmods = "counter_32k";
|
||||
};
|
||||
|
||||
dra7_ctrl_core: ctrl_core@4a002000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x4a002000 0x6d0>;
|
||||
@@ -239,28 +291,6 @@
|
||||
reg = <0x4a002e00 0x7c>;
|
||||
};
|
||||
|
||||
pbias_regulator: pbias_regulator {
|
||||
compatible = "ti,pbias-omap";
|
||||
reg = <0 0x4>;
|
||||
syscon = <&dra7_ctrl_general>;
|
||||
pbias_mmc_reg: pbias_mmc_omap5 {
|
||||
regulator-name = "pbias_mmc_omap5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dra7_pmx_core: pinmux@4a003400 {
|
||||
compatible = "ti,dra7-padconf", "pinctrl-single";
|
||||
reg = <0x4a003400 0x0464>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x3fffffff>;
|
||||
};
|
||||
|
||||
sdma: dma-controller@4a056000 {
|
||||
compatible = "ti,omap4430-sdma";
|
||||
reg = <0x4a056000 0x1000>;
|
||||
@@ -1424,7 +1454,7 @@
|
||||
compatible = "ti,dra7-d_can";
|
||||
ti,hwmods = "dcan1";
|
||||
reg = <0x4ae3c000 0x2000>;
|
||||
syscon-raminit = <&dra7_ctrl_core 0x558 0>;
|
||||
syscon-raminit = <&scm_conf 0x558 0>;
|
||||
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dcan1_sys_clk_mux>;
|
||||
status = "disabled";
|
||||
@@ -1434,7 +1464,7 @@
|
||||
compatible = "ti,dra7-d_can";
|
||||
ti,hwmods = "dcan2";
|
||||
reg = <0x48480000 0x2000>;
|
||||
syscon-raminit = <&dra7_ctrl_core 0x558 1>;
|
||||
syscon-raminit = <&scm_conf 0x558 1>;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sys_clkin1>;
|
||||
status = "disabled";
|
||||
|
||||
@@ -75,6 +75,27 @@
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <4>;
|
||||
};
|
||||
|
||||
wvga: display {
|
||||
model = "CLAA057VC01CW";
|
||||
bits-per-pixel = <16>;
|
||||
fsl,pcr = <0xfa208b80>;
|
||||
bus-width = <18>;
|
||||
native-mode = <&wvga_timings>;
|
||||
display-timings {
|
||||
wvga_timings: 640x480 {
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <45>;
|
||||
hfront-porch = <114>;
|
||||
hsync-len = <1>;
|
||||
vback-porch = <33>;
|
||||
vfront-porch = <11>;
|
||||
vsync-len = <1>;
|
||||
clock-frequency = <25200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
@@ -190,6 +211,33 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcd: lcdgrp {
|
||||
fsl,pins = <
|
||||
MX25_PAD_LD0__LD0 0xe0
|
||||
MX25_PAD_LD1__LD1 0xe0
|
||||
MX25_PAD_LD2__LD2 0xe0
|
||||
MX25_PAD_LD3__LD3 0xe0
|
||||
MX25_PAD_LD4__LD4 0xe0
|
||||
MX25_PAD_LD5__LD5 0xe0
|
||||
MX25_PAD_LD6__LD6 0xe0
|
||||
MX25_PAD_LD7__LD7 0xe0
|
||||
MX25_PAD_LD8__LD8 0xe0
|
||||
MX25_PAD_LD9__LD9 0xe0
|
||||
MX25_PAD_LD10__LD10 0xe0
|
||||
MX25_PAD_LD11__LD11 0xe0
|
||||
MX25_PAD_LD12__LD12 0xe0
|
||||
MX25_PAD_LD13__LD13 0xe0
|
||||
MX25_PAD_LD14__LD14 0xe0
|
||||
MX25_PAD_LD15__LD15 0xe0
|
||||
MX25_PAD_GPIO_E__LD16 0xe0
|
||||
MX25_PAD_GPIO_F__LD17 0xe0
|
||||
MX25_PAD_HSYNC__HSYNC 0xe0
|
||||
MX25_PAD_VSYNC__VSYNC 0xe0
|
||||
MX25_PAD_LSCLK__LSCLK 0xe0
|
||||
MX25_PAD_OE_ACD__OE_ACD 0xe0
|
||||
MX25_PAD_CONTRAST__CONTRAST 0xe0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
@@ -202,6 +250,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
display = <&wvga>;
|
||||
fsl,lpccr = <0x00a903ff>;
|
||||
fsl,lscr1 = <0x00120300>;
|
||||
fsl,dmacr = <0x00020010>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nfc {
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
@@ -17,48 +17,69 @@
|
||||
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||
*/
|
||||
|
||||
#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
|
||||
|
||||
#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
|
||||
#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
|
||||
|
||||
#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
|
||||
#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
|
||||
#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
|
||||
|
||||
#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000
|
||||
#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000
|
||||
#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x16 0x000
|
||||
#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000
|
||||
#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000
|
||||
#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x16 0x000
|
||||
#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000
|
||||
#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000
|
||||
#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x16 0x000
|
||||
#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000
|
||||
#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000
|
||||
#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x16 0x000
|
||||
#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000
|
||||
#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000
|
||||
#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x16 0x000
|
||||
#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000
|
||||
#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000
|
||||
#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000
|
||||
#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x16 0x000
|
||||
#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000
|
||||
#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000
|
||||
#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x16 0x000
|
||||
#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000
|
||||
#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000
|
||||
#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x16 0x000
|
||||
#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000
|
||||
#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000
|
||||
#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
|
||||
#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x16 0x000
|
||||
#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000
|
||||
#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000
|
||||
#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x16 0x000
|
||||
#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000
|
||||
#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000
|
||||
#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x16 0x000
|
||||
#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000
|
||||
|
||||
#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000
|
||||
@@ -133,20 +154,25 @@
|
||||
#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
|
||||
#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
|
||||
#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
|
||||
#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000
|
||||
|
||||
#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
|
||||
#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
|
||||
#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
|
||||
#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000
|
||||
|
||||
#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
|
||||
#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
|
||||
#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
|
||||
#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000
|
||||
|
||||
#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
|
||||
#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
|
||||
#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000
|
||||
|
||||
#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
|
||||
#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
|
||||
#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000
|
||||
|
||||
#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
|
||||
#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
|
||||
@@ -212,26 +238,33 @@
|
||||
|
||||
#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
|
||||
#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
|
||||
#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000
|
||||
|
||||
#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
|
||||
#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
|
||||
#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
|
||||
|
||||
#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
|
||||
#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001
|
||||
#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x15 0x001
|
||||
|
||||
#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
|
||||
#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
|
||||
#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
|
||||
|
||||
#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000
|
||||
#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
|
||||
#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001
|
||||
|
||||
#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000
|
||||
#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000
|
||||
#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000
|
||||
#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000
|
||||
#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000
|
||||
#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000
|
||||
#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001
|
||||
|
||||
#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000
|
||||
@@ -244,6 +277,7 @@
|
||||
#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000
|
||||
#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000
|
||||
#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
|
||||
@@ -257,26 +291,31 @@
|
||||
|
||||
#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
|
||||
#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000
|
||||
#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
|
||||
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
|
||||
|
||||
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
|
||||
#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000
|
||||
#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
|
||||
#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
|
||||
|
||||
#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
|
||||
#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000
|
||||
#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
|
||||
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
|
||||
|
||||
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001
|
||||
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x000
|
||||
#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000
|
||||
#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
|
||||
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
|
||||
|
||||
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
|
||||
#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
|
||||
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
|
||||
@@ -284,32 +323,32 @@
|
||||
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001
|
||||
#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x000
|
||||
#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
|
||||
#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
|
||||
|
||||
#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001
|
||||
#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x000
|
||||
#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
|
||||
#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
|
||||
|
||||
#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001
|
||||
#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x000
|
||||
#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
|
||||
#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001
|
||||
#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x000
|
||||
#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
|
||||
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001
|
||||
#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x000
|
||||
#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
|
||||
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
|
||||
#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001
|
||||
#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x000
|
||||
#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
|
||||
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
|
||||
|
||||
@@ -369,8 +408,8 @@
|
||||
#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
|
||||
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
|
||||
#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
|
||||
#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002
|
||||
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
|
||||
@@ -392,11 +431,11 @@
|
||||
#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000
|
||||
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002
|
||||
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x12 0x002
|
||||
#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000
|
||||
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002
|
||||
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x12 0x002
|
||||
#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
|
||||
@@ -410,7 +449,7 @@
|
||||
#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
|
||||
#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002
|
||||
#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x13 0x002
|
||||
#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
|
||||
@@ -455,9 +494,18 @@
|
||||
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000
|
||||
/*
|
||||
* According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
|
||||
* 01/2011) this is CAN1_TX but that's wrong.
|
||||
*/
|
||||
#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x14 0x000
|
||||
#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000
|
||||
/*
|
||||
* According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
|
||||
* 01/2011) this is CAN1_RX but that's wrong.
|
||||
*/
|
||||
#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000
|
||||
#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000
|
||||
|
||||
@@ -471,30 +519,34 @@
|
||||
#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000
|
||||
#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
|
||||
|
||||
#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000
|
||||
#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000
|
||||
#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000
|
||||
|
||||
#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000
|
||||
#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
|
||||
#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001
|
||||
#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
|
||||
|
||||
#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000
|
||||
#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x11 0x000
|
||||
#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x12 0x001
|
||||
#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x13 0x001
|
||||
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
|
||||
|
||||
#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
|
||||
#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x12 0x001
|
||||
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
|
||||
|
||||
#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
|
||||
#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
|
||||
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
|
||||
#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
|
||||
#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x16 0x002
|
||||
|
||||
#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
|
||||
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
|
||||
#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
|
||||
#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x16 0x000
|
||||
|
||||
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
|
||||
#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000
|
||||
@@ -505,6 +557,7 @@
|
||||
#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
|
||||
#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
|
||||
#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
|
||||
|
||||
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
|
||||
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
|
||||
|
||||
@@ -517,6 +570,7 @@
|
||||
|
||||
#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
|
||||
#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000
|
||||
|
||||
#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
|
||||
#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
|
||||
|
||||
|
||||
@@ -488,6 +488,7 @@
|
||||
interrupts = <54>;
|
||||
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -497,6 +498,7 @@
|
||||
interrupts = <55>;
|
||||
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@@ -78,7 +78,7 @@
|
||||
phy-mode = "rmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mac0_pins_a>;
|
||||
phy-reset-gpios = <&gpio4 13 0>;
|
||||
phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -110,6 +110,13 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
can0: can@80032000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can0_pins_a>;
|
||||
xceiver-supply = <®_can0_vcc>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
apbx@80040000 {
|
||||
@@ -130,6 +137,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
auart0: serial@8006a000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&auart0_pins_a>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@8007c000 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -143,7 +157,8 @@
|
||||
ahb@80080000 {
|
||||
usb0: usb@80080000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb0_otg_apf28dev>;
|
||||
pinctrl-0 = <&usb0_otg_apf28dev
|
||||
&usb0_id_pins_b>;
|
||||
vbus-supply = <®_usb0_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -156,7 +171,7 @@
|
||||
phy-mode = "rmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mac1_pins_a>;
|
||||
phy-reset-gpios = <&gpio0 23 0>;
|
||||
phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
@@ -175,6 +190,14 @@
|
||||
gpio = <&gpio1 23 1>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_can0_vcc: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "can0_vcc";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
@@ -200,8 +223,9 @@
|
||||
|
||||
user-button {
|
||||
label = "User button";
|
||||
gpios = <&gpio0 17 0>;
|
||||
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <0x100>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -829,6 +829,19 @@
|
||||
fsl,pull-up = <MXS_PULL_DISABLE>;
|
||||
};
|
||||
|
||||
spi3_pins_b: spi3@1 {
|
||||
reg = <1>;
|
||||
fsl,pinmux-ids = <
|
||||
MX28_PAD_SSP3_SCK__SSP3_SCK
|
||||
MX28_PAD_SSP3_MOSI__SSP3_CMD
|
||||
MX28_PAD_SSP3_MISO__SSP3_D0
|
||||
MX28_PAD_SSP3_SS0__SSP3_D3
|
||||
>;
|
||||
fsl,drive-strength = <MXS_DRIVE_8mA>;
|
||||
fsl,voltage = <MXS_VOLTAGE_HIGH>;
|
||||
fsl,pull-up = <MXS_PULL_ENABLE>;
|
||||
};
|
||||
|
||||
usb0_pins_a: usb0@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
@@ -1197,6 +1210,7 @@
|
||||
interrupts = <92>;
|
||||
clocks = <&clks 61>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@@ -318,6 +318,7 @@
|
||||
clocks = <&clks 73>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@@ -197,6 +197,7 @@
|
||||
reg = <0x53f80200 0x0200>;
|
||||
interrupts = <14>;
|
||||
clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -205,6 +206,7 @@
|
||||
reg = <0x53f80400 0x0200>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -213,6 +215,7 @@
|
||||
reg = <0x53f80600 0x0200>;
|
||||
interrupts = <17>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user