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[IA64] 4-level page tables

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This patch introduces 4-level page tables to ia64.  I have run
some benchmarks and found nothing interesting.  Performance has
consistently fallen within the noise range.

It also introduces a config option (setting the default to 3
levels).  The config option prevents having 4 level page
tables with 64k base page size.

Signed-off-by: Robin Holt <holt@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Robin Holt
2005-11-11 09:35:43 -06:00
committed by Tony Luck
parent d12eb7e11c
commit 837cd0bdf5
7 changed files with 153 additions and 36 deletions
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include/asm-ia64/pgalloc.h
+19
View File
@@ -86,6 +86,25 @@ static inline void pgd_free(pgd_t * pgd)
pgtable_quicklist_free(pgd);
}
#ifdef CONFIG_PGTABLE_4
static inline void
pgd_populate(struct mm_struct *mm, pgd_t * pgd_entry, pud_t * pud)
{
pgd_val(*pgd_entry) = __pa(pud);
}
static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
{
return pgtable_quicklist_alloc();
}
static inline void pud_free(pud_t * pud)
{
pgtable_quicklist_free(pud);
}
#define __pud_free_tlb(tlb, pud) pud_free(pud)
#endif /* CONFIG_PGTABLE_4 */
static inline void
pud_populate(struct mm_struct *mm, pud_t * pud_entry, pmd_t * pmd)
{