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sparc: Kill videopix SBUS driver.
This has been marked BROKEN for a long time and it's more likely to get rewritten from scratch than to be fixed up and made usable. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
@@ -30,15 +30,6 @@ config OBP_FLASH
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The OpenBoot PROM on Ultra systems is flashable. If you want to be
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able to upgrade the OBP firmware, say Y here.
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config SUN_VIDEOPIX
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tristate "Videopix Frame Grabber (EXPERIMENTAL)"
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depends on EXPERIMENTAL && (BROKEN || !64BIT)
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help
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Say Y here to support the Videopix Frame Grabber from Sun
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Microsystems, commonly found on SPARCstations. This card, which is
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based on the Phillips SAA9051, can handle NTSC and PAL/SECAM and
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SVIDEO signals.
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config TADPOLE_TS102_UCTRL
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tristate "Tadpole TS102 Microcontroller support (EXPERIMENTAL)"
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depends on EXPERIMENTAL && SPARC32
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@@ -7,7 +7,6 @@
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# Rewritten to use lists instead of if-statements.
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#
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vfc-objs := vfc_dev.o vfc_i2c.o
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bbc-objs := bbc_i2c.o bbc_envctrl.o
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obj-$(CONFIG_ENVCTRL) += envctrl.o
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@@ -17,7 +16,6 @@ obj-$(CONFIG_WATCHDOG_RIO) += riowatchdog.o
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obj-$(CONFIG_OBP_FLASH) += flash.o
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obj-$(CONFIG_SUN_OPENPROMIO) += openprom.o
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obj-$(CONFIG_SUN_MOSTEK_RTC) += rtc.o
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obj-$(CONFIG_SUN_VIDEOPIX) += vfc.o
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obj-$(CONFIG_TADPOLE_TS102_UCTRL) += uctrl.o
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obj-$(CONFIG_SUN_JSFLASH) += jsflash.o
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obj-$(CONFIG_BBC_I2C) += bbc.o
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@@ -1,171 +0,0 @@
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#ifndef _LINUX_VFC_H_
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#define _LINUX_VFC_H_
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/*
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* The control register for the vfc is at offset 0x4000
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* The first field ram bank is located at offset 0x5000
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* The second field ram bank is at offset 0x7000
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* i2c_reg address the Phillips PCF8584(see notes in vfc_i2c.c)
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* data and transmit register.
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* i2c_s1 controls register s1 of the PCF8584
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* i2c_write seems to be similar to i2c_write but I am not
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* quite sure why sun uses it
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*
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* I am also not sure whether or not you can read the fram bank as a
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* whole or whether you must read each word individually from offset
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* 0x5000 as soon as I figure it out I will update this file */
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struct vfc_regs {
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char pad1[0x4000];
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unsigned int control; /* Offset 0x4000 */
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char pad2[0xffb]; /* from offset 0x4004 to 0x5000 */
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unsigned int fram_bank1; /* Offset 0x5000 */
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char pad3[0xffb]; /* from offset 0x5004 to 0x6000 */
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unsigned int i2c_reg; /* Offset 0x6000 */
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unsigned int i2c_magic2; /* Offset 0x6004 */
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unsigned int i2c_s1; /* Offset 0x6008 */
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unsigned int i2c_write; /* Offset 0x600c */
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char pad4[0xff0]; /* from offset 0x6010 to 0x7000 */
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unsigned int fram_bank2; /* Offset 0x7000 */
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char pad5[0x1000];
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};
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#define VFC_SAA9051_NR (13)
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#define VFC_SAA9051_ADDR (0x8a)
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/* The saa9051 returns the following for its status
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* bit 0 - 0
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* bit 1 - SECAM color detected (1=found,0=not found)
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* bit 2 - COLOR detected (1=found,0=not found)
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* bit 3 - 0
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* bit 4 - Field frequency bit (1=60Hz (NTSC), 0=50Hz (PAL))
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* bit 5 - 1
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* bit 6 - horizontal frequency lock (1=transmitter found,
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* 0=no transmitter)
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* bit 7 - Power on reset bit (1=reset,0=at least one successful
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* read of the status byte)
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*/
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#define VFC_SAA9051_PONRES (0x80)
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#define VFC_SAA9051_HLOCK (0x40)
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#define VFC_SAA9051_FD (0x10)
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#define VFC_SAA9051_CD (0x04)
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#define VFC_SAA9051_CS (0x02)
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/* The various saa9051 sub addresses */
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#define VFC_SAA9051_IDEL (0)
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#define VFC_SAA9051_HSY_START (1)
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#define VFC_SAA9051_HSY_STOP (2)
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#define VFC_SAA9051_HC_START (3)
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#define VFC_SAA9051_HC_STOP (4)
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#define VFC_SAA9051_HS_START (5)
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#define VFC_SAA9051_HORIZ_PEAK (6)
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#define VFC_SAA9051_HUE (7)
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#define VFC_SAA9051_C1 (8)
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#define VFC_SAA9051_C2 (9)
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#define VFC_SAA9051_C3 (0xa)
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#define VFC_SAA9051_SECAM_DELAY (0xb)
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/* Bit settings for saa9051 sub address 0x06 */
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#define VFC_SAA9051_AP1 (0x01)
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#define VFC_SAA9051_AP2 (0x02)
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#define VFC_SAA9051_COR1 (0x04)
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#define VFC_SAA9051_COR2 (0x08)
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#define VFC_SAA9051_BP1 (0x10)
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#define VFC_SAA9051_BP2 (0x20)
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#define VFC_SAA9051_PF (0x40)
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#define VFC_SAA9051_BY (0x80)
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/* Bit settings for saa9051 sub address 0x08 */
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#define VFC_SAA9051_CCFR0 (0x01)
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#define VFC_SAA9051_CCFR1 (0x02)
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#define VFC_SAA9051_YPN (0x04)
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#define VFC_SAA9051_ALT (0x08)
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#define VFC_SAA9051_CO (0x10)
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#define VFC_SAA9051_VTR (0x20)
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#define VFC_SAA9051_FS (0x40)
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#define VFC_SAA9051_HPLL (0x80)
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/* Bit settings for saa9051 sub address 9 */
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#define VFC_SAA9051_SS0 (0x01)
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#define VFC_SAA9051_SS1 (0x02)
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#define VFC_SAA9051_AFCC (0x04)
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#define VFC_SAA9051_CI (0x08)
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#define VFC_SAA9051_SA9D4 (0x10) /* Don't care bit */
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#define VFC_SAA9051_OEC (0x20)
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#define VFC_SAA9051_OEY (0x40)
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#define VFC_SAA9051_VNL (0x80)
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/* Bit settings for saa9051 sub address 0x0A */
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#define VFC_SAA9051_YDL0 (0x01)
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#define VFC_SAA9051_YDL1 (0x02)
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#define VFC_SAA9051_YDL2 (0x04)
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#define VFC_SAA9051_SS2 (0x08)
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#define VFC_SAA9051_SS3 (0x10)
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#define VFC_SAA9051_YC (0x20)
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#define VFC_SAA9051_CT (0x40)
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#define VFC_SAA9051_SYC (0x80)
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#define VFC_SAA9051_SA(a,b) ((a)->saa9051_state_array[(b)+1])
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#define vfc_update_saa9051(a) (vfc_i2c_sendbuf((a),VFC_SAA9051_ADDR,\
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(a)->saa9051_state_array,\
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VFC_SAA9051_NR))
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struct vfc_dev {
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volatile struct vfc_regs __iomem *regs;
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struct vfc_regs *phys_regs;
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unsigned int control_reg;
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struct mutex device_lock_mtx;
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int instance;
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int busy;
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unsigned long which_io;
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unsigned char saa9051_state_array[VFC_SAA9051_NR];
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};
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void captstat_reset(struct vfc_dev *);
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void memptr_reset(struct vfc_dev *);
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int vfc_pcf8584_init(struct vfc_dev *);
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void vfc_i2c_delay_no_busy(struct vfc_dev *, unsigned long);
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void vfc_i2c_delay(struct vfc_dev *);
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int vfc_i2c_sendbuf(struct vfc_dev *, unsigned char, char *, int) ;
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int vfc_i2c_recvbuf(struct vfc_dev *, unsigned char, char *, int) ;
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int vfc_i2c_reset_bus(struct vfc_dev *);
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int vfc_init_i2c_bus(struct vfc_dev *);
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#define VFC_CONTROL_DIAGMODE 0x10000000
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#define VFC_CONTROL_MEMPTR 0x20000000
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#define VFC_CONTROL_CAPTURE 0x02000000
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#define VFC_CONTROL_CAPTRESET 0x04000000
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#define VFC_STATUS_CAPTURE 0x08000000
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#ifdef VFC_IOCTL_DEBUG
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#define VFC_IOCTL_DEBUG_PRINTK(a) printk a
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#else
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#define VFC_IOCTL_DEBUG_PRINTK(a)
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#endif
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#ifdef VFC_I2C_DEBUG
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#define VFC_I2C_DEBUG_PRINTK(a) printk a
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#else
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#define VFC_I2C_DEBUG_PRINTK(a)
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#endif
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#endif /* _LINUX_VFC_H_ */
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File diff suppressed because it is too large
Load Diff
@@ -1,335 +0,0 @@
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/*
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* drivers/sbus/char/vfc_i2c.c
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*
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* Driver for the Videopix Frame Grabber.
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*
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* Functions that support the Phillips i2c(I squared C) bus on the vfc
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* Documentation for the Phillips I2C bus can be found on the
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* phillips home page
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*
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* Copyright (C) 1996 Manish Vachharajani (mvachhar@noc.rutgers.edu)
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*
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*/
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/* NOTE: It seems to me that the documentation regarding the
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pcd8584t/pcf8584 does not show the correct way to address the i2c bus.
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Based on the information on the I2C bus itself and the remainder of
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the Phillips docs the following algorithms appear to be correct. I am
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fairly certain that the flowcharts in the phillips docs are wrong. */
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/wait.h>
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#include <linux/delay.h>
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#include <asm/openprom.h>
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#include <asm/oplib.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/sbus.h>
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#if 0
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#define VFC_I2C_DEBUG
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#endif
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#include "vfc.h"
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#include "vfc_i2c.h"
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#define WRITE_S1(__val) \
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sbus_writel(__val, &dev->regs->i2c_s1)
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#define WRITE_REG(__val) \
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sbus_writel(__val, &dev->regs->i2c_reg)
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#define VFC_I2C_READ (0x1)
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#define VFC_I2C_WRITE (0x0)
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/******
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The i2c bus controller chip on the VFC is a pcd8584t, but
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phillips claims it doesn't exist. As far as I can tell it is
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identical to the PCF8584 so I treat it like it is the pcf8584.
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NOTE: The pcf8584 only cares
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about the msb of the word you feed it
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*****/
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int vfc_pcf8584_init(struct vfc_dev *dev)
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{
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/* This will also choose register S0_OWN so we can set it. */
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WRITE_S1(RESET);
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/* The pcf8584 shifts this value left one bit and uses
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* it as its i2c bus address.
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*/
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WRITE_REG(0x55000000);
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/* This will set the i2c bus at the same speed sun uses,
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* and set another magic bit.
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*/
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WRITE_S1(SELECT(S2));
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WRITE_REG(0x14000000);
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/* Enable the serial port, idle the i2c bus and set
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* the data reg to s0.
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*/
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WRITE_S1(CLEAR_I2C_BUS);
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udelay(100);
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return 0;
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}
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void vfc_i2c_delay_no_busy(struct vfc_dev *dev, unsigned long usecs)
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{
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schedule_timeout_uninterruptible(usecs_to_jiffies(usecs));
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}
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void inline vfc_i2c_delay(struct vfc_dev *dev)
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{
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vfc_i2c_delay_no_busy(dev, 100);
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}
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int vfc_init_i2c_bus(struct vfc_dev *dev)
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{
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WRITE_S1(ENABLE_SERIAL | SELECT(S0) | ACK);
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vfc_i2c_reset_bus(dev);
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return 0;
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}
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int vfc_i2c_reset_bus(struct vfc_dev *dev)
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{
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VFC_I2C_DEBUG_PRINTK((KERN_DEBUG "vfc%d: Resetting the i2c bus\n",
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dev->instance));
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if(dev == NULL)
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return -EINVAL;
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if(dev->regs == NULL)
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return -EINVAL;
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WRITE_S1(SEND_I2C_STOP);
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WRITE_S1(SEND_I2C_STOP | ACK);
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vfc_i2c_delay(dev);
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WRITE_S1(CLEAR_I2C_BUS);
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VFC_I2C_DEBUG_PRINTK((KERN_DEBUG "vfc%d: I2C status %x\n",
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dev->instance,
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sbus_readl(&dev->regs->i2c_s1)));
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return 0;
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}
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static int vfc_i2c_wait_for_bus(struct vfc_dev *dev)
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{
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int timeout = 1000;
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while(!(sbus_readl(&dev->regs->i2c_s1) & BB)) {
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if(!(timeout--))
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return -ETIMEDOUT;
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vfc_i2c_delay(dev);
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}
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return 0;
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}
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static int vfc_i2c_wait_for_pin(struct vfc_dev *dev, int ack)
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{
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int timeout = 1000;
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int s1;
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while ((s1 = sbus_readl(&dev->regs->i2c_s1)) & PIN) {
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if (!(timeout--))
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return -ETIMEDOUT;
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vfc_i2c_delay(dev);
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}
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if (ack == VFC_I2C_ACK_CHECK) {
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if(s1 & LRB)
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return -EIO;
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}
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return 0;
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}
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#define SHIFT(a) ((a) << 24)
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static int vfc_i2c_xmit_addr(struct vfc_dev *dev, unsigned char addr,
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char mode)
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{
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int ret, raddr;
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#if 1
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WRITE_S1(SEND_I2C_STOP | ACK);
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WRITE_S1(SELECT(S0) | ENABLE_SERIAL);
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vfc_i2c_delay(dev);
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#endif
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switch(mode) {
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case VFC_I2C_READ:
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raddr = SHIFT(((unsigned int)addr | 0x1));
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WRITE_REG(raddr);
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VFC_I2C_DEBUG_PRINTK(("vfc%d: receiving from i2c addr 0x%x\n",
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dev->instance, addr | 0x1));
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break;
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case VFC_I2C_WRITE:
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raddr = SHIFT((unsigned int)addr & ~0x1);
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WRITE_REG(raddr);
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VFC_I2C_DEBUG_PRINTK(("vfc%d: sending to i2c addr 0x%x\n",
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dev->instance, addr & ~0x1));
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break;
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default:
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return -EINVAL;
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};
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WRITE_S1(SEND_I2C_START);
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vfc_i2c_delay(dev);
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ret = vfc_i2c_wait_for_pin(dev,VFC_I2C_ACK_CHECK); /* We wait
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for the
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i2c send
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to finish
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here but
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Sun
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doesn't,
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hmm */
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if (ret) {
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printk(KERN_ERR "vfc%d: VFC xmit addr timed out or no ack\n",
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dev->instance);
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return ret;
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} else if (mode == VFC_I2C_READ) {
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if ((ret = sbus_readl(&dev->regs->i2c_reg) & 0xff000000) != raddr) {
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printk(KERN_WARNING
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"vfc%d: returned slave address "
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"mismatch(%x,%x)\n",
|
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dev->instance, raddr, ret);
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}
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}
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return 0;
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}
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static int vfc_i2c_xmit_byte(struct vfc_dev *dev,unsigned char *byte)
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{
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int ret;
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u32 val = SHIFT((unsigned int)*byte);
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WRITE_REG(val);
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ret = vfc_i2c_wait_for_pin(dev, VFC_I2C_ACK_CHECK);
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switch(ret) {
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case -ETIMEDOUT:
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printk(KERN_ERR "vfc%d: VFC xmit byte timed out or no ack\n",
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dev->instance);
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break;
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case -EIO:
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ret = XMIT_LAST_BYTE;
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break;
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default:
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break;
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};
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return ret;
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}
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static int vfc_i2c_recv_byte(struct vfc_dev *dev, unsigned char *byte,
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int last)
|
||||
{
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int ret;
|
||||
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if (last) {
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WRITE_REG(NEGATIVE_ACK);
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VFC_I2C_DEBUG_PRINTK(("vfc%d: sending negative ack\n",
|
||||
dev->instance));
|
||||
} else {
|
||||
WRITE_S1(ACK);
|
||||
}
|
||||
|
||||
ret = vfc_i2c_wait_for_pin(dev, VFC_I2C_NO_ACK_CHECK);
|
||||
if(ret) {
|
||||
printk(KERN_ERR "vfc%d: "
|
||||
"VFC recv byte timed out\n",
|
||||
dev->instance);
|
||||
}
|
||||
*byte = (sbus_readl(&dev->regs->i2c_reg)) >> 24;
|
||||
return ret;
|
||||
}
|
||||
|
||||
int vfc_i2c_recvbuf(struct vfc_dev *dev, unsigned char addr,
|
||||
char *buf, int count)
|
||||
{
|
||||
int ret, last;
|
||||
|
||||
if(!(count && buf && dev && dev->regs) )
|
||||
return -EINVAL;
|
||||
|
||||
if ((ret = vfc_i2c_wait_for_bus(dev))) {
|
||||
printk(KERN_ERR "vfc%d: VFC I2C bus busy\n", dev->instance);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if ((ret = vfc_i2c_xmit_addr(dev, addr, VFC_I2C_READ))) {
|
||||
WRITE_S1(SEND_I2C_STOP);
|
||||
vfc_i2c_delay(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
last = 0;
|
||||
while (count--) {
|
||||
if (!count)
|
||||
last = 1;
|
||||
if ((ret = vfc_i2c_recv_byte(dev, buf, last))) {
|
||||
printk(KERN_ERR "vfc%d: "
|
||||
"VFC error while receiving byte\n",
|
||||
dev->instance);
|
||||
WRITE_S1(SEND_I2C_STOP);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
buf++;
|
||||
}
|
||||
WRITE_S1(SEND_I2C_STOP | ACK);
|
||||
vfc_i2c_delay(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int vfc_i2c_sendbuf(struct vfc_dev *dev, unsigned char addr,
|
||||
char *buf, int count)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!(buf && dev && dev->regs))
|
||||
return -EINVAL;
|
||||
|
||||
if ((ret = vfc_i2c_wait_for_bus(dev))) {
|
||||
printk(KERN_ERR "vfc%d: VFC I2C bus busy\n", dev->instance);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if ((ret = vfc_i2c_xmit_addr(dev, addr, VFC_I2C_WRITE))) {
|
||||
WRITE_S1(SEND_I2C_STOP);
|
||||
vfc_i2c_delay(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
while(count--) {
|
||||
ret = vfc_i2c_xmit_byte(dev, buf);
|
||||
switch(ret) {
|
||||
case XMIT_LAST_BYTE:
|
||||
VFC_I2C_DEBUG_PRINTK(("vfc%d: "
|
||||
"Receiver ended transmission with "
|
||||
" %d bytes remaining\n",
|
||||
dev->instance, count));
|
||||
ret = 0;
|
||||
goto done;
|
||||
break;
|
||||
case 0:
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "vfc%d: "
|
||||
"VFC error while sending byte\n", dev->instance);
|
||||
break;
|
||||
};
|
||||
|
||||
buf++;
|
||||
}
|
||||
done:
|
||||
WRITE_S1(SEND_I2C_STOP | ACK);
|
||||
vfc_i2c_delay(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,44 +0,0 @@
|
||||
#ifndef _LINUX_VFC_I2C_H_
|
||||
#define _LINUX_VFC_I2C_H_
|
||||
|
||||
/* control bits */
|
||||
#define PIN (0x80000000)
|
||||
#define ESO (0x40000000)
|
||||
#define ES1 (0x20000000)
|
||||
#define ES2 (0x10000000)
|
||||
#define ENI (0x08000000)
|
||||
#define STA (0x04000000)
|
||||
#define STO (0x02000000)
|
||||
#define ACK (0x01000000)
|
||||
|
||||
/* status bits */
|
||||
#define STS (0x20000000)
|
||||
#define BER (0x10000000)
|
||||
#define LRB (0x08000000)
|
||||
#define AAS (0x04000000)
|
||||
#define LAB (0x02000000)
|
||||
#define BB (0x01000000)
|
||||
|
||||
#define SEND_I2C_START (PIN | ESO | STA)
|
||||
#define SEND_I2C_STOP (PIN | ESO | STO)
|
||||
#define CLEAR_I2C_BUS (PIN | ESO | ACK)
|
||||
#define NEGATIVE_ACK ((ESO) & ~ACK)
|
||||
|
||||
#define SELECT(a) (a)
|
||||
#define S0 (PIN | ESO | ES1)
|
||||
#define S0_OWN (PIN)
|
||||
#define S2 (PIN | ES1)
|
||||
#define S3 (PIN | ES2)
|
||||
|
||||
#define ENABLE_SERIAL (PIN | ESO)
|
||||
#define DISABLE_SERIAL (PIN)
|
||||
#define RESET (PIN)
|
||||
|
||||
#define XMIT_LAST_BYTE (1)
|
||||
#define VFC_I2C_ACK_CHECK (1)
|
||||
#define VFC_I2C_NO_ACK_CHECK (0)
|
||||
|
||||
#endif /* _LINUX_VFC_I2C_H_ */
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user