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sh: intc - rework core code

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This patch reworks the intc core, implementing the following features:

- Support dual priority registers - one set and one clear register
- All 8/16/32 bit register combinations are now supported
- Both single mask and single enable bitmap register are supported
- Add code to set interrupt priority
- Speedup sense and priority configuration code
- Allocate data using bootmem, allows intc data structures to be
  __initdata
- Save memory - allocated memory footprint is smaller than intc
  structures

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
2007-08-12 15:26:12 +09:00
committed by Paul Mundt
parent 6ef5fb2cfc
commit 73505b445d
3 changed files with 345 additions and 229 deletions
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arch/sh/cchips/voyagergx/irq.c
+1 -1
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@@ -50,7 +50,7 @@ static struct intc_vect vectors[] = {
};
static struct intc_mask_reg mask_registers[] = {
{ VOYAGER_INT_MASK, 1, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
{ VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
{ UP, G54, G53, G52, G51, G50, G49, G48,
I2C, PW, 0, DMA, PCI, I2S, AC, US,
0, 0, U1, U0, CV, MC, S1, S0,