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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next into for-davem
This commit is contained in:
@@ -90,6 +90,7 @@ static struct usb_device_id ath3k_table[] = {
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{ USB_DEVICE(0x13d3, 0x3393) },
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{ USB_DEVICE(0x0489, 0xe04e) },
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{ USB_DEVICE(0x0489, 0xe056) },
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{ USB_DEVICE(0x0489, 0xe04d) },
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/* Atheros AR5BBU12 with sflash firmware */
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{ USB_DEVICE(0x0489, 0xE02C) },
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@@ -126,6 +127,7 @@ static struct usb_device_id ath3k_blist_tbl[] = {
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{ USB_DEVICE(0x13d3, 0x3393), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0489, 0xe04e), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0489, 0xe056), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0489, 0xe04d), .driver_info = BTUSB_ATH3012 },
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/* Atheros AR5BBU22 with sflash firmware */
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{ USB_DEVICE(0x0489, 0xE03C), .driver_info = BTUSB_ATH3012 },
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+20
-11
@@ -148,6 +148,7 @@ static struct usb_device_id blacklist_table[] = {
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{ USB_DEVICE(0x13d3, 0x3393), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0489, 0xe04e), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0489, 0xe056), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0489, 0xe04d), .driver_info = BTUSB_ATH3012 },
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/* Atheros AR5BBU12 with sflash firmware */
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{ USB_DEVICE(0x0489, 0xe02c), .driver_info = BTUSB_IGNORE },
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@@ -926,6 +927,22 @@ static void btusb_waker(struct work_struct *work)
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usb_autopm_put_interface(data->intf);
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}
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static int btusb_setup_bcm92035(struct hci_dev *hdev)
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{
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struct sk_buff *skb;
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u8 val = 0x00;
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BT_DBG("%s", hdev->name);
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skb = __hci_cmd_sync(hdev, 0xfc3b, 1, &val, HCI_INIT_TIMEOUT);
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if (IS_ERR(skb))
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BT_ERR("BCM92035 command failed (%ld)", -PTR_ERR(skb));
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else
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kfree_skb(skb);
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return 0;
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}
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static int btusb_probe(struct usb_interface *intf,
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const struct usb_device_id *id)
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{
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@@ -1028,6 +1045,9 @@ static int btusb_probe(struct usb_interface *intf,
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hdev->send = btusb_send_frame;
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hdev->notify = btusb_notify;
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if (id->driver_info & BTUSB_BCM92035)
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hdev->setup = btusb_setup_bcm92035;
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/* Interface numbers are hardcoded in the specification */
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data->isoc = usb_ifnum_to_if(data->udev, 1);
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@@ -1065,17 +1085,6 @@ static int btusb_probe(struct usb_interface *intf,
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data->isoc = NULL;
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}
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if (id->driver_info & BTUSB_BCM92035) {
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unsigned char cmd[] = { 0x3b, 0xfc, 0x01, 0x00 };
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struct sk_buff *skb;
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skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL);
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if (skb) {
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memcpy(skb_put(skb, sizeof(cmd)), cmd, sizeof(cmd));
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skb_queue_tail(&hdev->driver_init, skb);
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}
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}
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if (data->isoc) {
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err = usb_driver_claim_interface(&btusb_driver,
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data->isoc, data);
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@@ -153,6 +153,9 @@ static int h4_recv(struct hci_uart *hu, void *data, int count)
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{
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int ret;
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if (!test_bit(HCI_UART_REGISTERED, &hu->flags))
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return -EUNATCH;
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ret = hci_recv_stream_fragment(hu->hdev, data, count);
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if (ret < 0) {
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BT_ERR("Frame Reassembly Failed");
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@@ -388,7 +388,10 @@ static void hci_uart_tty_receive(struct tty_struct *tty, const u8 *data, char *f
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spin_lock(&hu->rx_lock);
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hu->proto->recv(hu, (void *) data, count);
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if (hu->hdev)
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hu->hdev->stat.byte_rx += count;
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spin_unlock(&hu->rx_lock);
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tty_unthrottle(tty);
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@@ -1293,7 +1293,8 @@ static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
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{
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struct adm8211_priv *priv = dev->priv;
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struct ieee80211_conf *conf = &dev->conf;
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int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
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int channel =
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ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
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if (channel != priv->channel) {
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priv->channel = channel;
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@@ -1943,12 +1943,12 @@ static int at76_config(struct ieee80211_hw *hw, u32 changed)
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struct at76_priv *priv = hw->priv;
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at76_dbg(DBG_MAC80211, "%s(): channel %d",
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__func__, hw->conf.channel->hw_value);
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__func__, hw->conf.chandef.chan->hw_value);
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at76_dbg_dump(DBG_MAC80211, priv->bssid, ETH_ALEN, "bssid:");
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mutex_lock(&priv->mtx);
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priv->channel = hw->conf.channel->hw_value;
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priv->channel = hw->conf.chandef.chan->hw_value;
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if (is_valid_ether_addr(priv->bssid))
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at76_join(priv);
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@@ -457,14 +457,14 @@ static int ar5523_set_chan(struct ar5523 *ar)
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memset(&reset, 0, sizeof(reset));
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reset.flags |= cpu_to_be32(UATH_CHAN_2GHZ);
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reset.flags |= cpu_to_be32(UATH_CHAN_OFDM);
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reset.freq = cpu_to_be32(conf->channel->center_freq);
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reset.freq = cpu_to_be32(conf->chandef.chan->center_freq);
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reset.maxrdpower = cpu_to_be32(50); /* XXX */
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reset.channelchange = cpu_to_be32(1);
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reset.keeprccontent = cpu_to_be32(0);
|
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|
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ar5523_dbg(ar, "set chan flags 0x%x freq %d\n",
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be32_to_cpu(reset.flags),
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conf->channel->center_freq);
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conf->chandef.chan->center_freq);
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return ar5523_cmd_write(ar, WDCMSG_RESET, &reset, sizeof(reset), 0);
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}
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@@ -594,7 +594,7 @@ static void ar5523_data_rx_cb(struct urb *urb)
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rx_status = IEEE80211_SKB_RXCB(data->skb);
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memset(rx_status, 0, sizeof(*rx_status));
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rx_status->freq = be32_to_cpu(desc->channel);
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rx_status->band = hw->conf.channel->band;
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rx_status->band = hw->conf.chandef.chan->band;
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rx_status->signal = -95 + be32_to_cpu(desc->rssi);
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ieee80211_rx_irqsafe(hw, data->skb);
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@@ -1153,13 +1153,13 @@ static int ar5523_get_wlan_mode(struct ar5523 *ar,
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struct ieee80211_sta *sta;
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u32 sta_rate_set;
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band = ar->hw->wiphy->bands[ar->hw->conf.channel->band];
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band = ar->hw->wiphy->bands[ar->hw->conf.chandef.chan->band];
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sta = ieee80211_find_sta(ar->vif, bss_conf->bssid);
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if (!sta) {
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ar5523_info(ar, "STA not found!\n");
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return WLAN_MODE_11b;
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}
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sta_rate_set = sta->supp_rates[ar->hw->conf.channel->band];
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sta_rate_set = sta->supp_rates[ar->hw->conf.chandef.chan->band];
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for (bit = 0; bit < band->n_bitrates; bit++) {
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if (sta_rate_set & 1) {
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@@ -1197,11 +1197,11 @@ static void ar5523_create_rateset(struct ar5523 *ar,
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ar5523_info(ar, "STA not found. Cannot set rates\n");
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sta_rate_set = bss_conf->basic_rates;
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} else
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sta_rate_set = sta->supp_rates[ar->hw->conf.channel->band];
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sta_rate_set = sta->supp_rates[ar->hw->conf.chandef.chan->band];
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ar5523_dbg(ar, "sta rate_set = %08x\n", sta_rate_set);
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band = ar->hw->wiphy->bands[ar->hw->conf.channel->band];
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band = ar->hw->wiphy->bands[ar->hw->conf.chandef.chan->band];
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for (bit = 0; bit < band->n_bitrates; bit++) {
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BUG_ON(i >= AR5523_MAX_NRATES);
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ar5523_dbg(ar, "Considering rate %d : %d\n",
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@@ -10,6 +10,7 @@ ath5k-y += phy.o
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ath5k-y += reset.o
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ath5k-y += attach.o
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ath5k-y += base.o
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CFLAGS_base.o += -I$(src)
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ath5k-y += led.o
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ath5k-y += rfkill.o
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ath5k-y += ani.o
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@@ -2639,7 +2639,7 @@ int ath5k_start(struct ieee80211_hw *hw)
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* be followed by initialization of the appropriate bits
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* and then setup of the interrupt mask.
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*/
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ah->curchan = ah->hw->conf.channel;
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ah->curchan = ah->hw->conf.chandef.chan;
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ah->imask = AR5K_INT_RXOK
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| AR5K_INT_RXERR
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| AR5K_INT_RXEOL
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@@ -202,7 +202,7 @@ ath5k_config(struct ieee80211_hw *hw, u32 changed)
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mutex_lock(&ah->lock);
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if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
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ret = ath5k_chan_set(ah, conf->channel);
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ret = ath5k_chan_set(ah, conf->chandef.chan);
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if (ret < 0)
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goto unlock;
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}
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@@ -678,7 +678,7 @@ ath5k_get_survey(struct ieee80211_hw *hw, int idx, struct survey_info *survey)
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memcpy(survey, &ah->survey, sizeof(*survey));
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survey->channel = conf->channel;
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survey->channel = conf->chandef.chan;
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survey->noise = ah->ah_noise_floor;
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survey->filled = SURVEY_INFO_NOISE_DBM |
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SURVEY_INFO_CHANNEL_TIME |
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||||
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@@ -97,7 +97,7 @@ TRACE_EVENT(ath5k_tx_complete,
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#if defined(CONFIG_ATH5K_TRACER) && !defined(__CHECKER__)
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|
||||
#undef TRACE_INCLUDE_PATH
|
||||
#define TRACE_INCLUDE_PATH ../../drivers/net/wireless/ath/ath5k
|
||||
#define TRACE_INCLUDE_PATH .
|
||||
#undef TRACE_INCLUDE_FILE
|
||||
#define TRACE_INCLUDE_FILE trace
|
||||
|
||||
|
||||
@@ -18,6 +18,7 @@
|
||||
#include "hw-ops.h"
|
||||
#include "../regd.h"
|
||||
#include "ar9002_phy.h"
|
||||
#include "ar5008_initvals.h"
|
||||
|
||||
/* All code below is for AR5008, AR9001, AR9002 */
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||||
|
||||
@@ -43,23 +44,16 @@ static const int m2ThreshLowExt_off = 127;
|
||||
static const int m1ThreshExt_off = 127;
|
||||
static const int m2ThreshExt_off = 127;
|
||||
|
||||
static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0);
|
||||
static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1);
|
||||
static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2);
|
||||
static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3);
|
||||
static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7);
|
||||
|
||||
static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
|
||||
int col)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < array->ia_rows; i++)
|
||||
bank[i] = INI_RA(array, i, col);
|
||||
}
|
||||
|
||||
|
||||
#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
|
||||
ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
|
||||
|
||||
static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
|
||||
u32 *data, unsigned int *writecnt)
|
||||
static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt)
|
||||
{
|
||||
struct ar5416IniArray *array = &ah->iniBank6;
|
||||
u32 *data = ah->analogBank6Data;
|
||||
int r;
|
||||
|
||||
ENABLE_REGWRITE_BUFFER(ah);
|
||||
@@ -165,7 +159,7 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
|
||||
ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
|
||||
|
||||
/* write Bank 6 with new params */
|
||||
REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
|
||||
ar5008_write_bank6(ah, ®_writes);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -469,31 +463,16 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
|
||||
*/
|
||||
static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
|
||||
{
|
||||
#define ATH_ALLOC_BANK(bank, size) do { \
|
||||
bank = devm_kzalloc(ah->dev, sizeof(u32) * size, GFP_KERNEL); \
|
||||
if (!bank) \
|
||||
goto error; \
|
||||
} while (0);
|
||||
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
int size = ah->iniBank6.ia_rows * sizeof(u32);
|
||||
|
||||
if (AR_SREV_9280_20_OR_LATER(ah))
|
||||
return 0;
|
||||
|
||||
ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
|
||||
ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
|
||||
ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
|
||||
ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
|
||||
ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
|
||||
ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
|
||||
ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
|
||||
ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
|
||||
ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
|
||||
if (!ah->analogBank6Data)
|
||||
return -ENOMEM;
|
||||
|
||||
return 0;
|
||||
#undef ATH_ALLOC_BANK
|
||||
error:
|
||||
ath_err(common, "Cannot allocate RF banks\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
||||
@@ -517,6 +496,7 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
|
||||
u32 ob5GHz = 0, db5GHz = 0;
|
||||
u32 ob2GHz = 0, db2GHz = 0;
|
||||
int regWrites = 0;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Software does not need to program bank data
|
||||
@@ -529,25 +509,8 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
|
||||
/* Setup rf parameters */
|
||||
eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
|
||||
|
||||
/* Setup Bank 0 Write */
|
||||
ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
|
||||
|
||||
/* Setup Bank 1 Write */
|
||||
ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
|
||||
|
||||
/* Setup Bank 2 Write */
|
||||
ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
|
||||
|
||||
/* Setup Bank 6 Write */
|
||||
ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
|
||||
modesIndex);
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
|
||||
ah->analogBank6Data[i] =
|
||||
INI_RA(&ah->iniBank6TPC, i, modesIndex);
|
||||
}
|
||||
}
|
||||
for (i = 0; i < ah->iniBank6.ia_rows; i++)
|
||||
ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex);
|
||||
|
||||
/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
|
||||
if (eepMinorRev >= 2) {
|
||||
@@ -568,22 +531,13 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
|
||||
}
|
||||
}
|
||||
|
||||
/* Setup Bank 7 Setup */
|
||||
ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
|
||||
|
||||
/* Write Analog registers */
|
||||
REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
|
||||
regWrites);
|
||||
REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
|
||||
regWrites);
|
||||
REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
|
||||
regWrites);
|
||||
REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
|
||||
regWrites);
|
||||
REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
|
||||
regWrites);
|
||||
REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
|
||||
regWrites);
|
||||
REG_WRITE_ARRAY(&bank0, 1, regWrites);
|
||||
REG_WRITE_ARRAY(&bank1, 1, regWrites);
|
||||
REG_WRITE_ARRAY(&bank2, 1, regWrites);
|
||||
REG_WRITE_ARRAY(&bank3, modesIndex, regWrites);
|
||||
ar5008_write_bank6(ah, ®Writes);
|
||||
REG_WRITE_ARRAY(&bank7, 1, regWrites);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -67,12 +67,10 @@ static int ar9002_hw_init_mode_regs(struct ath_hw *ah)
|
||||
} else if (AR_SREV_9100_OR_LATER(ah)) {
|
||||
INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
|
||||
INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
|
||||
INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
|
||||
INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
|
||||
} else {
|
||||
INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
|
||||
INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
|
||||
INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
|
||||
INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
|
||||
}
|
||||
|
||||
@@ -80,20 +78,11 @@ static int ar9002_hw_init_mode_regs(struct ath_hw *ah)
|
||||
/* Common for AR5416, AR913x, AR9160 */
|
||||
INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
|
||||
|
||||
INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0);
|
||||
INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1);
|
||||
INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2);
|
||||
INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
|
||||
INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
|
||||
|
||||
/* Common for AR5416, AR9160 */
|
||||
if (!AR_SREV_9100(ah))
|
||||
INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
|
||||
|
||||
/* Common for AR913x, AR9160 */
|
||||
if (!AR_SREV_5416(ah))
|
||||
INIT_INI_ARRAY(&ah->iniBank6TPC,
|
||||
ar5416Bank6TPC_9100);
|
||||
INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100);
|
||||
else
|
||||
INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC);
|
||||
}
|
||||
|
||||
/* iniAddac needs to be modified for these chips */
|
||||
|
||||
@@ -234,6 +234,7 @@ struct ath_buf {
|
||||
dma_addr_t bf_daddr; /* physical addr of desc */
|
||||
dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
|
||||
bool bf_stale;
|
||||
struct ieee80211_tx_rate rates[4];
|
||||
struct ath_buf_state bf_state;
|
||||
};
|
||||
|
||||
@@ -311,6 +312,7 @@ struct ath_rx_edma {
|
||||
struct ath_rx {
|
||||
u8 defant;
|
||||
u8 rxotherant;
|
||||
bool discard_next;
|
||||
u32 *rxlink;
|
||||
u32 num_pkts;
|
||||
unsigned int rxfilter;
|
||||
@@ -657,11 +659,10 @@ enum sc_op_flags {
|
||||
struct ath_rate_table;
|
||||
|
||||
struct ath9k_vif_iter_data {
|
||||
const u8 *hw_macaddr; /* phy's hardware address, set
|
||||
* before starting iteration for
|
||||
* valid bssid mask.
|
||||
*/
|
||||
u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
|
||||
u8 mask[ETH_ALEN]; /* bssid mask */
|
||||
bool has_hw_macaddr;
|
||||
|
||||
int naps; /* number of AP vifs */
|
||||
int nmeshes; /* number of mesh vifs */
|
||||
int nstations; /* number of station vifs */
|
||||
|
||||
@@ -79,7 +79,7 @@ static void ath9k_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
|
||||
u8 chainmask = ah->txchainmask;
|
||||
u8 rate = 0;
|
||||
|
||||
sband = &sc->sbands[common->hw->conf.channel->band];
|
||||
sband = &sc->sbands[common->hw->conf.chandef.chan->band];
|
||||
rate = sband->bitrates[rateidx].hw_value;
|
||||
if (vif->bss_conf.use_short_preamble)
|
||||
rate |= sband->bitrates[rateidx].hw_value_short;
|
||||
|
||||
@@ -208,7 +208,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
|
||||
return true;
|
||||
|
||||
ath_dbg(common, CALIBRATE, "Resetting Cal %d state for channel %u\n",
|
||||
currCal->calData->calType, conf->channel->center_freq);
|
||||
currCal->calData->calType, conf->chandef.chan->center_freq);
|
||||
|
||||
ah->caldata->CalValid &= ~currCal->calData->calType;
|
||||
currCal->calState = CAL_WAITING;
|
||||
|
||||
@@ -33,6 +33,12 @@ struct ar5416IniArray {
|
||||
u32 ia_columns;
|
||||
};
|
||||
|
||||
#define STATIC_INI_ARRAY(array) { \
|
||||
.ia_array = (u32 *)(array), \
|
||||
.ia_rows = ARRAY_SIZE(array), \
|
||||
.ia_columns = ARRAY_SIZE(array[0]), \
|
||||
}
|
||||
|
||||
#define INIT_INI_ARRAY(iniarray, array) do { \
|
||||
(iniarray)->ia_array = (u32 *)(array); \
|
||||
(iniarray)->ia_rows = ARRAY_SIZE(array); \
|
||||
|
||||
@@ -27,20 +27,6 @@ MODULE_AUTHOR("Atheros Communications");
|
||||
MODULE_DESCRIPTION("Shared library for Atheros wireless 802.11n LAN cards.");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
||||
int ath9k_cmn_padpos(__le16 frame_control)
|
||||
{
|
||||
int padpos = 24;
|
||||
if (ieee80211_has_a4(frame_control)) {
|
||||
padpos += ETH_ALEN;
|
||||
}
|
||||
if (ieee80211_is_data_qos(frame_control)) {
|
||||
padpos += IEEE80211_QOS_CTL_LEN;
|
||||
}
|
||||
|
||||
return padpos;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_cmn_padpos);
|
||||
|
||||
int ath9k_cmn_get_hw_crypto_keytype(struct sk_buff *skb)
|
||||
{
|
||||
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
|
||||
@@ -133,13 +119,14 @@ EXPORT_SYMBOL(ath9k_cmn_update_ichannel);
|
||||
struct ath9k_channel *ath9k_cmn_get_curchannel(struct ieee80211_hw *hw,
|
||||
struct ath_hw *ah)
|
||||
{
|
||||
struct ieee80211_channel *curchan = hw->conf.channel;
|
||||
struct ieee80211_channel *curchan = hw->conf.chandef.chan;
|
||||
struct ath9k_channel *channel;
|
||||
u8 chan_idx;
|
||||
|
||||
chan_idx = curchan->hw_value;
|
||||
channel = &ah->channels[chan_idx];
|
||||
ath9k_cmn_update_ichannel(channel, curchan, hw->conf.channel_type);
|
||||
ath9k_cmn_update_ichannel(channel, curchan,
|
||||
cfg80211_get_chandef_type(&hw->conf.chandef));
|
||||
|
||||
return channel;
|
||||
}
|
||||
|
||||
@@ -42,7 +42,6 @@
|
||||
#define ATH_EP_RND(x, mul) \
|
||||
(((x) + ((mul)/2)) / (mul))
|
||||
|
||||
int ath9k_cmn_padpos(__le16 frame_control);
|
||||
int ath9k_cmn_get_hw_crypto_keytype(struct sk_buff *skb);
|
||||
void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
|
||||
struct ieee80211_channel *chan,
|
||||
|
||||
@@ -55,12 +55,6 @@ ath9k_postprocess_radar_event(struct ath_softc *sc,
|
||||
u8 rssi;
|
||||
u16 dur;
|
||||
|
||||
ath_dbg(ath9k_hw_common(sc->sc_ah), DFS,
|
||||
"pulse_bw_info=0x%x, pri,ext len/rssi=(%u/%u, %u/%u)\n",
|
||||
ard->pulse_bw_info,
|
||||
ard->pulse_length_pri, ard->rssi,
|
||||
ard->pulse_length_ext, ard->ext_rssi);
|
||||
|
||||
/*
|
||||
* Only the last 2 bits of the BW info are relevant, they indicate
|
||||
* which channel the radar was detected in.
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user