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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"Driver updates for ARM SoCs, including a couple of newly added
drivers:
- The Qualcomm external bus interface 2 (EBI2), used in some of their
mobile phone chips for connecting flash memory, LCD displays or
other peripherals
- Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for
the EFUSE based on that firmware interface.
- Perf support for the AppliedMicro X-Gene performance monitor unit
- Reset driver for STMicroelectronics STM32
- Reset driver for SocioNext UniPhier SoCs
Aside from these, there are minor updates to SoC-specific bus,
clocksource, firmware, pinctrl, reset, rtc and pmic drivers"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
bus: qcom-ebi2: depend on HAS_IOMEM
pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
clk: mvebu: Add clk support for the orion5x SoC mv88f5181
dt-bindings: EXYNOS: Add Exynos5433 PMU compatible
clocksource: exynos_mct: Add the support for ARM64
perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
MAINTAINERS: Add entry for APM X-Gene SoC PMU driver
bus: qcom: add EBI2 driver
bus: qcom: add EBI2 device tree bindings
rtc: rtc-pm8xxx: Add support for pm8018 rtc
nvmem: amlogic: Add Amlogic Meson EFUSE driver
firmware: Amlogic: Add secure monitor driver
soc: qcom: smd: Reset rx tail rather than tx
memory: atmel-sdramc: fix a possible NULL dereference
reset: hi6220: allow to compile test driver on other architectures
reset: zynq: add driver Kconfig option
reset: sunxi: add driver Kconfig option
reset: stm32: add driver Kconfig option
reset: socfpga: add driver Kconfig option
...
This commit is contained in:
@@ -361,7 +361,7 @@ config CLKSRC_METAG_GENERIC
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config CLKSRC_EXYNOS_MCT
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bool "Exynos multi core timer driver" if COMPILE_TEST
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depends on ARM
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depends on ARM || ARM64
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help
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Support for Multi Core Timer controller on Exynos SoCs.
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@@ -223,6 +223,7 @@ static u64 notrace exynos4_read_sched_clock(void)
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return exynos4_read_count_32();
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}
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#if defined(CONFIG_ARM)
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static struct delay_timer exynos4_delay_timer;
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static cycles_t exynos4_read_current_timer(void)
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@@ -231,14 +232,17 @@ static cycles_t exynos4_read_current_timer(void)
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"cycles_t needs to move to 32-bit for ARM64 usage");
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return exynos4_read_count_32();
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}
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#endif
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static int __init exynos4_clocksource_init(void)
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{
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exynos4_mct_frc_start();
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#if defined(CONFIG_ARM)
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exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
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exynos4_delay_timer.freq = clk_rate;
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register_current_timer_delay(&exynos4_delay_timer);
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#endif
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if (clocksource_register_hz(&mct_frc, clk_rate))
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panic("%s: can't register clocksource\n", mct_frc.name);
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