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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"Driver updates for ARM SoCs, including a couple of newly added
drivers:
- The Qualcomm external bus interface 2 (EBI2), used in some of their
mobile phone chips for connecting flash memory, LCD displays or
other peripherals
- Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for
the EFUSE based on that firmware interface.
- Perf support for the AppliedMicro X-Gene performance monitor unit
- Reset driver for STMicroelectronics STM32
- Reset driver for SocioNext UniPhier SoCs
Aside from these, there are minor updates to SoC-specific bus,
clocksource, firmware, pinctrl, reset, rtc and pmic drivers"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
bus: qcom-ebi2: depend on HAS_IOMEM
pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
clk: mvebu: Add clk support for the orion5x SoC mv88f5181
dt-bindings: EXYNOS: Add Exynos5433 PMU compatible
clocksource: exynos_mct: Add the support for ARM64
perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
MAINTAINERS: Add entry for APM X-Gene SoC PMU driver
bus: qcom: add EBI2 driver
bus: qcom: add EBI2 device tree bindings
rtc: rtc-pm8xxx: Add support for pm8018 rtc
nvmem: amlogic: Add Amlogic Meson EFUSE driver
firmware: Amlogic: Add secure monitor driver
soc: qcom: smd: Reset rx tail rather than tx
memory: atmel-sdramc: fix a possible NULL dereference
reset: hi6220: allow to compile test driver on other architectures
reset: zynq: add driver Kconfig option
reset: sunxi: add driver Kconfig option
reset: stm32: add driver Kconfig option
reset: socfpga: add driver Kconfig option
...
This commit is contained in:
Linus Torvalds
+9
-5
@@ -108,6 +108,14 @@ config OMAP_OCP2SCP
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OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
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OCP2SCP.
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config QCOM_EBI2
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bool "Qualcomm External Bus Interface 2 (EBI2)"
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depends on HAS_IOMEM
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help
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Say y here to enable support for the Qualcomm External Bus
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Interface 2, which can be used to connect things like NAND Flash,
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SRAM, ethernet adapters, FPGAs and LCD displays.
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config SIMPLE_PM_BUS
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bool "Simple Power-Managed Bus Driver"
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depends on OF && PM
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@@ -132,12 +140,8 @@ config SUNXI_RSB
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with various RSB based devices, such as AXP223, AXP8XX PMICs,
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and AC100/AC200 ICs.
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# TODO: This uses pm_clk_*() symbols that aren't exported in v4.7 and hence
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# the driver will fail to build as a module. However there are patches to
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# address that queued for v4.8, so this can be turned into a tristate symbol
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# after v4.8-rc1.
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config TEGRA_ACONNECT
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bool "Tegra ACONNECT Bus Driver"
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tristate "Tegra ACONNECT Bus Driver"
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depends on ARCH_TEGRA_210_SOC
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depends on OF && PM
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select PM_CLK
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@@ -15,6 +15,7 @@ obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
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obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
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obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
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obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o
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obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
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obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
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obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o
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@@ -0,0 +1,408 @@
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/*
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* Qualcomm External Bus Interface 2 (EBI2) driver
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* an older version of the Qualcomm Parallel Interface Controller (QPIC)
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*
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* Copyright (C) 2016 Linaro Ltd.
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*
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* Author: Linus Walleij <linus.walleij@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*
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* See the device tree bindings for this block for more details on the
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* hardware.
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*/
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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/*
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* CS0, CS1, CS4 and CS5 are two bits wide, CS2 and CS3 are one bit.
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*/
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#define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1)
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#define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3)
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#define EBI2_CS2_ENABLE_MASK BIT(4)
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#define EBI2_CS3_ENABLE_MASK BIT(5)
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#define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7)
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#define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9)
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#define EBI2_CSN_MASK GENMASK(9, 0)
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#define EBI2_XMEM_CFG 0x0000 /* Power management etc */
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/*
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* SLOW CSn CFG
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*
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* Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
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* memory continues to drive the data bus after OE is de-asserted.
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* Inserted when reading one CS and switching to another CS or read
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* followed by write on the same CS. Valid values 0 thru 15.
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* Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
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* every write minimum 1. The data out is driven from the time WE is
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* asserted until CS is asserted. With a hold of 1, the CS stays
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* active for 1 extra cycle etc. Valid values 0 thru 15.
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* Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
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* write to a page or burst memory
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* Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
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* read to a page or burst memory
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* Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
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* so 1 thru 16 cycles.
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* Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
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* so 1 thru 16 cycles.
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*/
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#define EBI2_XMEM_CS0_SLOW_CFG 0x0008
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#define EBI2_XMEM_CS1_SLOW_CFG 0x000C
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#define EBI2_XMEM_CS2_SLOW_CFG 0x0010
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#define EBI2_XMEM_CS3_SLOW_CFG 0x0014
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#define EBI2_XMEM_CS4_SLOW_CFG 0x0018
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#define EBI2_XMEM_CS5_SLOW_CFG 0x001C
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#define EBI2_XMEM_RECOVERY_SHIFT 28
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#define EBI2_XMEM_WR_HOLD_SHIFT 24
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#define EBI2_XMEM_WR_DELTA_SHIFT 16
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#define EBI2_XMEM_RD_DELTA_SHIFT 8
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#define EBI2_XMEM_WR_WAIT_SHIFT 4
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#define EBI2_XMEM_RD_WAIT_SHIFT 0
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/*
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* FAST CSn CFG
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* Bits 31-28: ?
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* Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read
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* transfer. For a single read trandfer this will be the time
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* from CS assertion to OE assertion.
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* Bits 18-24: ?
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* Bits 17-16: ADV_OE_RECOVERY, the number of cycles elapsed before an OE
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* assertion, with respect to the cycle where ADV is asserted.
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* 2 means 2 cycles between ADV and OE. Values 0, 1, 2 or 3.
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* Bits 5: ADDR_HOLD_ENA, The address is held for an extra cycle to meet
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* hold time requirements with ADV assertion.
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*
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* The manual mentions "write precharge cycles" and "precharge cycles".
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* We have not been able to figure out which bit fields these correspond to
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* in the hardware, or what valid values exist. The current hypothesis is that
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* this is something just used on the FAST chip selects. There is also a "byte
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* device enable" flag somewhere for 8bit memories.
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*/
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#define EBI2_XMEM_CS0_FAST_CFG 0x0028
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#define EBI2_XMEM_CS1_FAST_CFG 0x002C
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#define EBI2_XMEM_CS2_FAST_CFG 0x0030
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#define EBI2_XMEM_CS3_FAST_CFG 0x0034
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#define EBI2_XMEM_CS4_FAST_CFG 0x0038
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#define EBI2_XMEM_CS5_FAST_CFG 0x003C
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#define EBI2_XMEM_RD_HOLD_SHIFT 24
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#define EBI2_XMEM_ADV_OE_RECOVERY_SHIFT 16
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#define EBI2_XMEM_ADDR_HOLD_ENA_SHIFT 5
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/**
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* struct cs_data - struct with info on a chipselect setting
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* @enable_mask: mask to enable the chipselect in the EBI2 config
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* @slow_cfg0: offset to XMEMC slow CS config
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* @fast_cfg1: offset to XMEMC fast CS config
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*/
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struct cs_data {
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u32 enable_mask;
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u16 slow_cfg;
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u16 fast_cfg;
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};
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static const struct cs_data cs_info[] = {
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{
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/* CS0 */
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.enable_mask = EBI2_CS0_ENABLE_MASK,
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.slow_cfg = EBI2_XMEM_CS0_SLOW_CFG,
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.fast_cfg = EBI2_XMEM_CS0_FAST_CFG,
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},
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{
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/* CS1 */
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.enable_mask = EBI2_CS1_ENABLE_MASK,
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.slow_cfg = EBI2_XMEM_CS1_SLOW_CFG,
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.fast_cfg = EBI2_XMEM_CS1_FAST_CFG,
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},
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{
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/* CS2 */
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.enable_mask = EBI2_CS2_ENABLE_MASK,
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.slow_cfg = EBI2_XMEM_CS2_SLOW_CFG,
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.fast_cfg = EBI2_XMEM_CS2_FAST_CFG,
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},
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{
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/* CS3 */
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.enable_mask = EBI2_CS3_ENABLE_MASK,
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.slow_cfg = EBI2_XMEM_CS3_SLOW_CFG,
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.fast_cfg = EBI2_XMEM_CS3_FAST_CFG,
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},
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{
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/* CS4 */
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.enable_mask = EBI2_CS4_ENABLE_MASK,
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.slow_cfg = EBI2_XMEM_CS4_SLOW_CFG,
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.fast_cfg = EBI2_XMEM_CS4_FAST_CFG,
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},
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{
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/* CS5 */
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.enable_mask = EBI2_CS5_ENABLE_MASK,
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.slow_cfg = EBI2_XMEM_CS5_SLOW_CFG,
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.fast_cfg = EBI2_XMEM_CS5_FAST_CFG,
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},
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};
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/**
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* struct ebi2_xmem_prop - describes an XMEM config property
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* @prop: the device tree binding name
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* @max: maximum value for the property
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* @slowreg: true if this property is in the SLOW CS config register
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* else it is assumed to be in the FAST config register
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* @shift: the bit field start in the SLOW or FAST register for this
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* property
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*/
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struct ebi2_xmem_prop {
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const char *prop;
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u32 max;
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bool slowreg;
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u16 shift;
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};
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static const struct ebi2_xmem_prop xmem_props[] = {
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{
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.prop = "qcom,xmem-recovery-cycles",
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.max = 15,
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.slowreg = true,
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.shift = EBI2_XMEM_RECOVERY_SHIFT,
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},
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{
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.prop = "qcom,xmem-write-hold-cycles",
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.max = 15,
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.slowreg = true,
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.shift = EBI2_XMEM_WR_HOLD_SHIFT,
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},
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{
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.prop = "qcom,xmem-write-delta-cycles",
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.max = 255,
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.slowreg = true,
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.shift = EBI2_XMEM_WR_DELTA_SHIFT,
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},
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{
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.prop = "qcom,xmem-read-delta-cycles",
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.max = 255,
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.slowreg = true,
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.shift = EBI2_XMEM_RD_DELTA_SHIFT,
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},
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{
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.prop = "qcom,xmem-write-wait-cycles",
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.max = 15,
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.slowreg = true,
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.shift = EBI2_XMEM_WR_WAIT_SHIFT,
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},
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{
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.prop = "qcom,xmem-read-wait-cycles",
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.max = 15,
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.slowreg = true,
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.shift = EBI2_XMEM_RD_WAIT_SHIFT,
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},
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{
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.prop = "qcom,xmem-address-hold-enable",
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.max = 1, /* boolean prop */
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.slowreg = false,
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.shift = EBI2_XMEM_ADDR_HOLD_ENA_SHIFT,
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},
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{
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.prop = "qcom,xmem-adv-to-oe-recovery-cycles",
|
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.max = 3,
|
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.slowreg = false,
|
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.shift = EBI2_XMEM_ADV_OE_RECOVERY_SHIFT,
|
||||
},
|
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{
|
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.prop = "qcom,xmem-read-hold-cycles",
|
||||
.max = 15,
|
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.slowreg = false,
|
||||
.shift = EBI2_XMEM_RD_HOLD_SHIFT,
|
||||
},
|
||||
};
|
||||
|
||||
static void qcom_ebi2_setup_chipselect(struct device_node *np,
|
||||
struct device *dev,
|
||||
void __iomem *ebi2_base,
|
||||
void __iomem *ebi2_xmem,
|
||||
u32 csindex)
|
||||
{
|
||||
const struct cs_data *csd;
|
||||
u32 slowcfg, fastcfg;
|
||||
u32 val;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
csd = &cs_info[csindex];
|
||||
val = readl(ebi2_base);
|
||||
val |= csd->enable_mask;
|
||||
writel(val, ebi2_base);
|
||||
dev_dbg(dev, "enabled CS%u\n", csindex);
|
||||
|
||||
/* Next set up the XMEMC */
|
||||
slowcfg = 0;
|
||||
fastcfg = 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(xmem_props); i++) {
|
||||
const struct ebi2_xmem_prop *xp = &xmem_props[i];
|
||||
|
||||
/* All are regular u32 values */
|
||||
ret = of_property_read_u32(np, xp->prop, &val);
|
||||
if (ret) {
|
||||
dev_dbg(dev, "could not read %s for CS%d\n",
|
||||
xp->prop, csindex);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* First check boolean props */
|
||||
if (xp->max == 1 && val) {
|
||||
if (xp->slowreg)
|
||||
slowcfg |= BIT(xp->shift);
|
||||
else
|
||||
fastcfg |= BIT(xp->shift);
|
||||
dev_dbg(dev, "set %s flag\n", xp->prop);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* We're dealing with an u32 */
|
||||
if (val > xp->max) {
|
||||
dev_err(dev,
|
||||
"too high value for %s: %u, capped at %u\n",
|
||||
xp->prop, val, xp->max);
|
||||
val = xp->max;
|
||||
}
|
||||
if (xp->slowreg)
|
||||
slowcfg |= (val << xp->shift);
|
||||
else
|
||||
fastcfg |= (val << xp->shift);
|
||||
dev_dbg(dev, "set %s to %u\n", xp->prop, val);
|
||||
}
|
||||
|
||||
dev_info(dev, "CS%u: SLOW CFG 0x%08x, FAST CFG 0x%08x\n",
|
||||
csindex, slowcfg, fastcfg);
|
||||
|
||||
if (slowcfg)
|
||||
writel(slowcfg, ebi2_xmem + csd->slow_cfg);
|
||||
if (fastcfg)
|
||||
writel(fastcfg, ebi2_xmem + csd->fast_cfg);
|
||||
}
|
||||
|
||||
static int qcom_ebi2_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device_node *child;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
void __iomem *ebi2_base;
|
||||
void __iomem *ebi2_xmem;
|
||||
struct clk *ebi2xclk;
|
||||
struct clk *ebi2clk;
|
||||
bool have_children = false;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ebi2xclk = devm_clk_get(dev, "ebi2x");
|
||||
if (IS_ERR(ebi2xclk))
|
||||
return PTR_ERR(ebi2xclk);
|
||||
|
||||
ret = clk_prepare_enable(ebi2xclk);
|
||||
if (ret) {
|
||||
dev_err(dev, "could not enable EBI2X clk (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ebi2clk = devm_clk_get(dev, "ebi2");
|
||||
if (IS_ERR(ebi2clk)) {
|
||||
ret = PTR_ERR(ebi2clk);
|
||||
goto err_disable_2x_clk;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(ebi2clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "could not enable EBI2 clk\n");
|
||||
goto err_disable_2x_clk;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
ebi2_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(ebi2_base)) {
|
||||
ret = PTR_ERR(ebi2_base);
|
||||
goto err_disable_clk;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
ebi2_xmem = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(ebi2_xmem)) {
|
||||
ret = PTR_ERR(ebi2_xmem);
|
||||
goto err_disable_clk;
|
||||
}
|
||||
|
||||
/* Allegedly this turns the power save mode off */
|
||||
writel(0UL, ebi2_xmem + EBI2_XMEM_CFG);
|
||||
|
||||
/* Disable all chipselects */
|
||||
val = readl(ebi2_base);
|
||||
val &= ~EBI2_CSN_MASK;
|
||||
writel(val, ebi2_base);
|
||||
|
||||
/* Walk over the child nodes and see what chipselects we use */
|
||||
for_each_available_child_of_node(np, child) {
|
||||
u32 csindex;
|
||||
|
||||
/* Figure out the chipselect */
|
||||
ret = of_property_read_u32(child, "reg", &csindex);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (csindex > 5) {
|
||||
dev_err(dev,
|
||||
"invalid chipselect %u, we only support 0-5\n",
|
||||
csindex);
|
||||
continue;
|
||||
}
|
||||
|
||||
qcom_ebi2_setup_chipselect(child,
|
||||
dev,
|
||||
ebi2_base,
|
||||
ebi2_xmem,
|
||||
csindex);
|
||||
|
||||
/* We have at least one child */
|
||||
have_children = true;
|
||||
}
|
||||
|
||||
if (have_children)
|
||||
return of_platform_default_populate(np, NULL, dev);
|
||||
return 0;
|
||||
|
||||
err_disable_clk:
|
||||
clk_disable_unprepare(ebi2clk);
|
||||
err_disable_2x_clk:
|
||||
clk_disable_unprepare(ebi2xclk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id qcom_ebi2_of_match[] = {
|
||||
{ .compatible = "qcom,msm8660-ebi2", },
|
||||
{ .compatible = "qcom,apq8060-ebi2", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver qcom_ebi2_driver = {
|
||||
.probe = qcom_ebi2_probe,
|
||||
.driver = {
|
||||
.name = "qcom-ebi2",
|
||||
.of_match_table = qcom_ebi2_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(qcom_ebi2_driver);
|
||||
MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
|
||||
MODULE_DESCRIPTION("Qualcomm EBI2 driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@@ -15,24 +15,6 @@
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
static int tegra_aconnect_add_clock(struct device *dev, char *name)
|
||||
{
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
clk = clk_get(dev, name);
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(dev, "%s clock not found\n", name);
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
ret = pm_clk_add_clk(dev, clk);
|
||||
if (ret)
|
||||
clk_put(clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra_aconnect_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
@@ -44,11 +26,11 @@ static int tegra_aconnect_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = tegra_aconnect_add_clock(&pdev->dev, "ape");
|
||||
ret = of_pm_clk_add_clk(&pdev->dev, "ape");
|
||||
if (ret)
|
||||
goto clk_destroy;
|
||||
|
||||
ret = tegra_aconnect_add_clock(&pdev->dev, "apb2ape");
|
||||
ret = of_pm_clk_add_clk(&pdev->dev, "apb2ape");
|
||||
if (ret)
|
||||
goto clk_destroy;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user