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[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation

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Patch from Catalin Marinas

Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that
the completion of a TLB maintenance operation is only guaranteed by
the execution of a DSB (Data Syncronization Barrier, formerly Data
Write Barrier or Drain Write Buffer).

Note that a DSB is only needed in the flush_tlb_kernel_* functions
since the completion is guaranteed by a mode change (i.e. switching
back to user mode) for the flush_tlb_user_* functions.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas
2006-03-07 14:42:27 +00:00
committed by Russell King
parent d11d9b2dd2
commit 6a0e243069
3 changed files with 8 additions and 1 deletions
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arch/arm/Kconfig
+1 -1
View File
@@ -78,7 +78,7 @@ menu "System Type"
choice
prompt "ARM system type"
default ARCH_RPC
default ARCH_VERSATILE
config ARCH_CLPS7500
bool "Cirrus-CL-PS7500FE"
arch/arm/mm/tlb-v6.S
+1
View File
@@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range)
add r0, r0, #PAGE_SZ
cmp r0, r1
blo 1b
mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
mov pc, lr
.section ".text.init", #alloc, #execinstr