You've already forked linux-apfs
mirror of
https://github.com/linux-apfs/linux-apfs.git
synced 2026-05-01 15:00:59 -07:00
Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq code updates from Thomas Gleixner:
"The irq department proudly presents:
- Another tree wide sweep of irq infrastructure abuse. Clear winner
of the trainwreck engineering contest was:
#include "../../../kernel/irq/settings.h"
- Tree wide update of irq_set_affinity() callbacks which miss a cpu
online check when picking a single cpu out of the affinity mask.
- Tree wide consolidation of interrupt statistics.
- Updates to the threaded interrupt infrastructure to allow explicit
wakeup of the interrupt thread and a variant of synchronize_irq()
which synchronizes only the hard interrupt handler. Both are
needed to replace the homebrewn thread handling in the mmc/sdhci
code.
- New irq chip callbacks to allow proper support for GPIO based irqs.
The GPIO based interrupts need to request/release GPIO resources
from request/free_irq.
- A few new ARM interrupt chips. No revolutionary new hardware, just
differently wreckaged variations of the scheme.
- Small improvments, cleanups and updates all over the place"
I was hoping that that trainwreck engineering contest was a April Fools'
joke. But no.
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (68 commits)
irqchip: sun7i/sun6i: Disable NMI before registering the handler
ARM: sun7i/sun6i: dts: Fix IRQ number for sun6i NMI controller
ARM: sun7i/sun6i: irqchip: Update the documentation
ARM: sun7i/sun6i: dts: Add NMI irqchip support
ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller
genirq: Export symbol no_action()
arm: omap: Fix typo in ams-delta-fiq.c
m68k: atari: Fix the last kernel_stat.h fallout
irqchip: sun4i: Simplify sun4i_irq_ack
irqchip: sun4i: Use handle_fasteoi_irq for all interrupts
genirq: procfs: Make smp_affinity values go+r
softirq: Add linux/irq.h to make it compile again
m68k: amiga: Add linux/irq.h to make it compile again
irqchip: sun4i: Don't ack IRQs > 0, fix acking of IRQ 0
irqchip: sun4i: Fix a comment about mask register initialization
irqchip: sun4i: Fix irq 0 not working
genirq: Add a new IRQCHIP_EOI_THREADED flag
genirq: Document IRQCHIP_ONESHOT_SAFE flag
ARM: sunxi: dt: Convert to the new irq controller compatibles
irqchip: sunxi: Change compatibles
...
This commit is contained in:
@@ -1,4 +1,4 @@
|
||||
Marvell Armada 370 and Armada XP Interrupt Controller
|
||||
Marvell Armada 370, 375, 38x, XP Interrupt Controller
|
||||
-----------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
@@ -16,7 +16,13 @@ Required properties:
|
||||
automatically map to the interrupt controller registers of the
|
||||
current CPU)
|
||||
|
||||
Optional properties:
|
||||
|
||||
- interrupts: If defined, then it indicates that this MPIC is
|
||||
connected as a slave to another interrupt controller. This is
|
||||
typically the case on Armada 375 and Armada 38x, where the MPIC is
|
||||
connected as a slave to the Cortex-A9 GIC. The provided interrupt
|
||||
indicate to which GIC interrupt the MPIC output is connected.
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
@@ -2,7 +2,7 @@ Allwinner Sunxi Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sun4i-ic"
|
||||
- compatible : should be "allwinner,sun4i-a10-ic"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
@@ -11,7 +11,7 @@ Required properties:
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "allwinner,sun4i-ic";
|
||||
compatible = "allwinner,sun4i-a10-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@@ -0,0 +1,27 @@
|
||||
Allwinner Sunxi NMI Controller
|
||||
==============================
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
|
||||
"allwinner,sun6i-a31-sc-nmi"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 2. The first cell is the IRQ number, the
|
||||
second cell the trigger type as defined in interrupt.txt in this directory.
|
||||
- interrupt-parent: Specifies the parent interrupt controller.
|
||||
- interrupts: Specifies the interrupt line (NMI) which is handled by
|
||||
the interrupt controller in the parent controller's notation. This value
|
||||
shall be the NMI.
|
||||
|
||||
Example:
|
||||
|
||||
sc-nmi-intc@01c00030 {
|
||||
compatible = "allwinner,sun7i-a20-sc-nmi";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x01c00030 0x0c>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 0 4>;
|
||||
};
|
||||
@@ -331,7 +331,7 @@
|
||||
};
|
||||
|
||||
intc: interrupt-controller@01c20400 {
|
||||
compatible = "allwinner,sun4i-ic";
|
||||
compatible = "allwinner,sun4i-a10-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@@ -294,7 +294,7 @@
|
||||
};
|
||||
|
||||
intc: interrupt-controller@01c20400 {
|
||||
compatible = "allwinner,sun4i-ic";
|
||||
compatible = "allwinner,sun4i-a10-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@@ -275,7 +275,7 @@
|
||||
ranges;
|
||||
|
||||
intc: interrupt-controller@01c20400 {
|
||||
compatible = "allwinner,sun4i-ic";
|
||||
compatible = "allwinner,sun4i-a10-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@@ -190,6 +190,14 @@
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
nmi_intc: interrupt-controller@01f00c0c {
|
||||
compatible = "allwinner,sun6i-a31-sc-nmi";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x01f00c0c 0x38>;
|
||||
interrupts = <0 32 4>;
|
||||
};
|
||||
|
||||
pio: pinctrl@01c20800 {
|
||||
compatible = "allwinner,sun6i-a31-pinctrl";
|
||||
reg = <0x01c20800 0x400>;
|
||||
|
||||
@@ -339,6 +339,14 @@
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
nmi_intc: interrupt-controller@01c00030 {
|
||||
compatible = "allwinner,sun7i-a20-sc-nmi";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x01c00030 0x0c>;
|
||||
interrupts = <0 0 4>;
|
||||
};
|
||||
|
||||
emac: ethernet@01c0b000 {
|
||||
compatible = "allwinner,sun4i-a10-emac";
|
||||
reg = <0x01c0b000 0x1000>;
|
||||
|
||||
@@ -120,7 +120,7 @@ static void imx6q_enable_wb(bool enable)
|
||||
|
||||
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
|
||||
{
|
||||
struct irq_desc *iomuxc_irq_desc;
|
||||
struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
|
||||
u32 val = readl_relaxed(ccm_base + CLPCR);
|
||||
|
||||
val &= ~BM_CLPCR_LPM;
|
||||
@@ -167,10 +167,9 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
|
||||
* 3) Software should mask IRQ #32 right after CCM Low-Power mode
|
||||
* is set (set bits 0-1 of CCM_CLPCR).
|
||||
*/
|
||||
iomuxc_irq_desc = irq_to_desc(32);
|
||||
imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
|
||||
imx_gpc_irq_unmask(iomuxc_irq_data);
|
||||
writel_relaxed(val, ccm_base + CLPCR);
|
||||
imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data);
|
||||
imx_gpc_irq_mask(iomuxc_irq_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -27,22 +27,8 @@
|
||||
|
||||
int mmp2_set_wake(struct irq_data *d, unsigned int on)
|
||||
{
|
||||
int irq = d->irq;
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
unsigned long data = 0;
|
||||
|
||||
if (unlikely(irq >= nr_irqs)) {
|
||||
pr_err("IRQ nubmers are out of boundary!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (on) {
|
||||
if (desc->action)
|
||||
desc->action->flags |= IRQF_NO_SUSPEND;
|
||||
} else {
|
||||
if (desc->action)
|
||||
desc->action->flags &= ~IRQF_NO_SUSPEND;
|
||||
}
|
||||
int irq = d->irq;
|
||||
|
||||
/* enable wakeup sources */
|
||||
switch (irq) {
|
||||
|
||||
@@ -27,22 +27,8 @@
|
||||
|
||||
int pxa910_set_wake(struct irq_data *data, unsigned int on)
|
||||
{
|
||||
int irq = data->irq;
|
||||
struct irq_desc *desc = irq_to_desc(data->irq);
|
||||
uint32_t awucrm = 0, apcr = 0;
|
||||
|
||||
if (unlikely(irq >= nr_irqs)) {
|
||||
pr_err("IRQ nubmers are out of boundary!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (on) {
|
||||
if (desc->action)
|
||||
desc->action->flags |= IRQF_NO_SUSPEND;
|
||||
} else {
|
||||
if (desc->action)
|
||||
desc->action->flags &= ~IRQF_NO_SUSPEND;
|
||||
}
|
||||
int irq = data->irq;
|
||||
|
||||
/* setting wakeup sources */
|
||||
switch (irq) {
|
||||
@@ -115,10 +101,12 @@ int pxa910_set_wake(struct irq_data *data, unsigned int on)
|
||||
if (irq >= IRQ_GPIO_START && irq < IRQ_BOARD_START) {
|
||||
awucrm = MPMU_AWUCRM_WAKEUP(2);
|
||||
apcr |= MPMU_APCR_SLPWP2;
|
||||
} else
|
||||
} else {
|
||||
/* FIXME: This should return a proper error code ! */
|
||||
printk(KERN_ERR "Error: no defined wake up source irq: %d\n",
|
||||
irq);
|
||||
}
|
||||
}
|
||||
|
||||
if (on) {
|
||||
if (awucrm) {
|
||||
|
||||
@@ -44,13 +44,10 @@ static unsigned int irq_counter[16];
|
||||
|
||||
static irqreturn_t deferred_fiq(int irq, void *dev_id)
|
||||
{
|
||||
struct irq_desc *irq_desc;
|
||||
struct irq_chip *irq_chip = NULL;
|
||||
int gpio, irq_num, fiq_count;
|
||||
struct irq_chip *irq_chip;
|
||||
|
||||
irq_desc = irq_to_desc(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));
|
||||
if (irq_desc)
|
||||
irq_chip = irq_desc->irq_data.chip;
|
||||
irq_chip = irq_get_chip(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));
|
||||
|
||||
/*
|
||||
* For each handled GPIO interrupt, keep calling its interrupt handler
|
||||
|
||||
@@ -364,7 +364,6 @@ static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
|
||||
|
||||
static struct irqaction irq_move_irqaction = {
|
||||
.handler = smp_irq_move_cleanup_interrupt,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "irq_move"
|
||||
};
|
||||
|
||||
@@ -489,14 +488,13 @@ ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
|
||||
ia64_srlz_d();
|
||||
while (vector != IA64_SPURIOUS_INT_VECTOR) {
|
||||
int irq = local_vector_to_irq(vector);
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
|
||||
if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
|
||||
smp_local_flush_tlb();
|
||||
kstat_incr_irqs_this_cpu(irq, desc);
|
||||
kstat_incr_irq_this_cpu(irq);
|
||||
} else if (unlikely(IS_RESCHEDULE(vector))) {
|
||||
scheduler_ipi();
|
||||
kstat_incr_irqs_this_cpu(irq, desc);
|
||||
kstat_incr_irq_this_cpu(irq);
|
||||
} else {
|
||||
ia64_setreg(_IA64_REG_CR_TPR, vector);
|
||||
ia64_srlz_d();
|
||||
@@ -549,13 +547,12 @@ void ia64_process_pending_intr(void)
|
||||
*/
|
||||
while (vector != IA64_SPURIOUS_INT_VECTOR) {
|
||||
int irq = local_vector_to_irq(vector);
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
|
||||
if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
|
||||
smp_local_flush_tlb();
|
||||
kstat_incr_irqs_this_cpu(irq, desc);
|
||||
kstat_incr_irq_this_cpu(irq);
|
||||
} else if (unlikely(IS_RESCHEDULE(vector))) {
|
||||
kstat_incr_irqs_this_cpu(irq, desc);
|
||||
kstat_incr_irq_this_cpu(irq);
|
||||
} else {
|
||||
struct pt_regs *old_regs = set_irq_regs(NULL);
|
||||
|
||||
@@ -602,7 +599,6 @@ static irqreturn_t dummy_handler (int irq, void *dev_id)
|
||||
|
||||
static struct irqaction ipi_irqaction = {
|
||||
.handler = handle_IPI,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "IPI"
|
||||
};
|
||||
|
||||
@@ -611,13 +607,11 @@ static struct irqaction ipi_irqaction = {
|
||||
*/
|
||||
static struct irqaction resched_irqaction = {
|
||||
.handler = dummy_handler,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "resched"
|
||||
};
|
||||
|
||||
static struct irqaction tlb_irqaction = {
|
||||
.handler = dummy_handler,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "tlb_flush"
|
||||
};
|
||||
|
||||
|
||||
@@ -1772,38 +1772,32 @@ __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
|
||||
|
||||
static struct irqaction cmci_irqaction = {
|
||||
.handler = ia64_mca_cmc_int_handler,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "cmc_hndlr"
|
||||
};
|
||||
|
||||
static struct irqaction cmcp_irqaction = {
|
||||
.handler = ia64_mca_cmc_int_caller,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "cmc_poll"
|
||||
};
|
||||
|
||||
static struct irqaction mca_rdzv_irqaction = {
|
||||
.handler = ia64_mca_rendez_int_handler,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "mca_rdzv"
|
||||
};
|
||||
|
||||
static struct irqaction mca_wkup_irqaction = {
|
||||
.handler = ia64_mca_wakeup_int_handler,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "mca_wkup"
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static struct irqaction mca_cpe_irqaction = {
|
||||
.handler = ia64_mca_cpe_int_handler,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "cpe_hndlr"
|
||||
};
|
||||
|
||||
static struct irqaction mca_cpep_irqaction = {
|
||||
.handler = ia64_mca_cpe_int_caller,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "cpe_poll"
|
||||
};
|
||||
#endif /* CONFIG_ACPI */
|
||||
|
||||
@@ -17,12 +17,9 @@ static int ia64_set_msi_irq_affinity(struct irq_data *idata,
|
||||
{
|
||||
struct msi_msg msg;
|
||||
u32 addr, data;
|
||||
int cpu = first_cpu(*cpu_mask);
|
||||
int cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
|
||||
unsigned int irq = idata->irq;
|
||||
|
||||
if (!cpu_online(cpu))
|
||||
return -1;
|
||||
|
||||
if (irq_prepare_move(irq, cpu))
|
||||
return -1;
|
||||
|
||||
@@ -139,10 +136,7 @@ static int dmar_msi_set_affinity(struct irq_data *data,
|
||||
unsigned int irq = data->irq;
|
||||
struct irq_cfg *cfg = irq_cfg + irq;
|
||||
struct msi_msg msg;
|
||||
int cpu = cpumask_first(mask);
|
||||
|
||||
if (!cpu_online(cpu))
|
||||
return -1;
|
||||
int cpu = cpumask_first_and(mask, cpu_online_mask);
|
||||
|
||||
if (irq_prepare_move(irq, cpu))
|
||||
return -1;
|
||||
|
||||
@@ -6387,7 +6387,6 @@ pfm_flush_pmds(struct task_struct *task, pfm_context_t *ctx)
|
||||
|
||||
static struct irqaction perfmon_irqaction = {
|
||||
.handler = pfm_interrupt_handler,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "perfmon"
|
||||
};
|
||||
|
||||
|
||||
@@ -380,7 +380,7 @@ static cycle_t itc_get_cycles(struct clocksource *cs)
|
||||
|
||||
static struct irqaction timer_irqaction = {
|
||||
.handler = timer_interrupt,
|
||||
.flags = IRQF_DISABLED | IRQF_IRQPOLL,
|
||||
.flags = IRQF_IRQPOLL,
|
||||
.name = "timer"
|
||||
};
|
||||
|
||||
|
||||
@@ -209,8 +209,8 @@ static int sn_set_affinity_irq(struct irq_data *data,
|
||||
nasid_t nasid;
|
||||
int slice;
|
||||
|
||||
nasid = cpuid_to_nasid(cpumask_first(mask));
|
||||
slice = cpuid_to_slice(cpumask_first(mask));
|
||||
nasid = cpuid_to_nasid(cpumask_first_and(mask, cpu_online_mask));
|
||||
slice = cpuid_to_slice(cpumask_first_and(mask, cpu_online_mask));
|
||||
|
||||
list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
|
||||
sn_irq_lh[irq], list)
|
||||
|
||||
@@ -166,7 +166,7 @@ static int sn_set_msi_irq_affinity(struct irq_data *data,
|
||||
struct sn_pcibus_provider *provider;
|
||||
unsigned int cpu, irq = data->irq;
|
||||
|
||||
cpu = cpumask_first(cpu_mask);
|
||||
cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
|
||||
sn_irq_info = sn_msi_info[irq].sn_irq_info;
|
||||
if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0)
|
||||
return -1;
|
||||
|
||||
@@ -18,6 +18,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/amigahw.h>
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user