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[XTENSA] Add support for cache-aliasing
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Chris Zankel
@@ -19,6 +19,15 @@
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#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
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#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
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#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
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#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
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/* Maximum cache size per way. */
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#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
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# define CACHE_WAY_SIZE DCACHE_WAY_SIZE
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#else
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# define CACHE_WAY_SIZE ICACHE_WAY_SIZE
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#endif
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#endif /* _XTENSA_CACHE_H */
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@@ -5,7 +5,7 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* (C) 2001 - 2006 Tensilica Inc.
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* (C) 2001 - 2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_CACHEFLUSH_H
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@@ -18,10 +18,7 @@
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#include <asm/page.h>
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/*
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* flush and invalidate data cache, invalidate instruction cache:
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*
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* __flush_invalidate_cache_all()
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* __flush_invalidate_cache_range(from,sze)
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* Lo-level routines for cache flushing.
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*
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* invalidate data or instruction cache:
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*
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@@ -40,26 +37,39 @@
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* __flush_invalidate_dcache_all()
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* __flush_invalidate_dcache_page(adr)
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* __flush_invalidate_dcache_range(from,size)
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*
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* specials for cache aliasing:
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*
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* __flush_invalidate_dcache_page_alias(vaddr,paddr)
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* __invalidate_icache_page_alias(vaddr,paddr)
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*/
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extern void __flush_invalidate_cache_all(void);
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extern void __flush_invalidate_cache_range(unsigned long, unsigned long);
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extern void __flush_invalidate_dcache_all(void);
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extern void __invalidate_dcache_all(void);
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extern void __invalidate_icache_all(void);
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extern void __invalidate_dcache_page(unsigned long);
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extern void __invalidate_icache_page(unsigned long);
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extern void __invalidate_icache_range(unsigned long, unsigned long);
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extern void __invalidate_dcache_range(unsigned long, unsigned long);
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#if XCHAL_DCACHE_IS_WRITEBACK
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extern void __flush_invalidate_dcache_all(void);
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extern void __flush_dcache_page(unsigned long);
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extern void __flush_dcache_range(unsigned long, unsigned long);
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extern void __flush_invalidate_dcache_page(unsigned long);
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extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
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#else
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# define __flush_dcache_page(p) do { } while(0)
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# define __flush_invalidate_dcache_page(p) do { } while(0)
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# define __flush_invalidate_dcache_range(p,s) do { } while(0)
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# define __flush_dcache_range(p,s) do { } while(0)
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# define __flush_dcache_page(p) do { } while(0)
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# define __flush_invalidate_dcache_page(p) __invalidate_dcache_page(p)
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# define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s)
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#endif
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
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#endif
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#if (ICACHE_WAY_SIZE > PAGE_SIZE)
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extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
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#endif
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/*
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@@ -71,17 +81,21 @@ extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
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* (see also Documentation/cachetlb.txt)
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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#define flush_cache_all() __flush_invalidate_cache_all();
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#define flush_cache_mm(mm) __flush_invalidate_cache_all();
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#define flush_cache_dup_mm(mm) __flush_invalidate_cache_all();
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#define flush_cache_all() \
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do { \
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__flush_invalidate_dcache_all(); \
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__invalidate_icache_all(); \
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} while (0)
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#define flush_cache_vmap(start,end) __flush_invalidate_cache_all();
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#define flush_cache_vunmap(start,end) __flush_invalidate_cache_all();
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#define flush_cache_mm(mm) flush_cache_all()
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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#define flush_cache_vmap(start,end) flush_cache_all()
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#define flush_cache_vunmap(start,end) flush_cache_all()
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extern void flush_dcache_page(struct page*);
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extern void flush_cache_range(struct vm_area_struct*, ulong, ulong);
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extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned long);
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@@ -101,24 +115,39 @@ extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned lon
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#endif
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/* Ensure consistency between data and instruction cache. */
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#define flush_icache_range(start,end) \
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__invalidate_icache_range(start,(end)-(start))
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do { \
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__flush_dcache_range(start, (end) - (start)); \
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__invalidate_icache_range(start,(end) - (start)); \
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} while (0)
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/* This is not required, see Documentation/cachetlb.txt */
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#define flush_icache_page(vma,page) do { } while(0)
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#define flush_icache_page(vma,page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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extern void copy_to_user_page(struct vm_area_struct*, struct page*,
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unsigned long, void*, const void*, unsigned long);
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extern void copy_from_user_page(struct vm_area_struct*, struct page*,
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unsigned long, void*, const void*, unsigned long);
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#else
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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__flush_dcache_range((unsigned long) dst, len); \
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__invalidate_icache_range((unsigned long) dst, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_CACHEFLUSH_H */
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@@ -14,6 +14,7 @@
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#ifdef __KERNEL__
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#include <asm/byteorder.h>
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#include <asm/page.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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@@ -15,6 +15,7 @@
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#include <asm/processor.h>
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#include <asm/types.h>
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#include <asm/cache.h>
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/*
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* Fixed TLB translations in the processor.
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@@ -39,6 +40,53 @@
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#define MAX_MEM_PFN XCHAL_KSEG_SIZE
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#define PGTABLE_START 0x80000000
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/*
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* Cache aliasing:
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*
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* If the cache size for one way is greater than the page size, we have to
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* deal with cache aliasing. The cache index is wider than the page size:
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*
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* | |cache| cache index
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* | pfn |off| virtual address
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* |xxxx:X|zzz|
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* | : | |
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* | \ / | |
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* |trans.| |
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* | / \ | |
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* |yyyy:Y|zzz| physical address
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*
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* When the page number is translated to the physical page address, the lowest
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* bit(s) (X) that are part of the cache index are also translated (Y).
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* If this translation changes bit(s) (X), the cache index is also afected,
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* thus resulting in a different cache line than before.
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* The kernel does not provide a mechanism to ensure that the page color
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* (represented by this bit) remains the same when allocated or when pages
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* are remapped. When user pages are mapped into kernel space, the color of
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* the page might also change.
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*
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* We use the address space VMALLOC_END ... VMALLOC_END + DCACHE_WAY_SIZE * 2
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* to temporarily map a patch so we can match the color.
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*/
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#if DCACHE_WAY_SIZE > PAGE_SIZE
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# define DCACHE_ALIAS_ORDER (DCACHE_WAY_SHIFT - PAGE_SHIFT)
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# define DCACHE_ALIAS_MASK (PAGE_MASK & (DCACHE_WAY_SIZE - 1))
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# define DCACHE_ALIAS(a) (((a) & DCACHE_ALIAS_MASK) >> PAGE_SHIFT)
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# define DCACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & DCACHE_ALIAS_MASK) == 0)
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#else
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# define DCACHE_ALIAS_ORDER 0
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#endif
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#if ICACHE_WAY_SIZE > PAGE_SIZE
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# define ICACHE_ALIAS_ORDER (ICACHE_WAY_SHIFT - PAGE_SHIFT)
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# define ICACHE_ALIAS_MASK (PAGE_MASK & (ICACHE_WAY_SIZE - 1))
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# define ICACHE_ALIAS(a) (((a) & ICACHE_ALIAS_MASK) >> PAGE_SHIFT)
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# define ICACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & ICACHE_ALIAS_MASK) == 0)
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#else
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# define ICACHE_ALIAS_ORDER 0
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#endif
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#ifdef __ASSEMBLY__
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#define __pgprot(x) (x)
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@@ -90,11 +138,11 @@ extern void copy_page(void *to, void *from);
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* some extra work
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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void clear_user_page(void *addr, unsigned long vaddr, struct page* page);
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void copy_user_page(void *to,void* from,unsigned long vaddr,struct page* page);
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#if DCACHE_WAY_SIZE > PAGE_SIZE
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extern void clear_user_page(void*, unsigned long, struct page*);
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extern void copy_user_page(void*, void*, unsigned long, struct page*);
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#else
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# define clear_user_page(page,vaddr,pg) clear_page(page)
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# define clear_user_page(page, vaddr, pg) clear_page(page)
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# define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
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#endif
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@@ -1,11 +1,11 @@
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/*
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* linux/include/asm-xtensa/pgalloc.h
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* include/asm-xtensa/pgalloc.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Copyright (C) 2001-2005 Tensilica Inc.
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* Copyright (C) 2001-2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_PGALLOC_H
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@@ -13,103 +13,54 @@
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#ifdef __KERNEL__
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#include <linux/threads.h>
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#include <linux/highmem.h>
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#include <asm/processor.h>
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#include <asm/cacheflush.h>
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/* Cache aliasing:
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*
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* If the cache size for one way is greater than the page size, we have to
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* deal with cache aliasing. The cache index is wider than the page size:
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*
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* |cache |
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* |pgnum |page| virtual address
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* |xxxxxX|zzzz|
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* | | |
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* \ / | |
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* trans.| |
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* / \ | |
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* |yyyyyY|zzzz| physical address
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*
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* When the page number is translated to the physical page address, the lowest
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* bit(s) (X) that are also part of the cache index are also translated (Y).
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* If this translation changes this bit (X), the cache index is also afected,
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* thus resulting in a different cache line than before.
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* The kernel does not provide a mechanism to ensure that the page color
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* (represented by this bit) remains the same when allocated or when pages
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* are remapped. When user pages are mapped into kernel space, the color of
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* the page might also change.
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*
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* We use the address space VMALLOC_END ... VMALLOC_END + DCACHE_WAY_SIZE * 2
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* to temporarily map a patch so we can match the color.
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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# define PAGE_COLOR_MASK (PAGE_MASK & (DCACHE_WAY_SIZE-1))
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# define PAGE_COLOR(a) \
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(((unsigned long)(a)&PAGE_COLOR_MASK) >> PAGE_SHIFT)
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# define PAGE_COLOR_EQ(a,b) \
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((((unsigned long)(a) ^ (unsigned long)(b)) & PAGE_COLOR_MASK) == 0)
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# define PAGE_COLOR_MAP0(v) \
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(VMALLOC_END + ((unsigned long)(v) & PAGE_COLOR_MASK))
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# define PAGE_COLOR_MAP1(v) \
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(VMALLOC_END + ((unsigned long)(v) & PAGE_COLOR_MASK) + DCACHE_WAY_SIZE)
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#endif
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/*
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* Allocating and freeing a pmd is trivial: the 1-entry pmd is
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* inside the pgd, so has no extra memory associated with it.
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*/
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#define pgd_free(pgd) free_page((unsigned long)(pgd))
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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static inline void
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pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *pte)
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{
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pmd_val(*(pmdp)) = (unsigned long)(pte);
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__asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
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}
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static inline void
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pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *page)
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{
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pmd_val(*(pmdp)) = (unsigned long)page_to_virt(page);
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__asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
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}
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#else
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# define pmd_populate_kernel(mm, pmdp, pte) \
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(pmd_val(*(pmdp)) = (unsigned long)(pte))
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# define pmd_populate(mm, pmdp, page) \
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(pmd_val(*(pmdp)) = (unsigned long)page_to_virt(page))
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#endif
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#define pmd_populate_kernel(mm, pmdp, ptep) \
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(pmd_val(*(pmdp)) = ((unsigned long)ptep))
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#define pmd_populate(mm, pmdp, page) \
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(pmd_val(*(pmdp)) = ((unsigned long)page_to_virt(page)))
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static inline pgd_t*
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pgd_alloc(struct mm_struct *mm)
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{
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pgd_t *pgd;
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pgd = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, PGD_ORDER);
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if (likely(pgd != NULL))
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__flush_dcache_page((unsigned long)pgd);
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return pgd;
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return (pgd_t*) __get_free_pages(GFP_KERNEL | __GFP_ZERO, PGD_ORDER);
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}
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extern pte_t* pte_alloc_one_kernel(struct mm_struct* mm, unsigned long addr);
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extern struct page* pte_alloc_one(struct mm_struct* mm, unsigned long addr);
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static inline void pgd_free(pgd_t *pgd)
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{
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free_page((unsigned long)pgd);
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}
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#define pte_free_kernel(pte) free_page((unsigned long)pte)
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#define pte_free(pte) __free_page(pte)
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/* Use a slab cache for the pte pages (see also sparc64 implementation) */
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extern struct kmem_cache *pgtable_cache;
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static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
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unsigned long address)
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{
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return kmem_cache_alloc(pgtable_cache, GFP_KERNEL|__GFP_REPEAT);
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}
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static inline struct page *pte_alloc_one(struct mm_struct *mm,
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unsigned long addr)
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{
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return virt_to_page(pte_alloc_one_kernel(mm, addr));
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}
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static inline void pte_free_kernel(pte_t *pte)
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{
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kmem_cache_free(pgtable_cache, pte);
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}
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static inline void pte_free(struct page *page)
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{
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kmem_cache_free(pgtable_cache, page_address(page));
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}
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_PGALLOC_H */
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@@ -1,5 +1,5 @@
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/*
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* linux/include/asm-xtensa/pgtable.h
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* include/asm-xtensa/pgtable.h
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
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@@ -60,16 +60,20 @@
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#define FIRST_USER_ADDRESS 0
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#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
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/* virtual memory area. We keep a distance to other memory regions to be
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/*
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* Virtual memory area. We keep a distance to other memory regions to be
|
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* on the safe side. We also use this area for cache aliasing.
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||||
*/
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// FIXME: virtual memory area must be configuration-dependent
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#define VMALLOC_START 0xC0000000
|
||||
#define VMALLOC_END 0xC7FF0000
|
||||
#define VMALLOC_END 0xC6FEFFFF
|
||||
#define TLBTEMP_BASE_1 0xC6FF0000
|
||||
#define TLBTEMP_BASE_2 0xC6FF8000
|
||||
#define MODULE_START 0xC7000000
|
||||
#define MODULE_END 0xC7FFFFFF
|
||||
|
||||
/* Xtensa Linux config PTE layout (when present):
|
||||
/*
|
||||
* Xtensa Linux config PTE layout (when present):
|
||||
* 31-12: PPN
|
||||
* 11-6: Software
|
||||
* 5-4: RING
|
||||
@@ -126,12 +130,13 @@
|
||||
#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
|
||||
#define PAGE_SHARED_EXEC \
|
||||
__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
|
||||
#define PAGE_KERNEL __pgprot(_PAGE_PRESENT)
|
||||
#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
|
||||
#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
|
||||
|
||||
#if (DCACHE_WAY_SIZE > PAGE_SIZE)
|
||||
# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_HW_WRITE)
|
||||
# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED)
|
||||
#else
|
||||
# define _PAGE_DIRECTORY (_PAGE_VALID|_PAGE_ACCESSED|_PAGE_HW_WRITE|_PAGE_CA_WB)
|
||||
# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
|
||||
#endif
|
||||
|
||||
#else /* no mmu */
|
||||
@@ -244,6 +249,10 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||||
static inline void update_pte(pte_t *ptep, pte_t pteval)
|
||||
{
|
||||
*ptep = pteval;
|
||||
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
|
||||
__asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
struct mm_struct;
|
||||
@@ -383,13 +392,12 @@ extern void update_mmu_cache(struct vm_area_struct * vma,
|
||||
* remap a physical page `pfn' of size `size' with page protection `prot'
|
||||
* into virtual address `from'
|
||||
*/
|
||||
|
||||
#define io_remap_pfn_range(vma,from,pfn,size,prot) \
|
||||
remap_pfn_range(vma, from, pfn, size, prot)
|
||||
|
||||
|
||||
/* No page table caches to init */
|
||||
|
||||
#define pgtable_cache_init() do { } while (0)
|
||||
extern void pgtable_cache_init(void);
|
||||
|
||||
typedef pte_t *pte_addr_t;
|
||||
|
||||
|
||||
@@ -11,14 +11,36 @@
|
||||
#ifndef _XTENSA_TLB_H
|
||||
#define _XTENSA_TLB_H
|
||||
|
||||
#define tlb_start_vma(tlb,vma) do { } while (0)
|
||||
#define tlb_end_vma(tlb,vma) do { } while (0)
|
||||
#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
|
||||
#include <asm/cache.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
#if (DCACHE_WAY_SIZE <= PAGE_SIZE)
|
||||
|
||||
/* Note, read http://lkml.org/lkml/2004/1/15/6 */
|
||||
|
||||
# define tlb_start_vma(tlb,vma) do { } while (0)
|
||||
# define tlb_end_vma(tlb,vma) do { } while (0)
|
||||
|
||||
#else
|
||||
|
||||
# define tlb_start_vma(tlb, vma) \
|
||||
do { \
|
||||
if (!tlb->fullmm) \
|
||||
flush_cache_range(vma, vma->vm_start, vma->vm_end); \
|
||||
} while(0)
|
||||
|
||||
# define tlb_end_vma(tlb, vma) \
|
||||
do { \
|
||||
if (!tlb->fullmm) \
|
||||
flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
|
||||
} while(0)
|
||||
|
||||
#endif
|
||||
|
||||
#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
|
||||
#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
|
||||
|
||||
#include <asm-generic/tlb.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
#define __pte_free_tlb(tlb,pte) pte_free(pte)
|
||||
|
||||
|
||||
Reference in New Issue
Block a user