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Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits) [ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 ports [ARM] 4140/1: AACI stability add ac97 timeout and retries [ARM] 4139/1: AACI record support [ARM] 4138/1: AACI: multiple channel support for IRQ handling [ARM] 4211/1: Provide a defconfig for ns9xxx [ARM] 4210/1: base for new machine type "NetSilicon NS9360" [ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM [ARM] 4221/1: S3C2443: DMA support [ARM] 4220/1: S3C24XX: DMA system initialised from sysdev [ARM] 4219/1: S3C2443: DMA source definitions [ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443 [ARM] 4217/1: S3C24XX: remove the dma channel show at startup [ARM] 4090/2: avoid clash between PXA and SA1111 defines [ARM] 4216/1: add .gitignore entries for ARM specific files [ARM] 4214/2: S3C2410: Add Armzone QT2410 [ARM] 4215/1: s3c2410 usb device: per-platform vbus_draw [ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST [ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos [ARM] 4137/1: Add kexec support [ARM] 4201/1: SMP barriers pair needed for the secondary boot process ... Fix up conflict due to typedef removal in sound/arm/aaci.h
This commit is contained in:
Linus Torvalds
@@ -1,6 +1,8 @@
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#ifndef ASMARM_HARDWARE_ARM_SCU_H
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#define ASMARM_HARDWARE_ARM_SCU_H
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#include <asm/arch/scu.h>
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/*
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* SCU registers
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*/
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@@ -0,0 +1,56 @@
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/*
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* include/asm-arm/hardware/cache-l2x0.h
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*
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* Copyright (C) 2007 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_HARDWARE_L2X0_H
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#define __ASM_ARM_HARDWARE_L2X0_H
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#define L2X0_CACHE_ID 0x000
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#define L2X0_CACHE_TYPE 0x004
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#define L2X0_CTRL 0x100
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#define L2X0_AUX_CTRL 0x104
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#define L2X0_EVENT_CNT_CTRL 0x200
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#define L2X0_EVENT_CNT1_CFG 0x204
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#define L2X0_EVENT_CNT0_CFG 0x208
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#define L2X0_EVENT_CNT1_VAL 0x20C
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#define L2X0_EVENT_CNT0_VAL 0x210
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#define L2X0_INTR_MASK 0x214
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#define L2X0_MASKED_INTR_STAT 0x218
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#define L2X0_RAW_INTR_STAT 0x21C
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#define L2X0_INTR_CLEAR 0x220
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#define L2X0_CACHE_SYNC 0x730
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#define L2X0_INV_LINE_PA 0x770
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#define L2X0_INV_WAY 0x77C
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#define L2X0_CLEAN_LINE_PA 0x7B0
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#define L2X0_CLEAN_LINE_IDX 0x7B8
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#define L2X0_CLEAN_WAY 0x7BC
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#define L2X0_CLEAN_INV_LINE_PA 0x7F0
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#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
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#define L2X0_CLEAN_INV_WAY 0x7FC
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#define L2X0_LOCKDOWN_WAY_D 0x900
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#define L2X0_LOCKDOWN_WAY_I 0x904
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#define L2X0_TEST_OPERATION 0xF00
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#define L2X0_LINE_DATA 0xF10
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#define L2X0_LINE_TAG 0xF30
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#define L2X0_DEBUG_CTRL 0xF40
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#ifndef __ASSEMBLY__
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extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
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#endif
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#endif
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@@ -33,8 +33,9 @@
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#define GIC_DIST_SOFTINT 0xf00
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#ifndef __ASSEMBLY__
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void gic_dist_init(void __iomem *base);
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void gic_cpu_init(void __iomem *base);
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void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start);
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void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
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void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
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void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
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#endif
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@@ -37,6 +37,13 @@ extern void gpio_line_set(int line, int value);
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#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
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#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
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#define IOP3XX_PERIPHERAL_SIZE 0x00002000
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#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
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IOP3XX_PERIPHERAL_SIZE - 1)
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#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
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IOP3XX_PERIPHERAL_SIZE - 1)
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#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
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(IOP3XX_PERIPHERAL_PHYS_BASE\
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- IOP3XX_PERIPHERAL_VIRT_BASE))
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#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
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/* Address Translation Unit */
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@@ -258,12 +265,20 @@ extern void gpio_line_set(int line, int value);
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#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
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#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
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#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR)
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#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\
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IOP3XX_PCI_IO_WINDOW_SIZE - 1)
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#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\
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IOP3XX_PCI_IO_WINDOW_SIZE - 1)
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#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) addr -\
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IOP3XX_PCI_LOWER_IO_PA) +\
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IOP3XX_PCI_LOWER_IO_VA)
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#ifndef __ASSEMBLY__
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void iop3xx_map_io(void);
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void iop3xx_init_time(unsigned long);
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unsigned long iop3xx_gettimeoffset(void);
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void iop_init_cp6_handler(void);
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extern struct platform_device iop3xx_i2c0_device;
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extern struct platform_device iop3xx_i2c1_device;
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@@ -29,6 +29,9 @@
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#define _SA1111(x) ((x) + sa1111->resource.start)
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#endif
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#define sa1111_writel(val,addr) __raw_writel(val, addr)
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#define sa1111_readl(addr) __raw_readl(addr)
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/*
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* 26 bits of the SA-1110 address bus are available to the SA-1111.
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* Use these when feeding target addresses to the DMA engines.
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@@ -44,14 +47,6 @@
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#define SA1111_SAC_DMA_MIN_XFER (0x800)
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/*
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* SA1111 register definitions.
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*/
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#define __CCREG(x) __REGP(SA1111_VBASE + (x))
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#define sa1111_writel(val,addr) __raw_writel(val, addr)
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#define sa1111_readl(addr) __raw_readl(addr)
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/*
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* System Bus Interface (SBI)
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*
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@@ -194,55 +189,37 @@
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* SADR Serial Audio Data Register (16 x 32-bit)
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*/
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#define _SACR0 _SA1111( 0x0600 )
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#define _SACR1 _SA1111( 0x0604 )
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#define _SACR2 _SA1111( 0x0608 )
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#define _SASR0 _SA1111( 0x060c )
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#define _SASR1 _SA1111( 0x0610 )
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#define _SASCR _SA1111( 0x0618 )
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#define _L3_CAR _SA1111( 0x061c )
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#define _L3_CDR _SA1111( 0x0620 )
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#define _ACCAR _SA1111( 0x0624 )
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#define _ACCDR _SA1111( 0x0628 )
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#define _ACSAR _SA1111( 0x062c )
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#define _ACSDR _SA1111( 0x0630 )
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#define _SADTCS _SA1111( 0x0634 )
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#define _SADTSA _SA1111( 0x0638 )
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#define _SADTCA _SA1111( 0x063c )
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#define _SADTSB _SA1111( 0x0640 )
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#define _SADTCB _SA1111( 0x0644 )
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#define _SADRCS _SA1111( 0x0648 )
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#define _SADRSA _SA1111( 0x064c )
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#define _SADRCA _SA1111( 0x0650 )
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#define _SADRSB _SA1111( 0x0654 )
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#define _SADRCB _SA1111( 0x0658 )
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#define _SAITR _SA1111( 0x065c )
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#define _SADR _SA1111( 0x0680 )
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#define SA1111_SERAUDIO 0x0600
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#define SACR0 __CCREG(0x0600)
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#define SACR1 __CCREG(0x0604)
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#define SACR2 __CCREG(0x0608)
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#define SASR0 __CCREG(0x060c)
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#define SASR1 __CCREG(0x0610)
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#define SASCR __CCREG(0x0618)
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#define L3_CAR __CCREG(0x061c)
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#define L3_CDR __CCREG(0x0620)
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#define ACCAR __CCREG(0x0624)
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#define ACCDR __CCREG(0x0628)
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#define ACSAR __CCREG(0x062c)
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#define ACSDR __CCREG(0x0630)
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#define SADTCS __CCREG(0x0634)
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#define SADTSA __CCREG(0x0638)
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#define SADTCA __CCREG(0x063c)
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#define SADTSB __CCREG(0x0640)
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#define SADTCB __CCREG(0x0644)
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#define SADRCS __CCREG(0x0648)
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#define SADRSA __CCREG(0x064c)
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#define SADRCA __CCREG(0x0650)
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#define SADRSB __CCREG(0x0654)
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#define SADRCB __CCREG(0x0658)
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#define SAITR __CCREG(0x065c)
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#define SADR __CCREG(0x0680)
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/*
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* These are offsets from the above base.
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*/
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#define SA1111_SACR0 0x00
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#define SA1111_SACR1 0x04
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#define SA1111_SACR2 0x08
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#define SA1111_SASR0 0x0c
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#define SA1111_SASR1 0x10
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#define SA1111_SASCR 0x18
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#define SA1111_L3_CAR 0x1c
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#define SA1111_L3_CDR 0x20
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#define SA1111_ACCAR 0x24
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#define SA1111_ACCDR 0x28
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#define SA1111_ACSAR 0x2c
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#define SA1111_ACSDR 0x30
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#define SA1111_SADTCS 0x34
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#define SA1111_SADTSA 0x38
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#define SA1111_SADTCA 0x3c
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#define SA1111_SADTSB 0x40
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#define SA1111_SADTCB 0x44
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#define SA1111_SADRCS 0x48
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#define SA1111_SADRSA 0x4c
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#define SA1111_SADRCA 0x50
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#define SA1111_SADRSB 0x54
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#define SA1111_SADRCB 0x58
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#define SA1111_SAITR 0x5c
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#define SA1111_SADR 0x80
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#ifndef CONFIG_ARCH_PXA
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#define SACR0_ENB (1<<0)
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#define SACR0_BCKD (1<<2)
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@@ -330,6 +307,8 @@
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#define SAITR_RDBDA (1<<10)
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#define SAITR_RDBDB (1<<11)
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#endif /* !CONFIG_ARCH_PXA */
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/*
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* General-Purpose I/O Interface
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*
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