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Merge tag 'iommu-updates-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel: - support for interrupt virtualization in the AMD IOMMU driver. These patches were shared with the KVM tree and are already merged through that tree. - generic DT-binding support for the ARM-SMMU driver. With this the driver now makes use of the generic DMA-API code. This also required some changes outside of the IOMMU code, but these are acked by the respective maintainers. - more cleanups and fixes all over the place. * tag 'iommu-updates-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (40 commits) iommu/amd: No need to wait iommu completion if no dte irq entry change iommu/amd: Free domain id when free a domain of struct dma_ops_domain iommu/amd: Use standard bitmap operation to set bitmap iommu/amd: Clean up the cmpxchg64 invocation iommu/io-pgtable-arm: Check for v7s-incapable systems iommu/dma: Avoid PCI host bridge windows iommu/dma: Add support for mapping MSIs iommu/arm-smmu: Set domain geometry iommu/arm-smmu: Wire up generic configuration support Docs: dt: document ARM SMMU generic binding usage iommu/arm-smmu: Convert to iommu_fwspec iommu/arm-smmu: Intelligent SMR allocation iommu/arm-smmu: Add a stream map entry iterator iommu/arm-smmu: Streamline SMMU data lookups iommu/arm-smmu: Refactor mmu-masters handling iommu/arm-smmu: Keep track of S2CR state iommu/arm-smmu: Consolidate stream map entry state iommu/arm-smmu: Handle stream IDs more dynamically iommu/arm-smmu: Set PRIVCFG in stage 1 STEs iommu/arm-smmu: Support non-PCI devices with SMMUv3 ...
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Linus Torvalds
@@ -27,6 +27,12 @@ the PCIe specification.
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* "cmdq-sync" - CMD_SYNC complete
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* "gerror" - Global Error activated
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- #iommu-cells : See the generic IOMMU binding described in
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devicetree/bindings/pci/pci-iommu.txt
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for details. For SMMUv3, must be 1, with each cell
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describing a single stream ID. All possible stream
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IDs which a device may emit must be described.
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** SMMUv3 optional properties:
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- dma-coherent : Present if DMA operations made by the SMMU (page
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@@ -54,6 +60,6 @@ the PCIe specification.
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<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
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dma-coherent;
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#iommu-cells = <0>;
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#iommu-cells = <1>;
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msi-parent = <&its 0xff0000>;
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};
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@@ -35,12 +35,16 @@ conditions.
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interrupt per context bank. In the case of a single,
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combined interrupt, it must be listed multiple times.
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- mmu-masters : A list of phandles to device nodes representing bus
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masters for which the SMMU can provide a translation
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and their corresponding StreamIDs (see example below).
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Each device node linked from this list must have a
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"#stream-id-cells" property, indicating the number of
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StreamIDs associated with it.
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- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
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for details. With a value of 1, each "iommus" entry
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represents a distinct stream ID emitted by that device
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into the relevant SMMU.
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SMMUs with stream matching support and complex masters
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may use a value of 2, where the second cell represents
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an SMR mask to combine with the ID in the first cell.
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Care must be taken to ensure the set of matched IDs
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does not result in conflicts.
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** System MMU optional properties:
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@@ -56,9 +60,20 @@ conditions.
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aliases of secure registers have to be used during
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SMMU configuration.
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Example:
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** Deprecated properties:
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smmu {
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- mmu-masters (deprecated in favour of the generic "iommus" binding) :
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A list of phandles to device nodes representing bus
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masters for which the SMMU can provide a translation
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and their corresponding Stream IDs. Each device node
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linked from this list must have a "#stream-id-cells"
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property, indicating the number of Stream ID
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arguments associated with its phandle.
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** Examples:
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/* SMMU with stream matching or stream indexing */
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smmu1: iommu {
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compatible = "arm,smmu-v1";
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reg = <0xba5e0000 0x10000>;
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#global-interrupts = <2>;
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@@ -68,11 +83,29 @@ Example:
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<0 35 4>,
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<0 36 4>,
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<0 37 4>;
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#iommu-cells = <1>;
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};
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/*
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* Two DMA controllers, the first with two StreamIDs (0xd01d
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* and 0xd01e) and the second with only one (0xd11c).
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*/
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mmu-masters = <&dma0 0xd01d 0xd01e>,
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<&dma1 0xd11c>;
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/* device with two stream IDs, 0 and 7 */
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master1 {
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iommus = <&smmu1 0>,
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<&smmu1 7>;
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};
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/* SMMU with stream matching */
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smmu2: iommu {
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...
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#iommu-cells = <2>;
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};
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/* device with stream IDs 0 and 7 */
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master2 {
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iommus = <&smmu2 0 0>,
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<&smmu2 7 0>;
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};
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/* device with stream IDs 1, 17, 33 and 49 */
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master3 {
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iommus = <&smmu2 1 0x30>;
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};
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@@ -0,0 +1,171 @@
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This document describes the generic device tree binding for describing the
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relationship between PCI(e) devices and IOMMU(s).
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Each PCI(e) device under a root complex is uniquely identified by its Requester
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ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
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Function number.
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For the purpose of this document, when treated as a numeric value, a RID is
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formatted such that:
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* Bits [15:8] are the Bus number.
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* Bits [7:3] are the Device number.
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* Bits [2:0] are the Function number.
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* Any other bits required for padding must be zero.
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IOMMUs may distinguish PCI devices through sideband data derived from the
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Requester ID. While a given PCI device can only master through one IOMMU, a
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root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
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bus).
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The generic 'iommus' property is insufficient to describe this relationship,
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and a mechanism is required to map from a PCI device to its IOMMU and sideband
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data.
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For generic IOMMU bindings, see
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Documentation/devicetree/bindings/iommu/iommu.txt.
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PCI root complex
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================
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Optional properties
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-------------------
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- iommu-map: Maps a Requester ID to an IOMMU and associated iommu-specifier
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data.
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The property is an arbitrary number of tuples of
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(rid-base,iommu,iommu-base,length).
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Any RID r in the interval [rid-base, rid-base + length) is associated with
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the listed IOMMU, with the iommu-specifier (r - rid-base + iommu-base).
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- iommu-map-mask: A mask to be applied to each Requester ID prior to being
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mapped to an iommu-specifier per the iommu-map property.
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Example (1)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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iommu: iommu@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to the IOMMU is the RID,
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* identity-mapped.
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*/
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iommu-map = <0x0 &iommu 0x0 0x10000>;
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};
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};
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Example (2)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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iommu: iommu@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to the IOMMU is the RID with the
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* function bits masked out.
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*/
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iommu-map = <0x0 &iommu 0x0 0x10000>;
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iommu-map-mask = <0xfff8>;
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};
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};
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Example (3)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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iommu: iommu@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to the IOMMU is the RID,
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* but the high bits of the bus number are flipped.
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*/
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iommu-map = <0x0000 &iommu 0x8000 0x8000>,
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<0x8000 &iommu 0x0000 0x8000>;
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};
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};
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Example (4)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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iommu_a: iommu@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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iommu_b: iommu@b {
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reg = <0xb 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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iommu_c: iommu@c {
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reg = <0xc 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* Devices with bus number 0-127 are mastered via IOMMU
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* a, with sideband data being RID[14:0].
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* Devices with bus number 128-255 are mastered via
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* IOMMU b, with sideband data being RID[14:0].
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* No devices master via IOMMU c.
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*/
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iommu-map = <0x0000 &iommu_a 0x0000 0x8000>,
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<0x8000 &iommu_b 0x0000 0x8000>;
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};
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};
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