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metag: Internal and external irqchips
Meta core internal interrupts (from HWSTATMETA and friends) are vectored onto the TR1 core trigger for the current thread. This is demultiplexed in irq-metag.c to individual Linux IRQs for each internal interrupt. External SoC interrupts (from HWSTATEXT and friends) are vectored onto the TR2 core trigger for the current thread. This is demultiplexed in irq-metag-ext.c to individual Linux IRQs for each external SoC interrupt. The external irqchip has devicetree bindings for configuring the number of irq banks and the type of masking available. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: Dom Cobley <popcornmix@gmail.com> Cc: Simon Arlott <simon@fire.lp0.eu> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-doc@vger.kernel.org
This commit is contained in:
James Hogan
@@ -0,0 +1,82 @@
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* Meta External Trigger Controller Binding
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This binding specifies what properties must be available in the device tree
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representation of a Meta external trigger controller.
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Required properties:
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- compatible: Specifies the compatibility list for the interrupt controller.
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The type shall be <string> and the value shall include "img,meta-intc".
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- num-banks: Specifies the number of interrupt banks (each of which can
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handle 32 interrupt sources).
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- interrupt-controller: The presence of this property identifies the node
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as an interupt controller. No property value shall be defined.
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 2.
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- #address-cells: Specifies the number of cells needed to encode an
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address. The type shall be <u32> and the value shall be 0. As such,
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'interrupt-map' nodes do not have to specify a parent unit address.
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Optional properties:
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- no-mask: The controller doesn't have any mask registers.
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* Interrupt Specifier Definition
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Interrupt specifiers consists of 2 cells encoded as follows:
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- <1st-cell>: The interrupt-number that identifies the interrupt source.
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- <2nd-cell>: The Linux interrupt flags containing level-sense information,
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encoded as follows:
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1 = edge triggered
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4 = level-sensitive
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* Examples
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Example 1:
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/*
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* Meta external trigger block
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*/
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intc: intc {
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// This is an interrupt controller node.
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interrupt-controller;
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// No address cells so that 'interrupt-map' nodes which
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// reference this interrupt controller node do not need a parent
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// address specifier.
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#address-cells = <0>;
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// Two cells to encode interrupt sources.
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#interrupt-cells = <2>;
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// Number of interrupt banks
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num-banks = <2>;
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// No HWMASKEXT is available (specify on Chorus2 and Comet ES1)
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no-mask;
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// Compatible with Meta hardware trigger block.
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compatible = "img,meta-intc";
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};
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Example 2:
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/*
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* An interrupt generating device that is wired to a Meta external
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* trigger block.
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*/
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uart1: uart@0x02004c00 {
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// Interrupt source '5' that is level-sensitive.
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// Note that there are only two cells as specified in the
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// interrupt parent's '#interrupt-cells' property.
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interrupts = <5 4 /* level */>;
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// The interrupt controller that this device is wired to.
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interrupt-parent = <&intc>;
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};
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@@ -5040,6 +5040,8 @@ F: arch/metag/
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F: Documentation/metag/
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F: Documentation/devicetree/bindings/metag/
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F: drivers/clocksource/metag_generic.c
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F: drivers/irqchip/irq-metag.c
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F: drivers/irqchip/irq-metag-ext.c
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MICROBLAZE ARCHITECTURE
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M: Michal Simek <monstr@monstr.eu>
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@@ -6,6 +6,8 @@
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/irqchip/metag-ext.h>
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#include <linux/irqchip/metag.h>
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#include <linux/irqdomain.h>
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#include <linux/ratelimit.h>
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@@ -258,6 +260,9 @@ void __init init_IRQ(void)
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irq_ctx_init(smp_processor_id());
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init_internal_IRQ();
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init_external_IRQ();
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if (machine_desc->init_irq)
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machine_desc->init_irq();
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}
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@@ -1,4 +1,6 @@
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_METAG) += irq-metag-ext.o
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obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
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obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,343 @@
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/*
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* Meta internal (HWSTATMETA) interrupt code.
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*
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* Copyright (C) 2011-2012 Imagination Technologies Ltd.
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*
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* This code is based on the code in SoC/common/irq.c and SoC/comet/irq.c
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* The code base could be generalised/merged as a lot of the functionality is
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* similar. Until this is done, we try to keep the code simple here.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <asm/irq.h>
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#include <asm/hwthread.h>
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#define PERF0VECINT 0x04820580
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#define PERF1VECINT 0x04820588
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#define PERF0TRIG_OFFSET 16
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#define PERF1TRIG_OFFSET 17
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/**
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* struct metag_internal_irq_priv - private meta internal interrupt data
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* @domain: IRQ domain for all internal Meta IRQs (HWSTATMETA)
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* @unmasked: Record of unmasked IRQs
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*/
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struct metag_internal_irq_priv {
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struct irq_domain *domain;
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unsigned long unmasked;
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};
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/* Private data for the one and only internal interrupt controller */
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static struct metag_internal_irq_priv metag_internal_irq_priv;
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static unsigned int metag_internal_irq_startup(struct irq_data *data);
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static void metag_internal_irq_shutdown(struct irq_data *data);
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static void metag_internal_irq_ack(struct irq_data *data);
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static void metag_internal_irq_mask(struct irq_data *data);
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static void metag_internal_irq_unmask(struct irq_data *data);
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#ifdef CONFIG_SMP
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static int metag_internal_irq_set_affinity(struct irq_data *data,
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const struct cpumask *cpumask, bool force);
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#endif
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static struct irq_chip internal_irq_edge_chip = {
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.name = "HWSTATMETA-IRQ",
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.irq_startup = metag_internal_irq_startup,
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.irq_shutdown = metag_internal_irq_shutdown,
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.irq_ack = metag_internal_irq_ack,
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.irq_mask = metag_internal_irq_mask,
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.irq_unmask = metag_internal_irq_unmask,
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#ifdef CONFIG_SMP
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.irq_set_affinity = metag_internal_irq_set_affinity,
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#endif
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};
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/*
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* metag_hwvec_addr - get the address of *VECINT regs of irq
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*
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* This function is a table of supported triggers on HWSTATMETA
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* Could do with a structure, but better keep it simple. Changes
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* in this code should be rare.
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*/
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static inline void __iomem *metag_hwvec_addr(irq_hw_number_t hw)
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{
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void __iomem *addr;
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switch (hw) {
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case PERF0TRIG_OFFSET:
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addr = (void __iomem *)PERF0VECINT;
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break;
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case PERF1TRIG_OFFSET:
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addr = (void __iomem *)PERF1VECINT;
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break;
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default:
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addr = NULL;
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break;
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}
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return addr;
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}
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/*
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* metag_internal_startup - setup an internal irq
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* @irq: the irq to startup
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*
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* Multiplex interrupts for @irq onto TR1. Clear any pending
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* interrupts.
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*/
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static unsigned int metag_internal_irq_startup(struct irq_data *data)
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{
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/* Clear (toggle) the bit in HWSTATMETA for our interrupt. */
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metag_internal_irq_ack(data);
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/* Enable the interrupt by unmasking it */
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metag_internal_irq_unmask(data);
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return 0;
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}
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/*
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* metag_internal_irq_shutdown - turn off the irq
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* @irq: the irq number to turn off
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*
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* Mask @irq and clear any pending interrupts.
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* Stop muxing @irq onto TR1.
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*/
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static void metag_internal_irq_shutdown(struct irq_data *data)
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{
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/* Disable the IRQ at the core by masking it. */
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metag_internal_irq_mask(data);
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/* Clear (toggle) the bit in HWSTATMETA for our interrupt. */
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metag_internal_irq_ack(data);
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}
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/*
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* metag_internal_irq_ack - acknowledge irq
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* @irq: the irq to ack
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*/
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static void metag_internal_irq_ack(struct irq_data *data)
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{
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irq_hw_number_t hw = data->hwirq;
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unsigned int bit = 1 << hw;
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if (metag_in32(HWSTATMETA) & bit)
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metag_out32(bit, HWSTATMETA);
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}
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/**
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* metag_internal_irq_mask() - mask an internal irq by unvectoring
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* @data: data for the internal irq to mask
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*
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* HWSTATMETA has no mask register. Instead the IRQ is unvectored from the core
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* and retriggered if necessary later.
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*/
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static void metag_internal_irq_mask(struct irq_data *data)
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{
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struct metag_internal_irq_priv *priv = &metag_internal_irq_priv;
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irq_hw_number_t hw = data->hwirq;
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void __iomem *vec_addr = metag_hwvec_addr(hw);
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clear_bit(hw, &priv->unmasked);
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/* there is no interrupt mask, so unvector the interrupt */
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metag_out32(0, vec_addr);
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}
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/**
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* meta_intc_unmask_edge_irq_nomask() - unmask an edge irq by revectoring
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* @data: data for the internal irq to unmask
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*
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* HWSTATMETA has no mask register. Instead the IRQ is revectored back to the
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* core and retriggered if necessary.
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*/
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static void metag_internal_irq_unmask(struct irq_data *data)
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{
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struct metag_internal_irq_priv *priv = &metag_internal_irq_priv;
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irq_hw_number_t hw = data->hwirq;
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unsigned int bit = 1 << hw;
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void __iomem *vec_addr = metag_hwvec_addr(hw);
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unsigned int thread = hard_processor_id();
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set_bit(hw, &priv->unmasked);
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/* there is no interrupt mask, so revector the interrupt */
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metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR1(thread)), vec_addr);
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/*
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* Re-trigger interrupt
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*
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* Writing a 1 toggles, and a 0->1 transition triggers. We only
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* retrigger if the status bit is already set, which means we
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* need to clear it first. Retriggering is fundamentally racy
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* because if the interrupt fires again after we clear it we
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* could end up clearing it again and the interrupt handler
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* thinking it hasn't fired. Therefore we need to keep trying to
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* retrigger until the bit is set.
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*/
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if (metag_in32(HWSTATMETA) & bit) {
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metag_out32(bit, HWSTATMETA);
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while (!(metag_in32(HWSTATMETA) & bit))
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metag_out32(bit, HWSTATMETA);
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}
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}
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#ifdef CONFIG_SMP
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/*
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* metag_internal_irq_set_affinity - set the affinity for an interrupt
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*/
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static int metag_internal_irq_set_affinity(struct irq_data *data,
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const struct cpumask *cpumask, bool force)
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{
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unsigned int cpu, thread;
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irq_hw_number_t hw = data->hwirq;
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/*
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* Wire up this interrupt from *VECINT to the Meta core.
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*
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* Note that we can't wire up *VECINT to interrupt more than
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* one cpu (the interrupt code doesn't support it), so we just
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* pick the first cpu we find in 'cpumask'.
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*/
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cpu = cpumask_any(cpumask);
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thread = cpu_2_hwthread_id[cpu];
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metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR1(thread)),
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metag_hwvec_addr(hw));
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return 0;
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}
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#endif
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/*
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* metag_internal_irq_demux - irq de-multiplexer
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* @irq: the interrupt number
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* @desc: the interrupt description structure for this irq
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*
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* The cpu receives an interrupt on TR1 when an interrupt has
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* occurred. It is this function's job to demux this irq and
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* figure out exactly which trigger needs servicing.
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*/
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static void metag_internal_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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struct metag_internal_irq_priv *priv = irq_desc_get_handler_data(desc);
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irq_hw_number_t hw;
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unsigned int irq_no;
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u32 status;
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recalculate:
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status = metag_in32(HWSTATMETA) & priv->unmasked;
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for (hw = 0; status != 0; status >>= 1, ++hw) {
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if (status & 0x1) {
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/*
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* Map the hardware IRQ number to a virtual Linux IRQ
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* number.
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*/
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irq_no = irq_linear_revmap(priv->domain, hw);
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/*
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* Only fire off interrupts that are
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* registered to be handled by the kernel.
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* Other interrupts are probably being
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* handled by other Meta hardware threads.
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*/
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generic_handle_irq(irq_no);
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/*
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* The handler may have re-enabled interrupts
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* which could have caused a nested invocation
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* of this code and make the copy of the
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* status register we are using invalid.
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*/
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goto recalculate;
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}
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}
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}
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/**
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* internal_irq_map() - Map an internal meta IRQ to a virtual IRQ number.
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* @hw: Number of the internal IRQ. Must be in range.
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*
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* Returns: The virtual IRQ number of the Meta internal IRQ specified by
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* @hw.
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*/
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int internal_irq_map(unsigned int hw)
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{
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struct metag_internal_irq_priv *priv = &metag_internal_irq_priv;
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if (!priv->domain)
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return -ENODEV;
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return irq_create_mapping(priv->domain, hw);
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}
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/**
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* metag_internal_irq_init_cpu - regsister with the Meta cpu
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* @cpu: the CPU to register on
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*
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* Configure @cpu's TR1 irq so that we can demux irqs.
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*/
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static void metag_internal_irq_init_cpu(struct metag_internal_irq_priv *priv,
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int cpu)
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{
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unsigned int thread = cpu_2_hwthread_id[cpu];
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unsigned int signum = TBID_SIGNUM_TR1(thread);
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int irq = tbisig_map(signum);
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/* Register the multiplexed IRQ handler */
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irq_set_handler_data(irq, priv);
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irq_set_chained_handler(irq, metag_internal_irq_demux);
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irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
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}
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/**
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* metag_internal_intc_map() - map an internal irq
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* @d: irq domain of internal trigger block
|
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* @irq: virtual irq number
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* @hw: hardware irq number within internal trigger block
|
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*
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* This sets up a virtual irq for a specified hardware interrupt. The irq chip
|
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* and handler is configured.
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*/
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static int metag_internal_intc_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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/* only register interrupt if it is mapped */
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if (!metag_hwvec_addr(hw))
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return -EINVAL;
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irq_set_chip_and_handler(irq, &internal_irq_edge_chip,
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handle_edge_irq);
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return 0;
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}
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static const struct irq_domain_ops metag_internal_intc_domain_ops = {
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.map = metag_internal_intc_map,
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};
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/**
|
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* metag_internal_irq_register - register internal IRQs
|
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*
|
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* Register the irq chip and handler function for all internal IRQs
|
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*/
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int __init init_internal_IRQ(void)
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{
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struct metag_internal_irq_priv *priv = &metag_internal_irq_priv;
|
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unsigned int cpu;
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/* Set up an IRQ domain */
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priv->domain = irq_domain_add_linear(NULL, 32,
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&metag_internal_intc_domain_ops,
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priv);
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if (unlikely(!priv->domain)) {
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pr_err("meta-internal-intc: cannot add IRQ domain\n");
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return -ENOMEM;
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}
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/* Setup TR1 for all cpus. */
|
||||
for_each_possible_cpu(cpu)
|
||||
metag_internal_irq_init_cpu(priv, cpu);
|
||||
|
||||
return 0;
|
||||
};
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Imagination Technologies
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_IRQCHIP_METAG_EXT_H_
|
||||
#define _LINUX_IRQCHIP_METAG_EXT_H_
|
||||
|
||||
struct irq_data;
|
||||
struct platform_device;
|
||||
|
||||
/* called from core irq code at init */
|
||||
int init_external_IRQ(void);
|
||||
|
||||
/*
|
||||
* called from SoC init_irq() callback to dynamically indicate the lack of
|
||||
* HWMASKEXT registers.
|
||||
*/
|
||||
void meta_intc_no_mask(void);
|
||||
|
||||
/*
|
||||
* These allow SoCs to specialise the interrupt controller from their init_irq
|
||||
* callbacks.
|
||||
*/
|
||||
|
||||
extern struct irq_chip meta_intc_edge_chip;
|
||||
extern struct irq_chip meta_intc_level_chip;
|
||||
|
||||
/* this should be called in the mask callback */
|
||||
void meta_intc_mask_irq_simple(struct irq_data *data);
|
||||
/* this should be called in the unmask callback */
|
||||
void meta_intc_unmask_irq_simple(struct irq_data *data);
|
||||
|
||||
#endif /* _LINUX_IRQCHIP_METAG_EXT_H_ */
|
||||
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Imagination Technologies
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_IRQCHIP_METAG_H_
|
||||
#define _LINUX_IRQCHIP_METAG_H_
|
||||
|
||||
#include <linux/errno.h>
|
||||
|
||||
#ifdef CONFIG_METAG_PERFCOUNTER_IRQS
|
||||
extern int init_internal_IRQ(void);
|
||||
extern int internal_irq_map(unsigned int hw);
|
||||
#else
|
||||
static inline int init_internal_IRQ(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int internal_irq_map(unsigned int hw)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _LINUX_IRQCHIP_METAG_H_ */
|
||||
Reference in New Issue
Block a user