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Merge tag 'omap-cleanup-c-for-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.8/clock
Convert the OMAP2+ clock code and data to rely on the common clock framework for internal bookkeeping and the driver API. Basic test logs for this branch on top of Tony's cleanup-prcm branch at commitc9d501e5cbare here: http://www.pwsan.com/omap/testlogs/common_clk_devel_3.8_rebase/20121112192516/ However, cleanup-prcm atc9d501e5does not include some fixes that are needed for a successful test. With several reverts, fixes, and workarounds applied, the following test logs were obtained: http://www.pwsan.com/omap/testlogs/TEST_common_clk_devel_3.8_rebase/20121112192300/ which indicate that the series tests cleanly. N.B. The common clock data addition patches result in many checkpatch warnings of the form "WARNING: static const char * array should probably be static const char * const". However, it appears that resolving these would require changes to the CCF itself. So the resolution of these warnings is being postponed until that can be coordinated. These patches result in a ~55KiB increase in runtime kernel memory usage when booting omap2plus_defconfig kernels. Conflicts: arch/arm/mach-omap2/clock33xx_data.c arch/arm/mach-omap2/clock3xxx_data.c arch/arm/mach-omap2/clock44xx_data.c
This commit is contained in:
Tony Lindgren
@@ -34,6 +34,7 @@ config ARCH_OMAP2
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select CPU_V6
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select MULTI_IRQ_HANDLER
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select SOC_HAS_OMAP2_SDRC
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select COMMON_CLK
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config ARCH_OMAP3
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bool "TI OMAP3"
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@@ -47,6 +48,7 @@ config ARCH_OMAP3
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select PM_OPP if PM
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select PM_RUNTIME if CPU_IDLE
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select SOC_HAS_OMAP2_SDRC
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select COMMON_CLK
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select USB_ARCH_HAS_EHCI if USB_SUPPORT
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config ARCH_OMAP4
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@@ -68,6 +70,7 @@ config ARCH_OMAP4
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select PM_OPP if PM
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select PM_RUNTIME if CPU_IDLE
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select USB_ARCH_HAS_EHCI if USB_SUPPORT
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select COMMON_CLK
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config SOC_OMAP5
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bool "TI OMAP5"
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@@ -77,6 +80,7 @@ config SOC_OMAP5
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select CPU_V7
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select HAVE_SMP
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select SOC_HAS_REALTIME_COUNTER
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select COMMON_CLK
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comment "OMAP Core Type"
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depends on ARCH_OMAP2
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@@ -111,6 +115,7 @@ config SOC_AM33XX
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select ARM_CPU_SUSPEND if PM
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select CPU_V7
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select MULTI_IRQ_HANDLER
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select COMMON_CLK
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config OMAP_PACKAGE_ZAF
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bool
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@@ -158,17 +158,17 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
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obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o
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obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
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obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
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obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
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obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
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obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o
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obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
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obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
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obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -38,62 +38,88 @@
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/* Private functions */
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static int _apll96_enable(struct clk *clk)
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/**
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* omap2xxx_clk_apll_locked - is the APLL locked?
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* @hw: struct clk_hw * of the APLL to check
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*
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* If the APLL IP block referred to by @hw indicates that it's locked,
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* return true; otherwise, return false.
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*/
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static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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u32 r, apll_mask;
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apll_mask = EN_APLL_LOCKED << clk->enable_bit;
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r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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return ((r & apll_mask) == apll_mask) ? true : false;
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}
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int omap2_clk_apll96_enable(struct clk_hw *hw)
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{
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return omap2xxx_cm_apll96_enable();
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}
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static int _apll54_enable(struct clk *clk)
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int omap2_clk_apll54_enable(struct clk_hw *hw)
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{
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return omap2xxx_cm_apll54_enable();
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}
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static void _apll96_allow_idle(struct clk *clk)
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static void _apll96_allow_idle(struct clk_hw_omap *clk)
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{
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omap2xxx_cm_set_apll96_auto_low_power_stop();
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}
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static void _apll96_deny_idle(struct clk *clk)
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static void _apll96_deny_idle(struct clk_hw_omap *clk)
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{
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omap2xxx_cm_set_apll96_disable_autoidle();
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}
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static void _apll54_allow_idle(struct clk *clk)
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static void _apll54_allow_idle(struct clk_hw_omap *clk)
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{
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omap2xxx_cm_set_apll54_auto_low_power_stop();
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}
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static void _apll54_deny_idle(struct clk *clk)
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static void _apll54_deny_idle(struct clk_hw_omap *clk)
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{
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omap2xxx_cm_set_apll54_disable_autoidle();
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}
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static void _apll96_disable(struct clk *clk)
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void omap2_clk_apll96_disable(struct clk_hw *hw)
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{
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omap2xxx_cm_apll96_disable();
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}
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static void _apll54_disable(struct clk *clk)
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void omap2_clk_apll54_disable(struct clk_hw *hw)
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{
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omap2xxx_cm_apll54_disable();
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}
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unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0;
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}
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unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0;
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}
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/* Public data */
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const struct clkops clkops_apll96 = {
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.enable = _apll96_enable,
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.disable = _apll96_disable,
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.allow_idle = _apll96_allow_idle,
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.deny_idle = _apll96_deny_idle,
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};
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const struct clkops clkops_apll54 = {
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.enable = _apll54_enable,
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.disable = _apll54_disable,
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const struct clk_hw_omap_ops clkhwops_apll54 = {
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.allow_idle = _apll54_allow_idle,
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.deny_idle = _apll54_deny_idle,
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};
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const struct clk_hw_omap_ops clkhwops_apll96 = {
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.allow_idle = _apll96_allow_idle,
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.deny_idle = _apll96_deny_idle,
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};
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/* Public functions */
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u32 omap2xxx_get_apll_clkin(void)
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@@ -29,7 +29,7 @@
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* REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
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* instead. Add some mechanism to optionally enter this mode.
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*/
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static void _allow_idle(struct clk *clk)
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static void _allow_idle(struct clk_hw_omap *clk)
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{
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if (!clk || !clk->dpll_data)
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return;
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@@ -43,7 +43,7 @@ static void _allow_idle(struct clk *clk)
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*
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* Disable DPLL automatic idle control. No return value.
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*/
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static void _deny_idle(struct clk *clk)
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static void _deny_idle(struct clk_hw_omap *clk)
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{
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if (!clk || !clk->dpll_data)
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return;
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@@ -53,9 +53,7 @@ static void _deny_idle(struct clk *clk)
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/* Public data */
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const struct clkops clkops_omap2xxx_dpll_ops = {
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const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
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.allow_idle = _allow_idle,
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.deny_idle = _deny_idle,
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};
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@@ -41,7 +41,7 @@
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* (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
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* during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
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*/
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static struct clk *dpll_core_ck;
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static struct clk_hw_omap *dpll_core_ck;
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/**
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* omap2xxx_clk_get_core_rate - return the CORE_CLK rate
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@@ -105,13 +105,16 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
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}
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unsigned long omap2_dpllcore_recalc(struct clk *clk)
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unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return omap2xxx_clk_get_core_rate();
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}
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int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
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int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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u32 cur_rate, low, mult, div, valid_rate, done_rate;
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u32 bypass = 0;
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struct prcm_config tmpset;
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@@ -189,8 +192,8 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
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* statically defined, this code may need to change to increment some
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* kind of use count on dpll_ck.
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*/
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void omap2xxx_clkt_dpllcore_init(struct clk *clk)
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void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
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{
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WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
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dpll_core_ck = clk;
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dpll_core_ck = to_clk_hw_omap(hw);
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}
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@@ -35,7 +35,7 @@
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* clk_enable/clk_disable()-based usecounting for osc_ck should be
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* replaced with autoidle-based usecounting.
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*/
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static int omap2_enable_osc_ck(struct clk *clk)
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int omap2_enable_osc_ck(struct clk_hw *clk)
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{
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u32 pcc;
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@@ -53,7 +53,7 @@ static int omap2_enable_osc_ck(struct clk *clk)
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* clk_enable/clk_disable()-based usecounting for osc_ck should be
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* replaced with autoidle-based usecounting.
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*/
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static void omap2_disable_osc_ck(struct clk *clk)
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void omap2_disable_osc_ck(struct clk_hw *clk)
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{
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u32 pcc;
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@@ -62,13 +62,8 @@ static void omap2_disable_osc_ck(struct clk *clk)
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__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
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}
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const struct clkops clkops_oscck = {
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.enable = omap2_enable_osc_ck,
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.disable = omap2_disable_osc_ck,
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};
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unsigned long omap2_osc_clk_recalc(struct clk *clk)
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unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
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unsigned long parent_rate)
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{
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return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
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}
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@@ -40,9 +40,8 @@ u32 omap2xxx_get_sysclkdiv(void)
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return div;
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}
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unsigned long omap2xxx_sys_clk_recalc(struct clk *clk)
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unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
|
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unsigned long parent_rate)
|
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{
|
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return clk->parent->rate / omap2xxx_get_sysclkdiv();
|
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return parent_rate / omap2xxx_get_sysclkdiv();
|
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}
|
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|
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@@ -59,7 +59,8 @@ static unsigned long sys_ck_rate;
|
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*
|
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* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
|
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*/
|
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unsigned long omap2_table_mpu_recalc(struct clk *clk)
|
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unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
|
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unsigned long parent_rate)
|
||||
{
|
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return curr_prcm_set->mpu_speed;
|
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}
|
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@@ -71,7 +72,8 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
|
||||
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
|
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* just uses the ARM rates.
|
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*/
|
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long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
|
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long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
|
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unsigned long *parent_rate)
|
||||
{
|
||||
const struct prcm_config *ptr;
|
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long highest_rate;
|
||||
@@ -94,7 +96,8 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
|
||||
}
|
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|
||||
/* Sets basic clocks based on the specified rate */
|
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int omap2_select_table_rate(struct clk *clk, unsigned long rate)
|
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int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
|
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unsigned long parent_rate)
|
||||
{
|
||||
u32 cur_rate, done_rate, bypass = 0, tmp;
|
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const struct prcm_config *prcm;
|
||||
|
||||
@@ -45,8 +45,10 @@
|
||||
* Program the DPLL M2 divider with the rounded target rate. Returns
|
||||
* -EINVAL upon error, or 0 upon success.
|
||||
*/
|
||||
int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
|
||||
int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
|
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unsigned long parent_rate)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
u32 new_div = 0;
|
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u32 unlock_dll = 0;
|
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u32 c;
|
||||
@@ -64,7 +66,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
|
||||
return -EINVAL;
|
||||
|
||||
sdrcrate = __clk_get_rate(sdrc_ick_p);
|
||||
clkrate = __clk_get_rate(clk);
|
||||
clkrate = __clk_get_rate(hw->clk);
|
||||
if (rate > clkrate)
|
||||
sdrcrate <<= ((rate / clkrate) >> 1);
|
||||
else
|
||||
@@ -113,8 +115,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
|
||||
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
|
||||
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
|
||||
0, 0, 0, 0);
|
||||
clk->rate = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -41,7 +41,7 @@
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/bug.h>
|
||||
|
||||
@@ -58,11 +58,14 @@
|
||||
* the element associated with the supplied parent clock address.
|
||||
* Returns a pointer to the struct clksel on success or NULL on error.
|
||||
*/
|
||||
static const struct clksel *_get_clksel_by_parent(struct clk *clk,
|
||||
static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk,
|
||||
struct clk *src_clk)
|
||||
{
|
||||
const struct clksel *clks;
|
||||
|
||||
if (!src_clk)
|
||||
return NULL;
|
||||
|
||||
for (clks = clk->clksel; clks->parent; clks++)
|
||||
if (clks->parent == src_clk)
|
||||
break; /* Found the requested parent */
|
||||
@@ -70,71 +73,13 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
|
||||
if (!clks->parent) {
|
||||
/* This indicates a data problem */
|
||||
WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
|
||||
__clk_get_name(clk), __clk_get_name(src_clk));
|
||||
__clk_get_name(clk->hw.clk), __clk_get_name(src_clk));
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return clks;
|
||||
}
|
||||
|
||||
/**
|
||||
* _get_div_and_fieldval() - find the new clksel divisor and field value to use
|
||||
* @src_clk: planned new parent struct clk *
|
||||
* @clk: struct clk * that is being reparented
|
||||
* @field_val: pointer to a u32 to contain the register data for the divisor
|
||||
*
|
||||
* Given an intended new parent struct clk * @src_clk, and the struct
|
||||
* clk * @clk to the clock that is being reparented, find the
|
||||
* appropriate rate divisor for the new clock (returned as the return
|
||||
* value), and the corresponding register bitfield data to program to
|
||||
* reach that divisor (returned in the u32 pointed to by @field_val).
|
||||
* Returns 0 on error, or returns the newly-selected divisor upon
|
||||
* success (in this latter case, the corresponding register bitfield
|
||||
* value is passed back in the variable pointed to by @field_val)
|
||||
*/
|
||||
static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
|
||||
u32 *field_val)
|
||||
{
|
||||
const struct clksel *clks;
|
||||
const struct clksel_rate *clkr, *max_clkr = NULL;
|
||||
u8 max_div = 0;
|
||||
|
||||
clks = _get_clksel_by_parent(clk, src_clk);
|
||||
if (!clks)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Find the highest divisor (e.g., the one resulting in the
|
||||
* lowest rate) to use as the default. This should avoid
|
||||
* clock rates that are too high for the device. XXX A better
|
||||
* solution here would be to try to determine if there is a
|
||||
* divisor matching the original clock rate before the parent
|
||||
* switch, and if it cannot be found, to fall back to the
|
||||
* highest divisor.
|
||||
*/
|
||||
for (clkr = clks->rates; clkr->div; clkr++) {
|
||||
if (!(clkr->flags & cpu_mask))
|
||||
continue;
|
||||
|
||||
if (clkr->div > max_div) {
|
||||
max_div = clkr->div;
|
||||
max_clkr = clkr;
|
||||
}
|
||||
}
|
||||
|
||||
if (max_div == 0) {
|
||||
/* This indicates an error in the clksel data */
|
||||
WARN(1, "clock: %s: could not find divisor for parent %s\n",
|
||||
__clk_get_name(clk),
|
||||
__clk_get_name(__clk_get_parent(src_clk)));
|
||||
return 0;
|
||||
}
|
||||
|
||||
*field_val = max_clkr->val;
|
||||
|
||||
return max_div;
|
||||
}
|
||||
|
||||
/**
|
||||
* _write_clksel_reg() - program a clock's clksel register in hardware
|
||||
* @clk: struct clk * to program
|
||||
@@ -148,7 +93,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
|
||||
* take into account any time the hardware might take to switch the
|
||||
* clock source.
|
||||
*/
|
||||
static void _write_clksel_reg(struct clk *clk, u32 field_val)
|
||||
static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
@@ -171,13 +116,14 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val)
|
||||
* before calling. Returns 0 on error or returns the actual integer divisor
|
||||
* upon success.
|
||||
*/
|
||||
static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
|
||||
static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val)
|
||||
{
|
||||
const struct clksel *clks;
|
||||
const struct clksel_rate *clkr;
|
||||
struct clk *parent;
|
||||
|
||||
parent = __clk_get_parent(clk);
|
||||
parent = __clk_get_parent(clk->hw.clk);
|
||||
|
||||
clks = _get_clksel_by_parent(clk, parent);
|
||||
if (!clks)
|
||||
return 0;
|
||||
@@ -193,7 +139,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
|
||||
if (!clkr->div) {
|
||||
/* This indicates a data error */
|
||||
WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
|
||||
__clk_get_name(clk), field_val, __clk_get_name(parent));
|
||||
__clk_get_name(clk->hw.clk), field_val,
|
||||
__clk_get_name(parent));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -210,7 +157,7 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
|
||||
* register field value _before_ left-shifting (i.e., LSB is at bit
|
||||
* 0); or returns 0xFFFFFFFF (~0) upon error.
|
||||
*/
|
||||
static u32 _divisor_to_clksel(struct clk *clk, u32 div)
|
||||
static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div)
|
||||
{
|
||||
const struct clksel *clks;
|
||||
const struct clksel_rate *clkr;
|
||||
@@ -219,7 +166,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
|
||||
/* should never happen */
|
||||
WARN_ON(div == 0);
|
||||
|
||||
parent = __clk_get_parent(clk);
|
||||
parent = __clk_get_parent(clk->hw.clk);
|
||||
clks = _get_clksel_by_parent(clk, parent);
|
||||
if (!clks)
|
||||
return ~0;
|
||||
@@ -234,7 +181,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
|
||||
|
||||
if (!clkr->div) {
|
||||
pr_err("clock: %s: could not find divisor %d for parent %s\n",
|
||||
__clk_get_name(clk), div, __clk_get_name(parent));
|
||||
__clk_get_name(clk->hw.clk), div,
|
||||
__clk_get_name(parent));
|
||||
return ~0;
|
||||
}
|
||||
|
||||
@@ -249,7 +197,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
|
||||
* into the hardware, convert it into the actual divisor value, and
|
||||
* return it; or return 0 on error.
|
||||
*/
|
||||
static u32 _read_divisor(struct clk *clk)
|
||||
static u32 _read_divisor(struct clk_hw_omap *clk)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
@@ -277,7 +225,8 @@ static u32 _read_divisor(struct clk *clk)
|
||||
*
|
||||
* Returns the rounded clock rate or returns 0xffffffff on error.
|
||||
*/
|
||||
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
|
||||
u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
|
||||
unsigned long target_rate,
|
||||
u32 *new_div)
|
||||
{
|
||||
unsigned long test_rate;
|
||||
@@ -288,9 +237,9 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
|
||||
unsigned long parent_rate;
|
||||
const char *clk_name;
|
||||
|
||||
parent = __clk_get_parent(clk);
|
||||
parent = __clk_get_parent(clk->hw.clk);
|
||||
clk_name = __clk_get_name(clk->hw.clk);
|
||||
parent_rate = __clk_get_rate(parent);
|
||||
clk_name = __clk_get_name(clk);
|
||||
|
||||
if (!clk->clksel || !clk->clksel_mask)
|
||||
return ~0;
|
||||
@@ -341,27 +290,35 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
|
||||
*/
|
||||
|
||||
/**
|
||||
* omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
|
||||
* @clk: OMAP clock struct ptr to use
|
||||
* omap2_clksel_find_parent_index() - return the array index of the current
|
||||
* hardware parent of @hw
|
||||
* @hw: struct clk_hw * to find the current hardware parent of
|
||||
*
|
||||
* Given a pointer @clk to a source-selectable struct clk, read the
|
||||
* hardware register and determine what its parent is currently set
|
||||
* to. Update @clk's .parent field with the appropriate clk ptr. No
|
||||
* return value.
|
||||
* Given a struct clk_hw pointer @hw to the 'hw' member of a struct
|
||||
* clk_hw_omap record representing a source-selectable hardware clock,
|
||||
* read the hardware register and determine what its parent is
|
||||
* currently set to. Intended to be called only by the common clock
|
||||
* framework struct clk_hw_ops.get_parent function pointer. Return
|
||||
* the array index of this parent clock upon success -- there is no
|
||||
* way to return an error, so if we encounter an error, just WARN()
|
||||
* and pretend that we know that we're doing.
|
||||
*/
|
||||
void omap2_init_clksel_parent(struct clk *clk)
|
||||
u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
const struct clksel *clks;
|
||||
const struct clksel_rate *clkr;
|
||||
u32 r, found = 0;
|
||||
struct clk *parent;
|
||||
const char *clk_name;
|
||||
int ret = 0, f = 0;
|
||||
|
||||
if (!clk->clksel || !clk->clksel_mask)
|
||||
return;
|
||||
parent = __clk_get_parent(hw->clk);
|
||||
clk_name = __clk_get_name(hw->clk);
|
||||
|
||||
parent = __clk_get_parent(clk);
|
||||
clk_name = __clk_get_name(clk);
|
||||
/* XXX should be able to return an error */
|
||||
WARN((!clk->clksel || !clk->clksel_mask),
|
||||
"clock: %s: attempt to call on a non-clksel clock", clk_name);
|
||||
|
||||
r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
|
||||
r >>= __ffs(clk->clksel_mask);
|
||||
@@ -372,27 +329,21 @@ void omap2_init_clksel_parent(struct clk *clk)
|
||||
continue;
|
||||
|
||||
if (clkr->val == r) {
|
||||
if (parent != clks->parent) {
|
||||
pr_debug("clock: %s: inited parent to %s (was %s)\n",
|
||||
clk_name,
|
||||
__clk_get_name(clks->parent),
|
||||
((parent) ?
|
||||
__clk_get_name(parent) :
|
||||
"NULL"));
|
||||
clk_reparent(clk, clks->parent);
|
||||
}
|
||||
found = 1;
|
||||
ret = f;
|
||||
}
|
||||
}
|
||||
f++;
|
||||
}
|
||||
|
||||
/* This indicates a data error */
|
||||
WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
|
||||
clk_name, r);
|
||||
|
||||
return;
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
|
||||
* @clk: struct clk *
|
||||
@@ -402,21 +353,23 @@ void omap2_init_clksel_parent(struct clk *clk)
|
||||
* function. Returns the clock's current rate, based on its parent's rate
|
||||
* and its current divisor setting in the hardware.
|
||||
*/
|
||||
unsigned long omap2_clksel_recalc(struct clk *clk)
|
||||
unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate)
|
||||
{
|
||||
unsigned long rate;
|
||||
u32 div = 0;
|
||||
struct clk *parent;
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
|
||||
if (!parent_rate)
|
||||
return 0;
|
||||
|
||||
div = _read_divisor(clk);
|
||||
if (div == 0)
|
||||
return __clk_get_rate(clk);
|
||||
if (!div)
|
||||
rate = parent_rate;
|
||||
else
|
||||
rate = parent_rate / div;
|
||||
|
||||
parent = __clk_get_parent(clk);
|
||||
rate = __clk_get_rate(parent) / div;
|
||||
|
||||
pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
|
||||
__clk_get_name(clk), rate, div);
|
||||
pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__,
|
||||
__clk_get_name(hw->clk), rate, div);
|
||||
|
||||
return rate;
|
||||
}
|
||||
@@ -432,8 +385,10 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
|
||||
*
|
||||
* Returns the rounded clock rate or returns 0xffffffff on error.
|
||||
*/
|
||||
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
|
||||
long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
u32 new_div;
|
||||
|
||||
return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
|
||||
@@ -454,8 +409,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
|
||||
* is changed, they will all be affected without any notification.
|
||||
* Returns -EINVAL upon error, or 0 upon success.
|
||||
*/
|
||||
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
|
||||
int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
u32 field_val, validrate, new_div = 0;
|
||||
|
||||
if (!clk->clksel || !clk->clksel_mask)
|
||||
@@ -471,10 +428,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
|
||||
|
||||
_write_clksel_reg(clk, field_val);
|
||||
|
||||
clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
|
||||
|
||||
pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
|
||||
__clk_get_rate(clk));
|
||||
pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk),
|
||||
__clk_get_rate(hw->clk));
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -499,32 +454,13 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
|
||||
* affected without any notification. Returns -EINVAL upon error, or
|
||||
* 0 upon success.
|
||||
*/
|
||||
int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
|
||||
int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val)
|
||||
{
|
||||
u32 field_val = 0;
|
||||
u32 parent_div;
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
|
||||
if (!clk->clksel || !clk->clksel_mask)
|
||||
return -EINVAL;
|
||||
|
||||
parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
|
||||
if (!parent_div)
|
||||
return -EINVAL;
|
||||
|
||||
_write_clksel_reg(clk, field_val);
|
||||
|
||||
clk_reparent(clk, new_parent);
|
||||
|
||||
/* CLKSEL clocks follow their parents' rates, divided by a divisor */
|
||||
clk->rate = __clk_get_rate(new_parent);
|
||||
|
||||
if (parent_div > 0)
|
||||
__clk_get_rate(clk) /= parent_div;
|
||||
|
||||
pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
|
||||
__clk_get_name(clk),
|
||||
__clk_get_name(__clk_get_parent(clk)),
|
||||
__clk_get_rate(clk));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -16,7 +16,7 @@
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/div64.h>
|
||||
@@ -76,7 +76,7 @@
|
||||
* (assuming that it is counting N upwards), or -2 if the enclosing loop
|
||||
* should skip to the next iteration (again assuming N is increasing).
|
||||
*/
|
||||
static int _dpll_test_fint(struct clk *clk, u8 n)
|
||||
static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
|
||||
{
|
||||
struct dpll_data *dd;
|
||||
long fint, fint_min, fint_max;
|
||||
@@ -85,7 +85,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
|
||||
dd = clk->dpll_data;
|
||||
|
||||
/* DPLL divider must result in a valid jitter correction val */
|
||||
fint = __clk_get_rate(__clk_get_parent(clk)) / n;
|
||||
fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
/* Should not be called for OMAP2, so warn if it is called */
|
||||
@@ -186,15 +186,15 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
|
||||
}
|
||||
|
||||
/* Public functions */
|
||||
|
||||
void omap2_init_dpll_parent(struct clk *clk)
|
||||
u8 omap2_init_dpll_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
u32 v;
|
||||
struct dpll_data *dd;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
if (!dd)
|
||||
return;
|
||||
return -EINVAL;
|
||||
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v &= dd->enable_mask;
|
||||
@@ -204,18 +204,18 @@ void omap2_init_dpll_parent(struct clk *clk)
|
||||
if (cpu_is_omap24xx()) {
|
||||
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
|
||||
clk_reparent(clk, dd->clk_bypass);
|
||||
return 1;
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
|
||||
clk_reparent(clk, dd->clk_bypass);
|
||||
return 1;
|
||||
} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
|
||||
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
|
||||
clk_reparent(clk, dd->clk_bypass);
|
||||
return 1;
|
||||
}
|
||||
return;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -232,7 +232,7 @@ void omap2_init_dpll_parent(struct clk *clk)
|
||||
* locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
|
||||
* if the clock @clk is not a DPLL.
|
||||
*/
|
||||
u32 omap2_get_dpll_rate(struct clk *clk)
|
||||
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
|
||||
{
|
||||
long long dpll_clk;
|
||||
u32 dpll_mult, dpll_div, v;
|
||||
@@ -288,8 +288,10 @@ u32 omap2_get_dpll_rate(struct clk *clk)
|
||||
* (expensive) function again. Returns ~0 if the target rate cannot
|
||||
* be rounded, or the rounded rate upon success.
|
||||
*/
|
||||
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
|
||||
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
int m, n, r, scaled_max_m;
|
||||
unsigned long scaled_rt_rp;
|
||||
unsigned long new_rate = 0;
|
||||
@@ -303,7 +305,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
|
||||
dd = clk->dpll_data;
|
||||
|
||||
ref_rate = __clk_get_rate(dd->clk_ref);
|
||||
clk_name = __clk_get_name(clk);
|
||||
clk_name = __clk_get_name(hw->clk);
|
||||
pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
|
||||
clk_name, target_rate);
|
||||
|
||||
|
||||
@@ -11,7 +11,7 @@
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
|
||||
@@ -23,7 +23,7 @@
|
||||
/* Private functions */
|
||||
|
||||
/* XXX */
|
||||
void omap2_clkt_iclk_allow_idle(struct clk *clk)
|
||||
void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
|
||||
{
|
||||
u32 v, r;
|
||||
|
||||
@@ -35,7 +35,7 @@ void omap2_clkt_iclk_allow_idle(struct clk *clk)
|
||||
}
|
||||
|
||||
/* XXX */
|
||||
void omap2_clkt_iclk_deny_idle(struct clk *clk)
|
||||
void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
|
||||
{
|
||||
u32 v, r;
|
||||
|
||||
@@ -48,33 +48,17 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk)
|
||||
|
||||
/* Public data */
|
||||
|
||||
const struct clkops clkops_omap2_iclk_dflt_wait = {
|
||||
.enable = omap2_dflt_clk_enable,
|
||||
.disable = omap2_dflt_clk_disable,
|
||||
.find_companion = omap2_clk_dflt_find_companion,
|
||||
const struct clk_hw_omap_ops clkhwops_iclk = {
|
||||
.allow_idle = omap2_clkt_iclk_allow_idle,
|
||||
.deny_idle = omap2_clkt_iclk_deny_idle,
|
||||
};
|
||||
|
||||
const struct clk_hw_omap_ops clkhwops_iclk_wait = {
|
||||
.allow_idle = omap2_clkt_iclk_allow_idle,
|
||||
.deny_idle = omap2_clkt_iclk_deny_idle,
|
||||
.find_idlest = omap2_clk_dflt_find_idlest,
|
||||
.allow_idle = omap2_clkt_iclk_allow_idle,
|
||||
.deny_idle = omap2_clkt_iclk_deny_idle,
|
||||
};
|
||||
|
||||
const struct clkops clkops_omap2_iclk_dflt = {
|
||||
.enable = omap2_dflt_clk_enable,
|
||||
.disable = omap2_dflt_clk_disable,
|
||||
.allow_idle = omap2_clkt_iclk_allow_idle,
|
||||
.deny_idle = omap2_clkt_iclk_deny_idle,
|
||||
};
|
||||
|
||||
const struct clkops clkops_omap2_iclk_idle_only = {
|
||||
.allow_idle = omap2_clkt_iclk_allow_idle,
|
||||
.deny_idle = omap2_clkt_iclk_deny_idle,
|
||||
};
|
||||
|
||||
const struct clkops clkops_omap2_mdmclk_dflt_wait = {
|
||||
.enable = omap2_dflt_clk_enable,
|
||||
.disable = omap2_dflt_clk_disable,
|
||||
.find_companion = omap2_clk_dflt_find_companion,
|
||||
.find_idlest = omap2_clk_dflt_find_idlest,
|
||||
.allow_idle = omap2_clkt_iclk_allow_idle,
|
||||
.deny_idle = omap2_clkt_iclk_deny_idle,
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
+272
-698
File diff suppressed because it is too large
Load Diff
+164
-161
@@ -20,6 +20,7 @@
|
||||
#include <linux/list.h>
|
||||
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
struct omap_clk {
|
||||
u16 cpu;
|
||||
@@ -52,44 +53,85 @@ struct omap_clk {
|
||||
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
|
||||
#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
|
||||
|
||||
struct module;
|
||||
struct clk;
|
||||
struct clockdomain;
|
||||
#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
|
||||
|
||||
/* Temporary, needed during the common clock framework conversion */
|
||||
#define __clk_get_name(clk) (clk->name)
|
||||
#define __clk_get_parent(clk) (clk->parent)
|
||||
#define __clk_get_rate(clk) (clk->rate)
|
||||
|
||||
/**
|
||||
* struct clkops - some clock function pointers
|
||||
* @enable: fn ptr that enables the current clock in hardware
|
||||
* @disable: fn ptr that enables the current clock in hardware
|
||||
* @find_idlest: function returning the IDLEST register for the clock's IP blk
|
||||
* @find_companion: function returning the "companion" clk reg for the clock
|
||||
* @allow_idle: fn ptr that enables autoidle for the current clock in hardware
|
||||
* @deny_idle: fn ptr that disables autoidle for the current clock in hardware
|
||||
*
|
||||
* A "companion" clk is an accompanying clock to the one being queried
|
||||
* that must be enabled for the IP module connected to the clock to
|
||||
* become accessible by the hardware. Neither @find_idlest nor
|
||||
* @find_companion should be needed; that information is IP
|
||||
* block-specific; the hwmod code has been created to handle this, but
|
||||
* until hwmod data is ready and drivers have been converted to use PM
|
||||
* runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
|
||||
* @find_companion must, unfortunately, remain.
|
||||
*/
|
||||
struct clkops {
|
||||
int (*enable)(struct clk *);
|
||||
void (*disable)(struct clk *);
|
||||
void (*find_idlest)(struct clk *, void __iomem **,
|
||||
u8 *, u8 *);
|
||||
void (*find_companion)(struct clk *, void __iomem **,
|
||||
u8 *);
|
||||
void (*allow_idle)(struct clk *);
|
||||
void (*deny_idle)(struct clk *);
|
||||
#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
|
||||
static struct clk _name = { \
|
||||
.name = #_name, \
|
||||
.hw = &_name##_hw.hw, \
|
||||
.parent_names = _parent_array_name, \
|
||||
.num_parents = ARRAY_SIZE(_parent_array_name), \
|
||||
.ops = &_clkops_name, \
|
||||
};
|
||||
|
||||
#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
|
||||
static struct clk_hw_omap _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.clkdm_name = _clkdm_name, \
|
||||
};
|
||||
|
||||
#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
|
||||
_clksel_reg, _clksel_mask, \
|
||||
_parent_names, _ops) \
|
||||
static struct clk _name; \
|
||||
static struct clk_hw_omap _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.clksel = _clksel, \
|
||||
.clksel_reg = _clksel_reg, \
|
||||
.clksel_mask = _clksel_mask, \
|
||||
.clkdm_name = _clkdm_name, \
|
||||
}; \
|
||||
DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
|
||||
|
||||
#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
|
||||
_clksel_reg, _clksel_mask, \
|
||||
_enable_reg, _enable_bit, \
|
||||
_hwops, _parent_names, _ops) \
|
||||
static struct clk _name; \
|
||||
static struct clk_hw_omap _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.ops = _hwops, \
|
||||
.enable_reg = _enable_reg, \
|
||||
.enable_bit = _enable_bit, \
|
||||
.clksel = _clksel, \
|
||||
.clksel_reg = _clksel_reg, \
|
||||
.clksel_mask = _clksel_mask, \
|
||||
.clkdm_name = _clkdm_name, \
|
||||
}; \
|
||||
DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
|
||||
|
||||
#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
|
||||
_parent_ptr, _flags, \
|
||||
_clksel_reg, _clksel_mask) \
|
||||
static const struct clksel _name##_div[] = { \
|
||||
{ \
|
||||
.parent = _parent_ptr, \
|
||||
.rates = div31_1to31_rates \
|
||||
}, \
|
||||
{ .parent = NULL }, \
|
||||
}; \
|
||||
static struct clk _name; \
|
||||
static const char *_name##_parent_names[] = { \
|
||||
_parent_name, \
|
||||
}; \
|
||||
static struct clk_hw_omap _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.clksel = _name##_div, \
|
||||
.clksel_reg = _clksel_reg, \
|
||||
.clksel_mask = _clksel_mask, \
|
||||
.ops = &clkhwops_omap4_dpllmx, \
|
||||
}; \
|
||||
DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
|
||||
|
||||
/* struct clksel_rate.flags possibilities */
|
||||
#define RATE_IN_242X (1 << 0)
|
||||
#define RATE_IN_243X (1 << 1)
|
||||
@@ -229,22 +271,10 @@ struct dpll_data {
|
||||
#define CLOCK_CLKOUTX2 (1 << 5)
|
||||
|
||||
/**
|
||||
* struct clk - OMAP struct clk
|
||||
* struct clk_hw_omap - OMAP struct clk
|
||||
* @node: list_head connecting this clock into the full clock list
|
||||
* @ops: struct clkops * for this clock
|
||||
* @name: the name of the clock in the hardware (used in hwmod data and debug)
|
||||
* @parent: pointer to this clock's parent struct clk
|
||||
* @children: list_head connecting to the child clks' @sibling list_heads
|
||||
* @sibling: list_head connecting this clk to its parent clk's @children
|
||||
* @rate: current clock rate
|
||||
* @enable_reg: register to write to enable the clock (see @enable_bit)
|
||||
* @recalc: fn ptr that returns the clock's current rate
|
||||
* @set_rate: fn ptr that can change the clock's current rate
|
||||
* @round_rate: fn ptr that can round the clock's current rate
|
||||
* @init: fn ptr to do clock-specific initialization
|
||||
* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
|
||||
* @usecount: number of users that have requested this clock to be enabled
|
||||
* @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
|
||||
* @flags: see "struct clk.flags possibilities" above
|
||||
* @clksel_reg: for clksel clks, register va containing src/divisor select
|
||||
* @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
|
||||
@@ -258,39 +288,17 @@ struct dpll_data {
|
||||
* XXX @rate_offset, @src_offset should probably be removed and OMAP1
|
||||
* clock code converted to use clksel.
|
||||
*
|
||||
* XXX @usecount is poorly named. It should be "enable_count" or
|
||||
* something similar. "users" in the description refers to kernel
|
||||
* code (core code or drivers) that have called clk_enable() and not
|
||||
* yet called clk_disable(); the usecount of parent clocks is also
|
||||
* incremented by the clock code when clk_enable() is called on child
|
||||
* clocks and decremented by the clock code when clk_disable() is
|
||||
* called on child clocks.
|
||||
*
|
||||
* XXX @clkdm, @usecount, @children, @sibling should be marked for
|
||||
* internal use only.
|
||||
*
|
||||
* @children and @sibling are used to optimize parent-to-child clock
|
||||
* tree traversals. (child-to-parent traversals use @parent.)
|
||||
*
|
||||
* XXX The notion of the clock's current rate probably needs to be
|
||||
* separated from the clock's target rate.
|
||||
*/
|
||||
struct clk {
|
||||
|
||||
struct clk_hw_omap_ops;
|
||||
|
||||
struct clk_hw_omap {
|
||||
struct clk_hw hw;
|
||||
struct list_head node;
|
||||
const struct clkops *ops;
|
||||
const char *name;
|
||||
struct clk *parent;
|
||||
struct list_head children;
|
||||
struct list_head sibling; /* node for children */
|
||||
unsigned long rate;
|
||||
void __iomem *enable_reg;
|
||||
unsigned long (*recalc)(struct clk *);
|
||||
int (*set_rate)(struct clk *, unsigned long);
|
||||
long (*round_rate)(struct clk *, unsigned long);
|
||||
void (*init)(struct clk *);
|
||||
u8 enable_bit;
|
||||
s8 usecount;
|
||||
unsigned long fixed_rate;
|
||||
u8 fixed_div;
|
||||
void __iomem *enable_reg;
|
||||
u8 enable_bit;
|
||||
u8 flags;
|
||||
void __iomem *clksel_reg;
|
||||
u32 clksel_mask;
|
||||
@@ -298,42 +306,22 @@ struct clk {
|
||||
struct dpll_data *dpll_data;
|
||||
const char *clkdm_name;
|
||||
struct clockdomain *clkdm;
|
||||
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
|
||||
struct dentry *dent; /* For visible tree hierarchy */
|
||||
#endif
|
||||
const struct clk_hw_omap_ops *ops;
|
||||
};
|
||||
|
||||
struct clk_functions {
|
||||
int (*clk_enable)(struct clk *clk);
|
||||
void (*clk_disable)(struct clk *clk);
|
||||
long (*clk_round_rate)(struct clk *clk, unsigned long rate);
|
||||
int (*clk_set_rate)(struct clk *clk, unsigned long rate);
|
||||
int (*clk_set_parent)(struct clk *clk, struct clk *parent);
|
||||
void (*clk_allow_idle)(struct clk *clk);
|
||||
void (*clk_deny_idle)(struct clk *clk);
|
||||
void (*clk_disable_unused)(struct clk *clk);
|
||||
struct clk_hw_omap_ops {
|
||||
void (*find_idlest)(struct clk_hw_omap *oclk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit, u8 *idlest_val);
|
||||
void (*find_companion)(struct clk_hw_omap *oclk,
|
||||
void __iomem **other_reg,
|
||||
u8 *other_bit);
|
||||
void (*allow_idle)(struct clk_hw_omap *oclk);
|
||||
void (*deny_idle)(struct clk_hw_omap *oclk);
|
||||
};
|
||||
|
||||
extern int mpurate;
|
||||
|
||||
extern int clk_init(struct clk_functions *custom_clocks);
|
||||
extern void clk_preinit(struct clk *clk);
|
||||
extern int clk_register(struct clk *clk);
|
||||
extern void clk_reparent(struct clk *child, struct clk *parent);
|
||||
extern void clk_unregister(struct clk *clk);
|
||||
extern void propagate_rate(struct clk *clk);
|
||||
extern void recalculate_root_clocks(void);
|
||||
extern unsigned long followparent_recalc(struct clk *clk);
|
||||
extern void clk_enable_init_clocks(void);
|
||||
unsigned long omap_fixed_divisor_recalc(struct clk *clk);
|
||||
extern struct clk *omap_clk_get_by_name(const char *name);
|
||||
extern int omap_clk_enable_autoidle_all(void);
|
||||
extern int omap_clk_disable_autoidle_all(void);
|
||||
|
||||
extern const struct clkops clkops_null;
|
||||
|
||||
extern struct clk dummy_ck;
|
||||
|
||||
unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
|
||||
/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
|
||||
#define CORE_CLK_SRC_32K 0x0
|
||||
@@ -364,57 +352,62 @@ extern struct clk dummy_ck;
|
||||
/* DPLL Type and DCO Selection Flags */
|
||||
#define DPLL_J_TYPE 0x1
|
||||
|
||||
int omap2_clk_enable(struct clk *clk);
|
||||
void omap2_clk_disable(struct clk *clk);
|
||||
long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
|
||||
int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
|
||||
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
|
||||
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
|
||||
unsigned long omap3_dpll_recalc(struct clk *clk);
|
||||
unsigned long omap3_clkoutx2_recalc(struct clk *clk);
|
||||
void omap3_dpll_allow_idle(struct clk *clk);
|
||||
void omap3_dpll_deny_idle(struct clk *clk);
|
||||
u32 omap3_dpll_autoidle_read(struct clk *clk);
|
||||
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
|
||||
int omap3_noncore_dpll_enable(struct clk *clk);
|
||||
void omap3_noncore_dpll_disable(struct clk *clk);
|
||||
int omap4_dpllmx_gatectrl_read(struct clk *clk);
|
||||
void omap4_dpllmx_allow_gatectrl(struct clk *clk);
|
||||
void omap4_dpllmx_deny_gatectrl(struct clk *clk);
|
||||
long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
|
||||
unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
|
||||
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
|
||||
unsigned long *parent_rate);
|
||||
unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
|
||||
int omap3_noncore_dpll_enable(struct clk_hw *hw);
|
||||
void omap3_noncore_dpll_disable(struct clk_hw *hw);
|
||||
int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
|
||||
void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
|
||||
void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
|
||||
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
|
||||
void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
|
||||
void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
|
||||
unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
|
||||
unsigned long target_rate,
|
||||
unsigned long *parent_rate);
|
||||
|
||||
#ifdef CONFIG_OMAP_RESET_CLOCKS
|
||||
void omap2_clk_disable_unused(struct clk *clk);
|
||||
#else
|
||||
#define omap2_clk_disable_unused NULL
|
||||
#endif
|
||||
|
||||
void omap2_init_clk_clkdm(struct clk *clk);
|
||||
void omap2_init_clk_clkdm(struct clk_hw *clk);
|
||||
void __init omap2_clk_disable_clkdm_control(void);
|
||||
|
||||
/* clkt_clksel.c public functions */
|
||||
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
|
||||
u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
|
||||
unsigned long target_rate,
|
||||
u32 *new_div);
|
||||
void omap2_init_clksel_parent(struct clk *clk);
|
||||
unsigned long omap2_clksel_recalc(struct clk *clk);
|
||||
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
|
||||
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
|
||||
int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
|
||||
u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
|
||||
unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
|
||||
long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
|
||||
unsigned long *parent_rate);
|
||||
int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
|
||||
|
||||
/* clkt_iclk.c public functions */
|
||||
extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
|
||||
extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
|
||||
extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
|
||||
extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
|
||||
|
||||
u32 omap2_get_dpll_rate(struct clk *clk);
|
||||
void omap2_init_dpll_parent(struct clk *clk);
|
||||
u8 omap2_init_dpll_parent(struct clk_hw *hw);
|
||||
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
|
||||
|
||||
int omap2_dflt_clk_enable(struct clk *clk);
|
||||
void omap2_dflt_clk_disable(struct clk *clk);
|
||||
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
|
||||
int omap2_dflt_clk_enable(struct clk_hw *hw);
|
||||
void omap2_dflt_clk_disable(struct clk_hw *hw);
|
||||
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
|
||||
void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
|
||||
void __iomem **other_reg,
|
||||
u8 *other_bit);
|
||||
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
|
||||
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit, u8 *idlest_val);
|
||||
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
|
||||
int omap2_clk_enable_autoidle_all(void);
|
||||
int omap2_clk_disable_autoidle_all(void);
|
||||
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
|
||||
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
|
||||
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
|
||||
const char *core_ck_name,
|
||||
@@ -432,28 +425,38 @@ extern const struct clksel_rate gpt_32k_rates[];
|
||||
extern const struct clksel_rate gpt_sys_rates[];
|
||||
extern const struct clksel_rate gfx_l3_rates[];
|
||||
extern const struct clksel_rate dsp_ick_rates[];
|
||||
extern struct clk dummy_ck;
|
||||
|
||||
extern const struct clkops clkops_omap2_iclk_dflt_wait;
|
||||
extern const struct clkops clkops_omap2_iclk_dflt;
|
||||
extern const struct clkops clkops_omap2_iclk_idle_only;
|
||||
extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
|
||||
extern const struct clkops clkops_omap2xxx_dpll_ops;
|
||||
extern const struct clkops clkops_omap3_noncore_dpll_ops;
|
||||
extern const struct clkops clkops_omap3_core_dpll_ops;
|
||||
extern const struct clkops clkops_omap4_dpllmx_ops;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
|
||||
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
|
||||
extern const struct clk_hw_omap_ops clkhwops_iclk;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_apll54;
|
||||
extern const struct clk_hw_omap_ops clkhwops_apll96;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
|
||||
|
||||
/* clksel_rate blocks shared between OMAP44xx and AM33xx */
|
||||
extern const struct clksel_rate div_1_0_rates[];
|
||||
extern const struct clksel_rate div3_1to4_rates[];
|
||||
extern const struct clksel_rate div_1_1_rates[];
|
||||
extern const struct clksel_rate div_1_2_rates[];
|
||||
extern const struct clksel_rate div_1_3_rates[];
|
||||
extern const struct clksel_rate div_1_4_rates[];
|
||||
extern const struct clksel_rate div31_1to31_rates[];
|
||||
|
||||
/* clocks shared between various OMAP SoCs */
|
||||
extern struct clk virt_19200000_ck;
|
||||
extern struct clk virt_26000000_ck;
|
||||
|
||||
extern int am33xx_clk_init(void);
|
||||
|
||||
extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
|
||||
extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user