apfs/linux-apfs
0
0
Fork 0
mirror of https://github.com/linux-apfs/linux-apfs.git synced 2026-05-01 15:00:59 -07:00
Code Issues Packages Projects Releases Wiki Activity

ARM: meson: DTS: enable L2 cache

Browse Source 
This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
This commit is contained in:
Beniamino Galvani
2014-11-18 15:30:35 +01:00
committed by Carlo Caione
parent aeff05a39a
commit 550ab390d7
3 changed files with 13 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/boot/dts/meson.dtsi
+7
View File
@@ -50,6 +50,13 @@
/ { / {
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
L2: l2-cache-controller@c4200000 {
compatible = "arm,pl310-cache";
reg = <0xc4200000 0x1000>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@c4301000 { gic: interrupt-controller@c4301000 {
compatible = "arm,cortex-a9-gic"; compatible = "arm,cortex-a9-gic";
reg = <0xc4301000 0x1000>, reg = <0xc4301000 0x1000>,
arch/arm/boot/dts/meson6.dtsi
+2
View File
@@ -60,12 +60,14 @@
cpu@200 { cpu@200 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x200>; reg = <0x200>;
}; };
cpu@201 { cpu@201 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x201>; reg = <0x201>;
}; };
}; };
arch/arm/boot/dts/meson8.dtsi
+4
View File
@@ -58,24 +58,28 @@
cpu@200 { cpu@200 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x200>; reg = <0x200>;
}; };
cpu@201 { cpu@201 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x201>; reg = <0x201>;
}; };
cpu@202 { cpu@202 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x202>; reg = <0x202>;
}; };
cpu@203 { cpu@203 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x203>; reg = <0x203>;
}; };
}; };