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i2c: Delete the broken i2c-ite bus driver
The rest of the ITE8172 support was already removed from MIPS tree. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Acked-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jean Delvare
committed by
Jean Delvare
Jean Delvare
parent
36cfb5ccfa
commit
51fd554b65
@@ -38,17 +38,6 @@ config I2C_ALGOPCA
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This support is also available as a module. If so, the module
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will be called i2c-algo-pca.
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config I2C_ALGOITE
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tristate "ITE I2C Algorithm"
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depends on MIPS_ITE8172 && I2C
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help
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This supports the use of the ITE8172 I2C interface found on some MIPS
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systems. Say Y if you have one of these. You should also say Y for
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the ITE I2C peripheral driver support below.
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This support is also available as a module. If so, the module
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will be called i2c-algo-ite.
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config I2C_ALGO8XX
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tristate "MPC8xx CPM I2C interface"
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depends on 8xx && I2C
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@@ -5,7 +5,6 @@
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obj-$(CONFIG_I2C_ALGOBIT) += i2c-algo-bit.o
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obj-$(CONFIG_I2C_ALGOPCF) += i2c-algo-pcf.o
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obj-$(CONFIG_I2C_ALGOPCA) += i2c-algo-pca.o
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obj-$(CONFIG_I2C_ALGOITE) += i2c-algo-ite.o
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obj-$(CONFIG_I2C_ALGO_SGI) += i2c-algo-sgi.o
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ifeq ($(CONFIG_I2C_DEBUG_ALGO),y)
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File diff suppressed because it is too large
Load Diff
@@ -1,117 +0,0 @@
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/*
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--------------------------------------------------------------------
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i2c-ite.h: Global defines for the I2C controller on board the
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ITE MIPS processor.
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--------------------------------------------------------------------
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Hai-Pao Fan, MontaVista Software, Inc.
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hpfan@mvista.com or source@mvista.com
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Copyright 2001 MontaVista Software Inc.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef I2C_ITE_H
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#define I2C_ITE_H 1
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#include <asm/it8172/it8172.h>
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/* I2C Registers */
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#define ITE_I2CHCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x30
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#define ITE_I2CHSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x34
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#define ITE_I2CSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x38
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#define ITE_I2CSSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x3c
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#define ITE_I2CCKCNT IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x48
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#define ITE_I2CSHDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x4c
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#define ITE_I2CRSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x50
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#define ITE_I2CPSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x54
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#define ITE_I2CFDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x70
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#define ITE_I2CFBCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x74
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#define ITE_I2CFCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x78
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#define ITE_I2CFSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x7c
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/* Host Control Register ITE_I2CHCR */
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#define ITE_I2CHCR_HCE 0x01 /* Enable I2C Host Controller */
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#define ITE_I2CHCR_IE 0x02 /* Enable the interrupt after completing
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the current transaction */
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#define ITE_I2CHCR_CP_W 0x00 /* bit2-4 000 - Write */
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#define ITE_I2CHCR_CP_R 0x08 /* 010 - Current address read */
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#define ITE_I2CHCR_CP_S 0x10 /* 100 - Sequential read */
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#define ITE_I2CHCR_ST 0x20 /* Initiates the I2C host controller to execute
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the command and send the data programmed in
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all required registers to I2C bus */
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#define ITE_CMD ITE_I2CHCR_HCE | ITE_I2CHCR_IE | ITE_I2CHCR_ST
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#define ITE_WRITE ITE_CMD | ITE_I2CHCR_CP_W
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#define ITE_READ ITE_CMD | ITE_I2CHCR_CP_R
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#define ITE_SREAD ITE_CMD | ITE_I2CHCR_CP_S
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/* Host Status Register ITE_I2CHSR */
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#define ITE_I2CHSR_DB 0x01 /* Device is busy, receives NACK response except
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in the first and last bytes */
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#define ITE_I2CHSR_DNE 0x02 /* Target address on I2C bus does not exist */
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#define ITE_I2CHSR_TDI 0x04 /* R/W Transaction on I2C bus was completed */
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#define ITE_I2CHSR_HB 0x08 /* Host controller is processing transactions */
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#define ITE_I2CHSR_FER 0x10 /* Error occurs in the FIFO */
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/* Slave Address Register ITE_I2CSAR */
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#define ITE_I2CSAR_SA_MASK 0xfe /* Target I2C device address */
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#define ITE_I2CSAR_ASO 0x0100 /* Output 1/0 to I2CAS port when the
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next slave address is addressed */
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/* Slave Sub-address Register ITE_I2CSSAR */
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#define ITE_I2CSSAR_SUBA_MASK 0xff /* Target I2C device sub-address */
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/* Clock Counter Register ITE_I2CCKCNT */
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#define ITE_I2CCKCNT_STOP 0x00 /* stop I2C clock */
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#define ITE_I2CCKCNT_HPCC_MASK 0x7f /* SCL high period counter */
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#define ITE_I2CCKCNT_LPCC_MASK 0x7f00 /* SCL low period counter */
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/* START Hold Time Register ITE_I2CSHDR */
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/* value is counted based on 16 MHz internal clock */
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#define ITE_I2CSHDR_FM 0x0a /* START condition at fast mode */
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#define ITE_I2CSHDR_SM 0x47 /* START contition at standard mode */
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/* (Repeated) START Setup Time Register ITE_I2CRSUR */
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/* value is counted based on 16 MHz internal clock */
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#define ITE_I2CRSUR_FM 0x0a /* repeated START condition at fast mode */
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#define ITE_I2CRSUR_SM 0x50 /* repeated START condition at standard mode */
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/* STOP setup Time Register ITE_I2CPSUR */
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/* FIFO Data Register ITE_I2CFDR */
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#define ITE_I2CFDR_MASK 0xff
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/* FIFO Byte Count Register ITE_I2CFBCR */
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#define ITE_I2CFBCR_MASK 0x3f
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/* FIFO Control Register ITE_I2CFCR */
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#define ITE_I2CFCR_FLUSH 0x01 /* Flush FIFO and reset the FIFO point
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and I2CFSR */
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/* FIFO Status Register ITE_I2CFSR */
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#define ITE_I2CFSR_FO 0x01 /* FIFO is overrun when write */
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#define ITE_I2CFSR_FU 0x02 /* FIFO is underrun when read */
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#define ITE_I2CFSR_FF 0x04 /* FIFO is full when write */
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#define ITE_I2CFSR_FE 0x08 /* FIFO is empty when read */
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#endif /* I2C_ITE_H */
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@@ -209,18 +209,6 @@ config I2C_ISA
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tristate
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depends on I2C
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config I2C_ITE
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tristate "ITE I2C Adapter"
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depends on I2C && MIPS_ITE8172
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select I2C_ALGOITE
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help
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This supports the ITE8172 I2C peripheral found on some MIPS
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systems. Say Y if you have one of these. You should also say Y for
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the ITE I2C driver algorithm support above.
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This support is also available as a module. If so, the module
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will be called i2c-ite.
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config I2C_IXP4XX
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tristate "IXP4xx GPIO-Based I2C Interface"
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depends on I2C && ARCH_IXP4XX
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@@ -16,7 +16,6 @@ obj-$(CONFIG_I2C_I810) += i2c-i810.o
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obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
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obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
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obj-$(CONFIG_I2C_ISA) += i2c-isa.o
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obj-$(CONFIG_I2C_ITE) += i2c-ite.o
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obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o
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obj-$(CONFIG_I2C_IXP4XX) += i2c-ixp4xx.o
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obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
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@@ -1,278 +0,0 @@
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/*
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-------------------------------------------------------------------------
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i2c-adap-ite.c i2c-hw access for the IIC peripheral on the ITE MIPS system
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-------------------------------------------------------------------------
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Hai-Pao Fan, MontaVista Software, Inc.
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hpfan@mvista.com or source@mvista.com
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Copyright 2001 MontaVista Software Inc.
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----------------------------------------------------------------------------
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This file was highly leveraged from i2c-elektor.c, which was created
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by Simon G. Vogl and Hans Berglund:
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Copyright (C) 1995-97 Simon G. Vogl
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1998-99 Hans Berglund
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* ------------------------------------------------------------------------- */
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/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
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Frodo Looijaard <frodol@dds.nl> */
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/wait.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-ite.h>
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#include <linux/i2c-adap-ite.h>
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#include "../i2c-ite.h"
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#define DEFAULT_BASE 0x14014030
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#define ITE_IIC_IO_SIZE 0x40
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#define DEFAULT_IRQ 0
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#define DEFAULT_CLOCK 0x1b0e /* default 16MHz/(27+14) = 400KHz */
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#define DEFAULT_OWN 0x55
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static int base;
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static int irq;
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static int clock;
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static int own;
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static struct iic_ite gpi;
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static wait_queue_head_t iic_wait;
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static int iic_pending;
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static spinlock_t lock;
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/* ----- local functions ---------------------------------------------- */
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static void iic_ite_setiic(void *data, int ctl, short val)
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{
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unsigned long j = jiffies + 10;
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pr_debug(" Write 0x%02x to 0x%x\n",(unsigned short)val, ctl&0xff);
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#ifdef DEBUG
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while (time_before(jiffies, j))
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schedule();
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#endif
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outw(val,ctl);
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}
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static short iic_ite_getiic(void *data, int ctl)
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{
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short val;
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val = inw(ctl);
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pr_debug("Read 0x%02x from 0x%x\n",(unsigned short)val, ctl&0xff);
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return (val);
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}
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/* Return our slave address. This is the address
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* put on the I2C bus when another master on the bus wants to address us
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* as a slave
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*/
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static int iic_ite_getown(void *data)
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{
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return (gpi.iic_own);
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}
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static int iic_ite_getclock(void *data)
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{
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return (gpi.iic_clock);
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}
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/* Put this process to sleep. We will wake up when the
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* IIC controller interrupts.
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*/
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static void iic_ite_waitforpin(void) {
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DEFINE_WAIT(wait);
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int timeout = 2;
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unsigned long flags;
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/* If interrupts are enabled (which they are), then put the process to
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* sleep. This process will be awakened by two events -- either the
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* the IIC peripheral interrupts or the timeout expires.
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* If interrupts are not enabled then delay for a reasonable amount
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* of time and return.
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*/
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if (gpi.iic_irq > 0) {
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spin_lock_irqsave(&lock, flags);
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if (iic_pending == 0) {
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spin_unlock_irqrestore(&lock, flags);
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prepare_to_wait(&iic_wait, &wait, TASK_INTERRUPTIBLE);
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if (schedule_timeout(timeout*HZ)) {
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spin_lock_irqsave(&lock, flags);
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if (iic_pending == 1) {
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iic_pending = 0;
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}
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spin_unlock_irqrestore(&lock, flags);
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}
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finish_wait(&iic_wait, &wait);
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} else {
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iic_pending = 0;
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spin_unlock_irqrestore(&lock, flags);
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}
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} else {
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udelay(100);
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}
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}
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static irqreturn_t iic_ite_handler(int this_irq, void *dev_id)
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{
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spin_lock(&lock);
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iic_pending = 1;
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spin_unlock(&lock);
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wake_up_interruptible(&iic_wait);
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return IRQ_HANDLED;
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}
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/* Lock the region of memory where I/O registers exist. Request our
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* interrupt line and register its associated handler.
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*/
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static int iic_hw_resrc_init(void)
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{
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if (!request_region(gpi.iic_base, ITE_IIC_IO_SIZE, "i2c"))
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return -ENODEV;
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if (gpi.iic_irq <= 0)
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return 0;
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if (request_irq(gpi.iic_irq, iic_ite_handler, 0, "ITE IIC", 0) < 0)
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gpi.iic_irq = 0;
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else
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enable_irq(gpi.iic_irq);
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return 0;
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}
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static void iic_ite_release(void)
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{
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if (gpi.iic_irq > 0) {
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disable_irq(gpi.iic_irq);
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free_irq(gpi.iic_irq, 0);
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}
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release_region(gpi.iic_base , 2);
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}
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/* ------------------------------------------------------------------------
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* Encapsulate the above functions in the correct operations structure.
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* This is only done when more than one hardware adapter is supported.
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*/
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static struct i2c_algo_iic_data iic_ite_data = {
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NULL,
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iic_ite_setiic,
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iic_ite_getiic,
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iic_ite_getown,
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iic_ite_getclock,
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iic_ite_waitforpin,
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80, 80, 100, /* waits, timeout */
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};
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static struct i2c_adapter iic_ite_ops = {
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.owner = THIS_MODULE,
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.id = I2C_HW_I_IIC,
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.algo_data = &iic_ite_data,
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.name = "ITE IIC adapter",
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};
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/* Called when the module is loaded. This function starts the
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* cascade of calls up through the hierarchy of i2c modules (i.e. up to the
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* algorithm layer and into to the core layer)
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*/
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static int __init iic_ite_init(void)
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{
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struct iic_ite *piic = &gpi;
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printk(KERN_INFO "Initialize ITE IIC adapter module\n");
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if (base == 0)
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piic->iic_base = DEFAULT_BASE;
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else
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piic->iic_base = base;
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if (irq == 0)
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piic->iic_irq = DEFAULT_IRQ;
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else
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piic->iic_irq = irq;
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if (clock == 0)
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piic->iic_clock = DEFAULT_CLOCK;
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else
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piic->iic_clock = clock;
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if (own == 0)
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piic->iic_own = DEFAULT_OWN;
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else
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piic->iic_own = own;
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iic_ite_data.data = (void *)piic;
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init_waitqueue_head(&iic_wait);
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spin_lock_init(&lock);
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if (iic_hw_resrc_init() == 0) {
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if (i2c_iic_add_bus(&iic_ite_ops) < 0)
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return -ENODEV;
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} else {
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return -ENODEV;
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}
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printk(KERN_INFO " found device at %#x irq %d.\n",
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piic->iic_base, piic->iic_irq);
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return 0;
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}
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||||
|
||||
|
||||
static void iic_ite_exit(void)
|
||||
{
|
||||
i2c_iic_del_bus(&iic_ite_ops);
|
||||
iic_ite_release();
|
||||
}
|
||||
|
||||
/* If modules is NOT defined when this file is compiled, then the MODULE_*
|
||||
* macros will resolve to nothing
|
||||
*/
|
||||
MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
|
||||
MODULE_DESCRIPTION("I2C-Bus adapter routines for ITE IIC bus adapter");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
module_param(base, int, 0);
|
||||
module_param(irq, int, 0);
|
||||
module_param(clock, int, 0);
|
||||
module_param(own, int, 0);
|
||||
|
||||
|
||||
/* Called when module is loaded or when kernel is initialized.
|
||||
* If MODULES is defined when this file is compiled, then this function will
|
||||
* resolve to init_module (the function called when insmod is invoked for a
|
||||
* module). Otherwise, this function is called early in the boot, when the
|
||||
* kernel is intialized. Check out /include/init.h to see how this works.
|
||||
*/
|
||||
module_init(iic_ite_init);
|
||||
|
||||
/* Resolves to module_cleanup when MODULES is defined. */
|
||||
module_exit(iic_ite_exit);
|
||||
Reference in New Issue
Block a user