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Merge branch 'linux-2.6' into for-2.6.22
This commit is contained in:
Paul Mackerras
@@ -17,9 +17,6 @@
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# define __kernel_extbl(val, shift) __builtin_alpha_extbl(val, shift)
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# define __kernel_extwl(val, shift) __builtin_alpha_extwl(val, shift)
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# define __kernel_cmpbge(a, b) __builtin_alpha_cmpbge(a, b)
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# define __kernel_cttz(x) __builtin_ctzl(x)
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# define __kernel_ctlz(x) __builtin_clzl(x)
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# define __kernel_ctpop(x) __builtin_popcountl(x)
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#else
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# define __kernel_insbl(val, shift) \
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({ unsigned long __kir; \
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@@ -49,17 +46,39 @@
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({ unsigned long __kir; \
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__asm__("cmpbge %r2,%1,%0" : "=r"(__kir) : "rI"(b), "rJ"(a)); \
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__kir; })
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#endif
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#ifdef __alpha_cix__
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# if __GNUC__ == 3 && __GNUC_MINOR__ >= 4 || __GNUC__ > 3
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# define __kernel_cttz(x) __builtin_ctzl(x)
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# define __kernel_ctlz(x) __builtin_clzl(x)
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# define __kernel_ctpop(x) __builtin_popcountl(x)
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# else
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# define __kernel_cttz(x) \
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({ unsigned long __kir; \
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__asm__("cttz %1,%0" : "=r"(__kir) : "r"(x)); \
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__kir; })
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# define __kernel_ctlz(x) \
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({ unsigned long __kir; \
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__asm__("ctlz %1,%0" : "=r"(__kir) : "r"(x)); \
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__kir; })
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# define __kernel_ctpop(x) \
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({ unsigned long __kir; \
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__asm__("ctpop %1,%0" : "=r"(__kir) : "r"(x)); \
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__kir; })
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# endif
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#else
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# define __kernel_cttz(x) \
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({ unsigned long __kir; \
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__asm__("cttz %1,%0" : "=r"(__kir) : "r"(x)); \
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__asm__(".arch ev67; cttz %1,%0" : "=r"(__kir) : "r"(x)); \
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__kir; })
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# define __kernel_ctlz(x) \
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({ unsigned long __kir; \
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__asm__("ctlz %1,%0" : "=r"(__kir) : "r"(x)); \
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__asm__(".arch ev67; ctlz %1,%0" : "=r"(__kir) : "r"(x)); \
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__kir; })
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# define __kernel_ctpop(x) \
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({ unsigned long __kir; \
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__asm__("ctpop %1,%0" : "=r"(__kir) : "r"(x)); \
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__asm__(".arch ev67; ctpop %1,%0" : "=r"(__kir) : "r"(x)); \
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__kir; })
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#endif
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@@ -78,16 +97,20 @@
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#else
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#define __kernel_ldbu(mem) \
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({ unsigned char __kir; \
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__asm__("ldbu %0,%1" : "=r"(__kir) : "m"(mem)); \
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__asm__(".arch ev56; \
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ldbu %0,%1" : "=r"(__kir) : "m"(mem)); \
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__kir; })
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#define __kernel_ldwu(mem) \
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({ unsigned short __kir; \
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__asm__("ldwu %0,%1" : "=r"(__kir) : "m"(mem)); \
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__asm__(".arch ev56; \
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ldwu %0,%1" : "=r"(__kir) : "m"(mem)); \
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__kir; })
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#define __kernel_stb(val,mem) \
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__asm__("stb %1,%0" : "=m"(mem) : "r"(val))
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#define __kernel_stw(val,mem) \
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__asm__("stw %1,%0" : "=m"(mem) : "r"(val))
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#define __kernel_stb(val,mem) \
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__asm__(".arch ev56; \
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stb %1,%0" : "=m"(mem) : "r"(val))
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#define __kernel_stw(val,mem) \
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__asm__(".arch ev56; \
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stw %1,%0" : "=m"(mem) : "r"(val))
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#endif
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#ifdef __KERNEL__
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@@ -72,6 +72,8 @@
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*
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*/
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#define MCPCIA_MAX_HOSES 4
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#define MCPCIA_MID(m) ((unsigned long)(m) << 33)
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/* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively.
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@@ -113,6 +113,7 @@ static inline unsigned long virt_to_bus(void *address)
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unsigned long bus = phys + __direct_map_base;
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return phys <= __direct_map_size ? bus : 0;
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}
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#define isa_virt_to_bus virt_to_bus
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static inline void *bus_to_virt(unsigned long address)
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{
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@@ -52,6 +52,8 @@
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#define SO_PEERSEC 30
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#define SO_PASSSEC 34
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#define SO_TIMESTAMPNS 35
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#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
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/* Security levels - as per NRL IPv6 - don't actually do anything */
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#define SO_SECURITY_AUTHENTICATION 19
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@@ -10,6 +10,7 @@
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#define SIOCSPGRP _IOW('s', 8, pid_t)
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#define SIOCGPGRP _IOR('s', 9, pid_t)
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#define SIOCGSTAMP 0x8906 /* Get stamp - linux-specific */
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#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
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#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
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#endif /* _ASM_ALPHA_SOCKIOS_H */
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@@ -61,8 +61,6 @@ extern void * __memsetw(void *dest, unsigned short, size_t count);
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? __constant_c_memset((s),0x0001000100010001UL*(unsigned short)(c),(n)) \
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: __memsetw((s),(c),(n)))
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extern int strcasecmp(const char *, const char *);
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#endif /* __KERNEL__ */
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#endif /* __ALPHA_STRING_H__ */
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@@ -2,6 +2,7 @@
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#define __ASM_ARM_DIV64
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#include <asm/system.h>
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#include <linux/types.h>
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/*
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* The semantics of do_div() are:
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@@ -223,4 +224,6 @@
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#endif
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||||
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extern uint64_t div64_64(uint64_t dividend, uint64_t divisor);
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#endif
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@@ -49,5 +49,7 @@
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#define SO_PEERSEC 31
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#define SO_PASSSEC 34
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#define SO_TIMESTAMPNS 35
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#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
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#endif /* _ASM_SOCKET_H */
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@@ -7,6 +7,7 @@
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#define FIOGETOWN 0x8903
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#define SIOCGPGRP 0x8904
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#define SIOCATMARK 0x8905
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#define SIOCGSTAMP 0x8906 /* Get stamp */
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#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
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#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
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#endif
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@@ -49,5 +49,7 @@
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|
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#define SO_PEERSEC 31
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#define SO_PASSSEC 34
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#define SO_TIMESTAMPNS 35
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#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
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||||
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#endif /* _ASM_SOCKET_H */
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@@ -7,6 +7,7 @@
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#define FIOGETOWN 0x8903
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#define SIOCGPGRP 0x8904
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#define SIOCATMARK 0x8905
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#define SIOCGSTAMP 0x8906 /* Get stamp */
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#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
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#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
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#endif
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@@ -0,0 +1,39 @@
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#ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
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#define __ASM_AVR32_ARCH_AT32AP_IO_H
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/* For "bizarre" halfword swapping */
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#include <linux/byteorder/swabb.h>
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#if defined(CONFIG_AP7000_32_BIT_SMC)
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# define __swizzle_addr_b(addr) (addr ^ 3UL)
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# define __swizzle_addr_w(addr) (addr ^ 2UL)
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# define __swizzle_addr_l(addr) (addr)
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# define ioswabb(a, x) (x)
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# define ioswabw(a, x) (x)
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# define ioswabl(a, x) (x)
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# define __mem_ioswabb(a, x) (x)
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# define __mem_ioswabw(a, x) swab16(x)
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# define __mem_ioswabl(a, x) swab32(x)
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#elif defined(CONFIG_AP7000_16_BIT_SMC)
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# define __swizzle_addr_b(addr) (addr ^ 1UL)
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# define __swizzle_addr_w(addr) (addr)
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# define __swizzle_addr_l(addr) (addr)
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# define ioswabb(a, x) (x)
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# define ioswabw(a, x) (x)
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# define ioswabl(a, x) swahw32(x)
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# define __mem_ioswabb(a, x) (x)
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# define __mem_ioswabw(a, x) swab16(x)
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# define __mem_ioswabl(a, x) swahb32(x)
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#else
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# define __swizzle_addr_b(addr) (addr)
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# define __swizzle_addr_w(addr) (addr)
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# define __swizzle_addr_l(addr) (addr)
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# define ioswabb(a, x) (x)
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# define ioswabw(a, x) swab16(x)
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# define ioswabl(a, x) swab32(x)
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# define __mem_ioswabb(a, x) (x)
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# define __mem_ioswabw(a, x) (x)
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# define __mem_ioswabl(a, x) (x)
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#endif
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#endif /* __ASM_AVR32_ARCH_AT32AP_IO_H */
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@@ -47,11 +47,33 @@ struct smc_config {
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*/
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unsigned int nwe_controlled:1;
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/*
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* 0: NWAIT is disabled
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* 1: Reserved
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* 2: NWAIT is frozen mode
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* 3: NWAIT in ready mode
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*/
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unsigned int nwait_mode:2;
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/*
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* 0: Byte select access type
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* 1: Byte write access type
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*/
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unsigned int byte_write:1;
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/*
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* Number of clock cycles before data is released after
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* the rising edge of the read controlling signal
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*
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* Total cycles from SMC is tdf_cycles + 1
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*/
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unsigned int tdf_cycles:4;
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|
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/*
|
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* 0: TDF optimization disabled
|
||||
* 1: TDF optimization enabled
|
||||
*/
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unsigned int tdf_mode:1;
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};
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|
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extern int smc_set_configuration(int cs, const struct smc_config *config);
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|
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@@ -0,0 +1,112 @@
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/*
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* Copyright (C) 2007 Atmel Corporation
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
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|
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#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
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#define _ASM_AVR32_ARCH_AT32AP_TIME_H
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#include <linux/platform_device.h>
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|
||||
extern struct irqaction timer_irqaction;
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extern struct platform_device at32_systc0_device;
|
||||
extern void local_timer_interrupt(int irq, void *dev_id);
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#define TIMER_BCR 0x000000c0
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#define TIMER_BCR_SYNC 0
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#define TIMER_BMR 0x000000c4
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#define TIMER_BMR_TC0XC0S 0
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#define TIMER_BMR_TC1XC1S 2
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#define TIMER_BMR_TC2XC2S 4
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#define TIMER_CCR 0x00000000
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#define TIMER_CCR_CLKDIS 1
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#define TIMER_CCR_CLKEN 0
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#define TIMER_CCR_SWTRG 2
|
||||
#define TIMER_CMR 0x00000004
|
||||
#define TIMER_CMR_ABETRG 10
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#define TIMER_CMR_ACPA 16
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||||
#define TIMER_CMR_ACPC 18
|
||||
#define TIMER_CMR_AEEVT 20
|
||||
#define TIMER_CMR_ASWTRG 22
|
||||
#define TIMER_CMR_BCPB 24
|
||||
#define TIMER_CMR_BCPC 26
|
||||
#define TIMER_CMR_BEEVT 28
|
||||
#define TIMER_CMR_BSWTRG 30
|
||||
#define TIMER_CMR_BURST 4
|
||||
#define TIMER_CMR_CLKI 3
|
||||
#define TIMER_CMR_CPCDIS 7
|
||||
#define TIMER_CMR_CPCSTOP 6
|
||||
#define TIMER_CMR_CPCTRG 14
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||||
#define TIMER_CMR_EEVT 10
|
||||
#define TIMER_CMR_EEVTEDG 8
|
||||
#define TIMER_CMR_ENETRG 12
|
||||
#define TIMER_CMR_ETRGEDG 8
|
||||
#define TIMER_CMR_LDBDIS 7
|
||||
#define TIMER_CMR_LDBSTOP 6
|
||||
#define TIMER_CMR_LDRA 16
|
||||
#define TIMER_CMR_LDRB 18
|
||||
#define TIMER_CMR_TCCLKS 0
|
||||
#define TIMER_CMR_WAVE 15
|
||||
#define TIMER_CMR_WAVSEL 13
|
||||
#define TIMER_CV 0x00000010
|
||||
#define TIMER_CV_CV 0
|
||||
#define TIMER_IDR 0x00000028
|
||||
#define TIMER_IDR_COVFS 0
|
||||
#define TIMER_IDR_CPAS 2
|
||||
#define TIMER_IDR_CPBS 3
|
||||
#define TIMER_IDR_CPCS 4
|
||||
#define TIMER_IDR_ETRGS 7
|
||||
#define TIMER_IDR_LDRAS 5
|
||||
#define TIMER_IDR_LDRBS 6
|
||||
#define TIMER_IDR_LOVRS 1
|
||||
#define TIMER_IER 0x00000024
|
||||
#define TIMER_IER_COVFS 0
|
||||
#define TIMER_IER_CPAS 2
|
||||
#define TIMER_IER_CPBS 3
|
||||
#define TIMER_IER_CPCS 4
|
||||
#define TIMER_IER_ETRGS 7
|
||||
#define TIMER_IER_LDRAS 5
|
||||
#define TIMER_IER_LDRBS 6
|
||||
#define TIMER_IER_LOVRS 1
|
||||
#define TIMER_IMR 0x0000002c
|
||||
#define TIMER_IMR_COVFS 0
|
||||
#define TIMER_IMR_CPAS 2
|
||||
#define TIMER_IMR_CPBS 3
|
||||
#define TIMER_IMR_CPCS 4
|
||||
#define TIMER_IMR_ETRGS 7
|
||||
#define TIMER_IMR_LDRAS 5
|
||||
#define TIMER_IMR_LDRBS 6
|
||||
#define TIMER_IMR_LOVRS 1
|
||||
#define TIMER_RA 0x00000014
|
||||
#define TIMER_RA_RA 0
|
||||
#define TIMER_RB 0x00000018
|
||||
#define TIMER_RB_RB 0
|
||||
#define TIMER_RC 0x0000001c
|
||||
#define TIMER_RC_RC 0
|
||||
#define TIMER_SR 0x00000020
|
||||
#define TIMER_SR_CLKSTA 16
|
||||
#define TIMER_SR_COVFS 0
|
||||
#define TIMER_SR_CPAS 2
|
||||
#define TIMER_SR_CPBS 3
|
||||
#define TIMER_SR_CPCS 4
|
||||
#define TIMER_SR_ETRGS 7
|
||||
#define TIMER_SR_LDRAS 5
|
||||
#define TIMER_SR_LDRBS 6
|
||||
#define TIMER_SR_LOVRS 1
|
||||
#define TIMER_SR_MTIOA 17
|
||||
#define TIMER_SR_MTIOB 18
|
||||
|
||||
/* Bit manipulation macros */
|
||||
#define TIMER_BIT(name) (1 << TIMER_##name)
|
||||
#define TIMER_BF(name,value) ((value) << TIMER_##name)
|
||||
|
||||
/* Register access macros */
|
||||
#define timer_read(port,instance,reg) \
|
||||
__raw_readl(port + (0x40 * instance) + TIMER_##reg)
|
||||
#define timer_write(port,instance,reg,value) \
|
||||
__raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
|
||||
|
||||
#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
|
||||
@@ -173,7 +173,7 @@ static inline int atomic_sub_if_positive(int i, atomic_t *v)
|
||||
}
|
||||
|
||||
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
|
||||
#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
|
||||
#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
|
||||
|
||||
#define atomic_sub(i, v) (void)atomic_sub_return(i, v)
|
||||
#define atomic_add(i, v) (void)atomic_add_return(i, v)
|
||||
|
||||
+40
-14
@@ -18,27 +18,53 @@
|
||||
|
||||
#ifdef CONFIG_DEBUG_BUGVERBOSE
|
||||
|
||||
#define BUG() \
|
||||
do { \
|
||||
asm volatile(".hword %0\n\t" \
|
||||
".hword %1\n\t" \
|
||||
".long %2" \
|
||||
: \
|
||||
: "n"(AVR32_BUG_OPCODE), \
|
||||
"i"(__LINE__), "X"(__FILE__)); \
|
||||
} while (0)
|
||||
#define _BUG_OR_WARN(flags) \
|
||||
asm volatile( \
|
||||
"1: .hword %0\n" \
|
||||
" .section __bug_table,\"a\",@progbits\n" \
|
||||
"2: .long 1b\n" \
|
||||
" .long %1\n" \
|
||||
" .short %2\n" \
|
||||
" .short %3\n" \
|
||||
" .org 2b + %4\n" \
|
||||
" .previous" \
|
||||
: \
|
||||
: "i"(AVR32_BUG_OPCODE), "i"(__FILE__), \
|
||||
"i"(__LINE__), "i"(flags), \
|
||||
"i"(sizeof(struct bug_entry)))
|
||||
|
||||
#else
|
||||
|
||||
#define BUG() \
|
||||
do { \
|
||||
asm volatile(".hword %0\n\t" \
|
||||
: : "n"(AVR32_BUG_OPCODE)); \
|
||||
} while (0)
|
||||
#define _BUG_OR_WARN(flags) \
|
||||
asm volatile( \
|
||||
"1: .hword %0\n" \
|
||||
" .section __bug_table,\"a\",@progbits\n" \
|
||||
"2: .long 1b\n" \
|
||||
" .short %1\n" \
|
||||
" .org 2b + %2\n" \
|
||||
" .previous" \
|
||||
: \
|
||||
: "i"(AVR32_BUG_OPCODE), "i"(flags), \
|
||||
"i"(sizeof(struct bug_entry)))
|
||||
|
||||
#endif /* CONFIG_DEBUG_BUGVERBOSE */
|
||||
|
||||
#define BUG() \
|
||||
do { \
|
||||
_BUG_OR_WARN(0); \
|
||||
for (;;); \
|
||||
} while (0)
|
||||
|
||||
#define WARN_ON(condition) \
|
||||
({ \
|
||||
typeof(condition) __ret_warn_on = (condition); \
|
||||
if (unlikely(__ret_warn_on)) \
|
||||
_BUG_OR_WARN(BUGFLAG_WARNING); \
|
||||
unlikely(__ret_warn_on); \
|
||||
})
|
||||
|
||||
#define HAVE_ARCH_BUG
|
||||
#define HAVE_ARCH_WARN_ON
|
||||
|
||||
#endif /* CONFIG_BUG */
|
||||
|
||||
|
||||
+173
-153
@@ -1,13 +1,15 @@
|
||||
#ifndef __ASM_AVR32_IO_H
|
||||
#define __ASM_AVR32_IO_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#include <asm/arch/io.h>
|
||||
|
||||
/* virt_to_phys will only work when address is in P1 or P2 */
|
||||
static __inline__ unsigned long virt_to_phys(volatile void *address)
|
||||
{
|
||||
@@ -36,104 +38,215 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
|
||||
extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
|
||||
extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
|
||||
|
||||
static inline void writeb(unsigned char b, volatile void __iomem *addr)
|
||||
static inline void __raw_writeb(u8 v, volatile void __iomem *addr)
|
||||
{
|
||||
*(volatile unsigned char __force *)addr = b;
|
||||
*(volatile u8 __force *)addr = v;
|
||||
}
|
||||
static inline void writew(unsigned short b, volatile void __iomem *addr)
|
||||
static inline void __raw_writew(u16 v, volatile void __iomem *addr)
|
||||
{
|
||||
*(volatile unsigned short __force *)addr = b;
|
||||
*(volatile u16 __force *)addr = v;
|
||||
}
|
||||
static inline void writel(unsigned int b, volatile void __iomem *addr)
|
||||
static inline void __raw_writel(u32 v, volatile void __iomem *addr)
|
||||
{
|
||||
*(volatile unsigned int __force *)addr = b;
|
||||
*(volatile u32 __force *)addr = v;
|
||||
}
|
||||
#define __raw_writeb writeb
|
||||
#define __raw_writew writew
|
||||
#define __raw_writel writel
|
||||
|
||||
static inline unsigned char readb(const volatile void __iomem *addr)
|
||||
static inline u8 __raw_readb(const volatile void __iomem *addr)
|
||||
{
|
||||
return *(const volatile unsigned char __force *)addr;
|
||||
return *(const volatile u8 __force *)addr;
|
||||
}
|
||||
static inline unsigned short readw(const volatile void __iomem *addr)
|
||||
static inline u16 __raw_readw(const volatile void __iomem *addr)
|
||||
{
|
||||
return *(const volatile unsigned short __force *)addr;
|
||||
return *(const volatile u16 __force *)addr;
|
||||
}
|
||||
static inline unsigned int readl(const volatile void __iomem *addr)
|
||||
static inline u32 __raw_readl(const volatile void __iomem *addr)
|
||||
{
|
||||
return *(const volatile unsigned int __force *)addr;
|
||||
return *(const volatile u32 __force *)addr;
|
||||
}
|
||||
#define __raw_readb readb
|
||||
#define __raw_readw readw
|
||||
#define __raw_readl readl
|
||||
|
||||
#define writesb(p, d, l) __raw_writesb((unsigned int)p, d, l)
|
||||
#define writesw(p, d, l) __raw_writesw((unsigned int)p, d, l)
|
||||
#define writesl(p, d, l) __raw_writesl((unsigned int)p, d, l)
|
||||
/* Convert I/O port address to virtual address */
|
||||
#ifndef __io
|
||||
# define __io(p) ((void *)phys_to_uncached(p))
|
||||
#endif
|
||||
|
||||
#define readsb(p, d, l) __raw_readsb((unsigned int)p, d, l)
|
||||
#define readsw(p, d, l) __raw_readsw((unsigned int)p, d, l)
|
||||
#define readsl(p, d, l) __raw_readsl((unsigned int)p, d, l)
|
||||
/*
|
||||
* Not really sure about the best way to slow down I/O on
|
||||
* AVR32. Defining it as a no-op until we have an actual test case.
|
||||
*/
|
||||
#define SLOW_DOWN_IO do { } while (0)
|
||||
|
||||
#define __BUILD_MEMORY_SINGLE(pfx, bwl, type) \
|
||||
static inline void \
|
||||
pfx##write##bwl(type val, volatile void __iomem *addr) \
|
||||
{ \
|
||||
volatile type *__addr; \
|
||||
type __val; \
|
||||
\
|
||||
__addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
|
||||
__val = pfx##ioswab##bwl(__addr, val); \
|
||||
\
|
||||
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
|
||||
\
|
||||
*__addr = __val; \
|
||||
} \
|
||||
\
|
||||
static inline type pfx##read##bwl(const volatile void __iomem *addr) \
|
||||
{ \
|
||||
volatile type *__addr; \
|
||||
type __val; \
|
||||
\
|
||||
__addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
|
||||
\
|
||||
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
|
||||
\
|
||||
__val = *__addr; \
|
||||
return pfx##ioswab##bwl(__addr, __val); \
|
||||
}
|
||||
|
||||
#define __BUILD_IOPORT_SINGLE(pfx, bwl, type, p, slow) \
|
||||
static inline void pfx##out##bwl##p(type val, unsigned long port) \
|
||||
{ \
|
||||
volatile type *__addr; \
|
||||
type __val; \
|
||||
\
|
||||
__addr = __io(__swizzle_addr_##bwl(port)); \
|
||||
__val = pfx##ioswab##bwl(__addr, val); \
|
||||
\
|
||||
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
|
||||
\
|
||||
*__addr = __val; \
|
||||
slow; \
|
||||
} \
|
||||
\
|
||||
static inline type pfx##in##bwl##p(unsigned long port) \
|
||||
{ \
|
||||
volatile type *__addr; \
|
||||
type __val; \
|
||||
\
|
||||
__addr = __io(__swizzle_addr_##bwl(port)); \
|
||||
\
|
||||
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
|
||||
\
|
||||
__val = *__addr; \
|
||||
slow; \
|
||||
\
|
||||
return pfx##ioswab##bwl(__addr, __val); \
|
||||
}
|
||||
|
||||
#define __BUILD_MEMORY_PFX(bus, bwl, type) \
|
||||
__BUILD_MEMORY_SINGLE(bus, bwl, type)
|
||||
|
||||
#define BUILDIO_MEM(bwl, type) \
|
||||
__BUILD_MEMORY_PFX(, bwl, type) \
|
||||
__BUILD_MEMORY_PFX(__mem_, bwl, type)
|
||||
|
||||
#define __BUILD_IOPORT_PFX(bus, bwl, type) \
|
||||
__BUILD_IOPORT_SINGLE(bus, bwl, type, ,) \
|
||||
__BUILD_IOPORT_SINGLE(bus, bwl, type, _p, SLOW_DOWN_IO)
|
||||
|
||||
#define BUILDIO_IOPORT(bwl, type) \
|
||||
__BUILD_IOPORT_PFX(, bwl, type) \
|
||||
__BUILD_IOPORT_PFX(__mem_, bwl, type)
|
||||
|
||||
BUILDIO_MEM(b, u8)
|
||||
BUILDIO_MEM(w, u16)
|
||||
BUILDIO_MEM(l, u32)
|
||||
|
||||
BUILDIO_IOPORT(b, u8)
|
||||
BUILDIO_IOPORT(w, u16)
|
||||
BUILDIO_IOPORT(l, u32)
|
||||
|
||||
#define readb_relaxed readb
|
||||
#define readw_relaxed readw
|
||||
#define readl_relaxed readl
|
||||
|
||||
#define __BUILD_MEMORY_STRING(bwl, type) \
|
||||
static inline void writes##bwl(volatile void __iomem *addr, \
|
||||
const void *data, unsigned int count) \
|
||||
{ \
|
||||
const type *__data = data; \
|
||||
\
|
||||
while (count--) \
|
||||
__mem_write##bwl(*__data++, addr); \
|
||||
} \
|
||||
\
|
||||
static inline void reads##bwl(const volatile void __iomem *addr, \
|
||||
void *data, unsigned int count) \
|
||||
{ \
|
||||
type *__data = data; \
|
||||
\
|
||||
while (count--) \
|
||||
*__data++ = __mem_read##bwl(addr); \
|
||||
}
|
||||
|
||||
#define __BUILD_IOPORT_STRING(bwl, type) \
|
||||
static inline void outs##bwl(unsigned long port, const void *data, \
|
||||
unsigned int count) \
|
||||
{ \
|
||||
const type *__data = data; \
|
||||
\
|
||||
while (count--) \
|
||||
__mem_out##bwl(*__data++, port); \
|
||||
} \
|
||||
\
|
||||
static inline void ins##bwl(unsigned long port, void *data, \
|
||||
unsigned int count) \
|
||||
{ \
|
||||
type *__data = data; \
|
||||
\
|
||||
while (count--) \
|
||||
*__data++ = __mem_in##bwl(port); \
|
||||
}
|
||||
|
||||
#define BUILDSTRING(bwl, type) \
|
||||
__BUILD_MEMORY_STRING(bwl, type) \
|
||||
__BUILD_IOPORT_STRING(bwl, type)
|
||||
|
||||
BUILDSTRING(b, u8)
|
||||
BUILDSTRING(w, u16)
|
||||
BUILDSTRING(l, u32)
|
||||
|
||||
/*
|
||||
* io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be
|
||||
*/
|
||||
#ifndef ioread8
|
||||
|
||||
#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; })
|
||||
#define ioread8(p) ((unsigned int)readb(p))
|
||||
|
||||
#define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
|
||||
#define ioread16be(p) ({ unsigned int __v = be16_to_cpu(__raw_readw(p)); __v; })
|
||||
#define ioread16(p) ((unsigned int)readw(p))
|
||||
#define ioread16be(p) ((unsigned int)__raw_readw(p))
|
||||
|
||||
#define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
|
||||
#define ioread32be(p) ({ unsigned int __v = be32_to_cpu(__raw_readl(p)); __v; })
|
||||
#define ioread32(p) ((unsigned int)readl(p))
|
||||
#define ioread32be(p) ((unsigned int)__raw_readl(p))
|
||||
|
||||
#define iowrite8(v,p) __raw_writeb(v, p)
|
||||
#define iowrite8(v,p) writeb(v, p)
|
||||
|
||||
#define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p)
|
||||
#define iowrite16be(v,p) __raw_writew(cpu_to_be16(v), p)
|
||||
#define iowrite16(v,p) writew(v, p)
|
||||
#define iowrite16be(v,p) __raw_writew(v, p)
|
||||
|
||||
#define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p)
|
||||
#define iowrite32be(v,p) __raw_writel(cpu_to_be32(v), p)
|
||||
#define iowrite32(v,p) writel(v, p)
|
||||
#define iowrite32be(v,p) __raw_writel(v, p)
|
||||
|
||||
#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
|
||||
#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
|
||||
#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
|
||||
#define ioread8_rep(p,d,c) readsb(p,d,c)
|
||||
#define ioread16_rep(p,d,c) readsw(p,d,c)
|
||||
#define ioread32_rep(p,d,c) readsl(p,d,c)
|
||||
|
||||
#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
|
||||
#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
|
||||
#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
|
||||
#define iowrite8_rep(p,s,c) writesb(p,s,c)
|
||||
#define iowrite16_rep(p,s,c) writesw(p,s,c)
|
||||
#define iowrite32_rep(p,s,c) writesl(p,s,c)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* These two are only here because ALSA _thinks_ it needs them...
|
||||
*/
|
||||
static inline void memcpy_fromio(void * to, const volatile void __iomem *from,
|
||||
unsigned long count)
|
||||
{
|
||||
char *p = to;
|
||||
while (count) {
|
||||
count--;
|
||||
*p = readb(from);
|
||||
p++;
|
||||
from++;
|
||||
}
|
||||
memcpy(to, (const void __force *)from, count);
|
||||
}
|
||||
|
||||
static inline void memcpy_toio(volatile void __iomem *to, const void * from,
|
||||
unsigned long count)
|
||||
{
|
||||
const char *p = from;
|
||||
while (count) {
|
||||
count--;
|
||||
writeb(*p, to);
|
||||
p++;
|
||||
to++;
|
||||
}
|
||||
memcpy((void __force *)to, from, count);
|
||||
}
|
||||
|
||||
static inline void memset_io(volatile void __iomem *addr, unsigned char val,
|
||||
@@ -142,99 +255,8 @@ static inline void memset_io(volatile void __iomem *addr, unsigned char val,
|
||||
memset((void __force *)addr, val, count);
|
||||
}
|
||||
|
||||
/*
|
||||
* Bad read/write accesses...
|
||||
*/
|
||||
extern void __readwrite_bug(const char *fn);
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
/* Convert I/O port address to virtual address */
|
||||
#define __io(p) ((void __iomem *)phys_to_uncached(p))
|
||||
|
||||
/*
|
||||
* IO port access primitives
|
||||
* -------------------------
|
||||
*
|
||||
* The AVR32 doesn't have special IO access instructions; all IO is memory
|
||||
* mapped. Note that these are defined to perform little endian accesses
|
||||
* only. Their primary purpose is to access PCI and ISA peripherals.
|
||||
*
|
||||
* Note that for a big endian machine, this implies that the following
|
||||
* big endian mode connectivity is in place.
|
||||
*
|
||||
* The machine specific io.h include defines __io to translate an "IO"
|
||||
* address to a memory address.
|
||||
*
|
||||
* Note that we prevent GCC re-ordering or caching values in expressions
|
||||
* by introducing sequence points into the in*() definitions. Note that
|
||||
* __raw_* do not guarantee this behaviour.
|
||||
*
|
||||
* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
|
||||
*/
|
||||
#define outb(v, p) __raw_writeb(v, __io(p))
|
||||
#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
|
||||
#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
|
||||
|
||||
#define inb(p) __raw_readb(__io(p))
|
||||
#define inw(p) le16_to_cpu(__raw_readw(__io(p)))
|
||||
#define inl(p) le32_to_cpu(__raw_readl(__io(p)))
|
||||
|
||||
static inline void __outsb(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
outb(*(u8 *)addr, port);
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __insb(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
*(u8 *)addr = inb(port);
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __outsw(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
outw(*(u16 *)addr, port);
|
||||
addr += 2;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __insw(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
*(u16 *)addr = inw(port);
|
||||
addr += 2;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __outsl(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
outl(*(u32 *)addr, port);
|
||||
addr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __insl(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
*(u32 *)addr = inl(port);
|
||||
addr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
#define outsb(port, addr, count) __outsb(port, addr, count)
|
||||
#define insb(port, addr, count) __insb(port, addr, count)
|
||||
#define outsw(port, addr, count) __outsw(port, addr, count)
|
||||
#define insw(port, addr, count) __insw(port, addr, count)
|
||||
#define outsl(port, addr, count) __outsl(port, addr, count)
|
||||
#define insl(port, addr, count) __insl(port, addr, count)
|
||||
|
||||
extern void __iomem *__ioremap(unsigned long offset, size_t size,
|
||||
unsigned long flags);
|
||||
extern void __iounmap(void __iomem *addr);
|
||||
@@ -292,6 +314,4 @@ extern void __iounmap(void __iomem *addr);
|
||||
*/
|
||||
#define xlate_dev_kmem_ptr(p) p
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ASM_AVR32_IO_H */
|
||||
|
||||
@@ -40,6 +40,14 @@ enum tlb_config {
|
||||
TLB_INVALID
|
||||
};
|
||||
|
||||
#define AVR32_FEATURE_RMW (1 << 0)
|
||||
#define AVR32_FEATURE_DSP (1 << 1)
|
||||
#define AVR32_FEATURE_SIMD (1 << 2)
|
||||
#define AVR32_FEATURE_OCD (1 << 3)
|
||||
#define AVR32_FEATURE_PCTR (1 << 4)
|
||||
#define AVR32_FEATURE_JAVA (1 << 5)
|
||||
#define AVR32_FEATURE_FPU (1 << 6)
|
||||
|
||||
struct avr32_cpuinfo {
|
||||
struct clk *clk;
|
||||
unsigned long loops_per_jiffy;
|
||||
@@ -48,6 +56,7 @@ struct avr32_cpuinfo {
|
||||
unsigned short arch_revision;
|
||||
unsigned short cpu_revision;
|
||||
enum tlb_config tlb_config;
|
||||
unsigned long features;
|
||||
|
||||
struct cache_info icache;
|
||||
struct cache_info dcache;
|
||||
@@ -125,10 +134,10 @@ extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
|
||||
#define thread_saved_pc(tsk) ((tsk)->thread.cpu_context.pc)
|
||||
|
||||
struct pt_regs;
|
||||
void show_trace(struct task_struct *task, unsigned long *stack,
|
||||
struct pt_regs *regs);
|
||||
|
||||
extern unsigned long get_wchan(struct task_struct *p);
|
||||
extern void show_regs_log_lvl(struct pt_regs *regs, const char *log_lvl);
|
||||
extern void show_stack_log_lvl(struct task_struct *tsk, unsigned long sp,
|
||||
struct pt_regs *regs, const char *log_lvl);
|
||||
|
||||
#define KSTK_EIP(tsk) ((tsk)->thread.cpu_context.pc)
|
||||
#define KSTK_ESP(tsk) ((tsk)->thread.cpu_context.ksp)
|
||||
|
||||
@@ -124,19 +124,12 @@ struct tagtable {
|
||||
#define for_each_tag(t,base) \
|
||||
for (t = base; t->hdr.size; t = tag_next(t))
|
||||
|
||||
extern struct tag_mem_range *mem_phys;
|
||||
extern struct tag_mem_range *mem_reserved;
|
||||
extern struct tag_mem_range *mem_ramdisk;
|
||||
|
||||
extern struct tag *bootloader_tags;
|
||||
|
||||
extern void setup_bootmem(void);
|
||||
extern void setup_processor(void);
|
||||
extern void board_setup_fbmem(unsigned long fbmem_start,
|
||||
unsigned long fbmem_size);
|
||||
extern resource_size_t fbmem_start;
|
||||
extern resource_size_t fbmem_size;
|
||||
|
||||
/* Chip-specific hook to enable the use of SDRAM */
|
||||
void chip_enable_sdram(void);
|
||||
void setup_processor(void);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
|
||||
@@ -49,5 +49,7 @@
|
||||
|
||||
#define SO_PEERSEC 31
|
||||
#define SO_PASSSEC 34
|
||||
#define SO_TIMESTAMPNS 35
|
||||
#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
|
||||
|
||||
#endif /* __ASM_AVR32_SOCKET_H */
|
||||
|
||||
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Reference in New Issue
Block a user